For i.MX7 U-Boot initializes the system counter. On i.MX6 Barebox is
often used which doesn't initialize the counter. With this patch, we try
to auto-detect whether the counter is initialized or not and do the
initialization ourself if necessary.
Closes#3869
This allows an application to get the registers of the LPSPI. That is
usefull for applications that want to use DMA for a very specialized and
highly optimized communication.
Update #4180
Note: The changes have been done with portability in mind. The driver
should (in theory) be able to replace the original one in the MPC BSPs
too. For full compatibility an adaption layer and especially a test
would be necessary. Because both are missing, don't integrate it into
the MPC BSP now.
Update #4180
RTEMS OFW is a FDT only implementation of the OpenFirmWare
interface. This API is created to be compatible with FreeBSD
OpenFirmWare interface. The main intention is to make
porting of FreeBSD drivers to RTEMS easier.
Most functions implemented have an direct one-one mapping
with the original OFW API and some extra auxiliary functions
were implemented to make working with device trees easier in
RTEMS.
Update #3784
This BSP supports the Arm Fixed Virtual Platform. Only the Cortex-R52
processor configuration is supported by the BSP. It should be easy to
add support for other variants if needed.
Update #4202.
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
The arm_cp15 function for accessing the current CPU index is specific
to ARMv7 while this header is used for ARMv8 as well. Instead, use a
generic accessor that is part of the standard CPU API.
Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.
Update #4202.
Currently, zynq-uart code is always built and has some requirements for
BSPs that use it. Instead of making all BSPs satisfy that requirement or
working around it by setting defaults, this moves the zynq-uart code
into its own spec build object so it can be included if needed.
This adds a BSP family that runs on the Xilinx Ultrascale+ MPSOC
(ZynqMP) family of chips. It is configured to be usable on the Qemu
ZCU102 machine definition and should be almost trivially portable to
ZynqMP development boards and custom hardware. It is also configured to
be usable with libbsd.
The zynq-uart set_attributes implementation was configured to always
return false which causes spconsole01 to fail. This restores the
disabled implementation which sets the baud rate registers
appropriately and allows spconsole01 to pass. This also expands the
set_attributes functionality to allow setting of the stop bits,
character width, and parity.
Also start interrupt server tasks on processors which do not have a
scheduler. Applications may dynamically manage processors using
rtems_scheduler_remove_processor() and rtems_scheduler_add_processor().
