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bsps: Move ARM GICv2 driver to bsps/shared

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This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
This commit is contained in:
Kinsey Moore
2020-10-29 13:40:54 -05:00
committed by Joel Sherrill
parent f0859573f9
commit a151ee167e
18 changed files with 33 additions and 32 deletions
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2
bsps/aarch64/shared/irq/irq-arm-gicv3-aarch64.c → bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
View File

@@ -60,5 +60,5 @@ void arm_interrupt_facility_set_exception_handler(void)
void bsp_interrupt_dispatch(void)
{
gicv3_interrupt_dispatch();
gicvx_interrupt_dispatch();
}

2
bsps/arm/shared/irq/irq-arm-gicv3-aarch32.c → bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
View File

@@ -57,5 +57,5 @@ void arm_interrupt_facility_set_exception_handler(void)
void bsp_interrupt_dispatch(void)
{
gicv3_interrupt_dispatch();
gicvx_interrupt_dispatch();
}

4
bsps/include/dev/irq/arm-gic-irq.h
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@@ -122,10 +122,10 @@ void arm_interrupt_facility_set_exception_handler(void);
void arm_interrupt_handler_dispatch(rtems_vector_number vector);
/**
* This is the GICv3 interrupt dispatcher that is to be called from the
* This is the GICv1/GICv2/GICv3 interrupt dispatcher that is to be called from the
* architecture-specific implementation of the IRQ handler.
*/
void gicv3_interrupt_dispatch(void);
void gicvx_interrupt_dispatch(void);
static inline uint32_t arm_gic_irq_processor_count(void)
{

17
bsps/arm/shared/irq/irq-gic.c → bsps/shared/dev/irq/arm-gicv2.c
View File

@@ -14,10 +14,6 @@
#include <dev/irq/arm-gic.h>
#include <rtems/score/armv4.h>
#include <libcpu/arm-cp15.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>
#include <bsp/start.h>
@@ -53,7 +49,7 @@
#define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
#endif
void bsp_interrupt_dispatch(void)
void gicvx_interrupt_dispatch(void)
{
volatile gic_cpuif *cpuif = GIC_CPUIF;
uint32_t icciar = cpuif->icciar;
@@ -61,11 +57,7 @@ void bsp_interrupt_dispatch(void)
rtems_vector_number spurious = 1023;
if (vector != spurious) {
uint32_t psr = _ARMV4_Status_irq_enable();
bsp_interrupt_handler_dispatch(vector);
_ARMV4_Status_restore(psr);
arm_interrupt_handler_dispatch(vector);
cpuif->icceoir = icciar;
}
@@ -117,10 +109,7 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
uint32_t id_count = get_id_count(dist);
uint32_t id;
arm_cp15_set_exception_handler(
ARM_EXCEPTION_IRQ,
_ARMV4_Exception_interrupt
);
arm_interrupt_facility_set_exception_handler();
for (id = 0; id < id_count; id += 32) {
#ifdef BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0

2
bsps/shared/dev/irq/arm-gicv3.c
View File

@@ -134,7 +134,7 @@
#define ARM_GIC_REDIST ((volatile gic_redist *) BSP_ARM_GIC_REDIST_BASE)
#define ARM_GIC_SGI_PPI (((volatile gic_sgi_ppi *) ((char*)BSP_ARM_GIC_REDIST_BASE + (1 << 16))))
void gicv3_interrupt_dispatch(void)
void gicvx_interrupt_dispatch(void)
{
uint32_t icciar = READ_SR(ICC_IAR1);
rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);