bsps: Use header file for GIC architecture support

This avoids a function call overhead in the interrupt dispatching.

Update #4202.
This commit is contained in:
Sebastian Huber
2020-12-22 13:00:27 +01:00
parent 23d9223ad3
commit 9f3a08ef2d
21 changed files with 36 additions and 33 deletions

View File

@@ -34,10 +34,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <dev/irq/arm-gic-irq.h>
#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
#include <rtems/score/cpu.h>
#include <bsp/irq-generic.h>
void arm_interrupt_handler_dispatch(rtems_vector_number vector)
#ifdef __cplusplus
extern "C" {
#endif
static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
{
uint32_t interrupt_level = _CPU_ISR_Get_level();
AArch64_interrupt_enable(1);
@@ -45,7 +53,7 @@ void arm_interrupt_handler_dispatch(rtems_vector_number vector)
_CPU_ISR_Set_level(interrupt_level);
}
void arm_interrupt_facility_set_exception_handler(void)
static inline void arm_interrupt_facility_set_exception_handler(void)
{
AArch64_set_exception_handler(
AARCH64_EXCEPTION_SPx_IRQ,
@@ -56,3 +64,9 @@ void arm_interrupt_facility_set_exception_handler(void)
_AArch64_Exception_interrupt_nest
);
}
#ifdef __cplusplus
}
#endif
#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */

View File

@@ -34,12 +34,18 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
#define _RTEMS_DEV_IRQ_ARM_GIC_ARM_H
#include <libcpu/arm-cp15.h>
#include <dev/irq/arm-gic-irq.h>
#include <bsp/irq-generic.h>
#include <rtems/score/armv4.h>
void arm_interrupt_handler_dispatch(rtems_vector_number vector)
#ifdef __cplusplus
extern "C" {
#endif
static inline void arm_interrupt_handler_dispatch(rtems_vector_number vector)
{
uint32_t psr = _ARMV4_Status_irq_enable();
bsp_interrupt_handler_dispatch(vector);
@@ -47,10 +53,16 @@ void arm_interrupt_handler_dispatch(rtems_vector_number vector)
_ARMV4_Status_restore(psr);
}
void arm_interrupt_facility_set_exception_handler(void)
static inline void arm_interrupt_facility_set_exception_handler(void)
{
arm_cp15_set_exception_handler(
ARM_EXCEPTION_IRQ,
_ARMV4_Exception_interrupt
);
}
#ifdef __cplusplus
}
#endif
#endif /* _RTEMS_DEV_IRQ_ARM_GIC_ARM_H */

View File

@@ -97,19 +97,6 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq(
return sc;
}
/**
* This architecture-specific function sets the exception vector for handling
* IRQs.
*/
void arm_interrupt_facility_set_exception_handler(void);
/**
* This architecture-specific function dispatches a triggered IRQ.
*
* @param[in] vector The vector on which the IRQ occurred.
*/
void arm_interrupt_handler_dispatch(rtems_vector_number vector);
uint32_t arm_gic_irq_processor_count(void);
void arm_gic_irq_initialize_secondary_cpu(void);

View File

@@ -13,6 +13,7 @@
*/
#include <dev/irq/arm-gic.h>
#include <dev/irq/arm-gic-arch.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>

View File

@@ -26,6 +26,7 @@
*/
#include <dev/irq/arm-gic.h>
#include <dev/irq/arm-gic-arch.h>
#include <bsp/irq.h>
#include <bsp/irq-generic.h>

View File

@@ -63,7 +63,6 @@ endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# Console
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c

View File

@@ -52,7 +52,6 @@ endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# Console
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c

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@@ -57,7 +57,6 @@ endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# Console
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios-init.c

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@@ -36,7 +36,6 @@ librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/cache/cache-cp15.c
# irq
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# console
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/xen/console/console.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c

View File

@@ -56,7 +56,6 @@ endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# Console
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c

View File

@@ -56,7 +56,6 @@ endif
# IRQ
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/irq/irq-default-handler.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/irq/arm-gicv2.c
librtemsbsp_a_SOURCES += ../../../../../../bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
# Console
librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/serial/console-termios.c

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@@ -30,7 +30,6 @@ source:
- bsps/shared/start/sbrk.c
- bsps/shared/dev/irq/arm-gicv3.c
- bsps/shared/irq/irq-default-handler.c
- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
- bsps/shared/dev/btimer/btimer-cpucounter.c
- bsps/shared/dev/clock/arm-generic-timer.c
- bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c

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@@ -14,6 +14,7 @@ install:
- bsps/include/dev/clock/arm-generic-timer.h
- destination: ${BSP_INCLUDEDIR}/dev/irq
source:
- bsps/aarch64/include/dev/irq/arm-gic-arch.h
- bsps/include/dev/irq/arm-gic-irq.h
- bsps/include/dev/irq/arm-gic-regs.h
- bsps/include/dev/irq/arm-gic-tm27.h

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@@ -29,7 +29,6 @@ source:
- bsps/shared/start/bspreset-arm-psci.c
- bsps/shared/start/sbrk.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c
- bsps/shared/irq/irq-default-handler.c
- bsps/shared/dev/btimer/btimer-cpucounter.c
- bsps/shared/dev/clock/arm-generic-timer.c

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@@ -129,7 +129,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/shared/dev/btimer/btimer-stub.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c

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@@ -37,6 +37,7 @@ install:
- bsps/arm/include/bsp/start.h
- destination: ${BSP_INCLUDEDIR}/dev/irq
source:
- bsps/arm/include/dev/irq/arm-gic-arch.h
- bsps/include/dev/irq/arm-gic-irq.h
- bsps/include/dev/irq/arm-gic-regs.h
- bsps/include/dev/irq/arm-gic-tm27.h

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@@ -97,7 +97,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/shared/dev/btimer/btimer-stub.c
- bsps/shared/dev/getentropy/getentropy-cpucounter.c

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@@ -68,7 +68,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/arm/shared/fb/arm-pl111.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/serial/arm-pl050.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/shared/dev/btimer/btimer-stub.c

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@@ -64,7 +64,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/arm/xen/console/console.c
- bsps/arm/xen/start/bspstart.c

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@@ -25,7 +25,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/arm/xilinx-zynq/console/console-config.c
- bsps/arm/xilinx-zynq/console/console-init.c

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@@ -82,7 +82,6 @@ source:
- bsps/arm/shared/cp15/arm-cp15-set-exception-handler.c
- bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
- bsps/shared/dev/irq/arm-gicv2.c
- bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c
- bsps/arm/shared/start/bsp-start-memcpy.S
- bsps/arm/xilinx-zynqmp/console/console-config.c
- bsps/arm/xilinx-zynqmp/start/bspreset.c