forked from Imagelibrary/rtems
bsps/arm: Add arm-data-cache-loop-set-way.h
This makes it possible to reuse this loop. Update #4202.
This commit is contained in:
Sebastian Huber
96
bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
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96
bsps/arm/include/dev/cache/arm-data-cache-loop-set-way.h
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@@ -0,0 +1,96 @@
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/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2018 embedded brains GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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.macro ARM_DATA_CACHE_LOOP_SET_WAY CRM
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/* Get cache levels (LoC) from CLIDR */
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mrc p15, 1, r1, c0, c0, 1
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mov r2, r1, lsr #24
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ands r2, r2, #0x7
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beq 5f
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/* Start with level 0 */
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mov r3, #0
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/* Flush level specified by r3 */
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1:
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/* Check cache type and skip this level if there is no data cache */
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add r4, r3, r3, lsl #1
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lsr r5, r1, r4
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and r5, r5, #0x7
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cmp r5, #2
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blt 4f
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/* Read CCSIDR */
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lsl r4, r3, #1
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mcr p15, 2, r4, c0, c0, 0
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isb
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mrc p15, 1, r5, c0, c0, 0
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/* Get cache line power */
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and r6, r5, #0x7
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add r6, r6, #4
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/* Get ways minus one */
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mov r7, #0x3ff
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ands r7, r7, r5, lsr #3
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/* Get way shift */
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clz r8, r7
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/* Get sets minus one */
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mov r9, #0x7fff
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ands r9, r9, r5, lsr #13
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/* Loop over ways */
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2:
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mov r10, r9
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/* Loop over sets */
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3:
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orr r11, r4, r7, lsl r8
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orr r11, r11, r10, lsl r6
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/* Cache operation by set and way */
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mcr p15, 0, r11, c7, \CRM, 2
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subs r10, r10, #1
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bge 3b
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subs r7, r7, #1
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bge 2b
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/* Next level */
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4:
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add r3, r3, #1
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cmp r2, r3
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bgt 1b
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/* Done */
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5:
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.endm
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71
bsps/arm/shared/cache/cache-v7ar-disable-data.S
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71
bsps/arm/shared/cache/cache-v7ar-disable-data.S
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@@ -27,7 +27,9 @@
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#include <rtems/asm.h>
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#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 65 || __ARM_ARCH_PROFILE == 82)
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#include <dev/cache/arm-data-cache-loop-set-way.h>
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#if __ARM_ARCH >= 7 && (__ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R')
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.globl rtems_cache_disable_data
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.syntax unified
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@@ -53,68 +55,13 @@ FUNCTION_ENTRY(rtems_cache_disable_data)
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mcr p15, 0, r1, c1, c0, 0
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isb
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/* Get cache levels (LoC) from CLIDR */
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mrc p15, 1, r1, c0, c0, 1
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mov r2, r1, lsr #24
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ands r2, r2, #0x7
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beq .Ldone
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/*
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* Clean and invalidate the sets and ways of all data or unified cache
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* levels using DCCISW (Data Cache line Clean and Invalidate by
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* Set/Way).
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*/
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ARM_DATA_CACHE_LOOP_SET_WAY c14
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/* Start with level 0 */
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mov r3, #0
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.Lflush_level:
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/* Flush level specified by r3 */
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/* Check cache type */
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add r4, r3, r3, lsl #1
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lsr r5, r1, r4
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and r5, r5, #0x7
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cmp r5, #2
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blt .Lno_data_cache
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/* Read CCSIDR */
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lsl r4, r3, #1
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mcr p15, 2, r4, c0, c0, 0
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isb
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mrc p15, 1, r5, c0, c0, 0
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/* Get cache line power */
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and r6, r5, #0x7
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add r6, r6, #4
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/* Get ways minus one */
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mov r7, #0x3ff
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ands r7, r7, r5, lsr #3
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/* Get way shift */
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clz r8, r7
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/* Get sets minus one */
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mov r9, #0x7fff
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ands r9, r9, r5, lsr #13
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.Lloop_over_ways:
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mov r10, r9
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.Lloop_over_sets:
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orr r11, r4, r7, lsl r8
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orr r11, r11, r10, lsl r6
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/* Clean and invalidate by set and way */
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mcr p15, 0, r11, c7, c14, 2
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subs r10, r10, #1
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bge .Lloop_over_sets
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subs r7, r7, #1
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bge .Lloop_over_ways
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.Lno_data_cache:
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/* Next level */
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add r3, r3, #1
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cmp r2, r3
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bgt .Lflush_level
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.Ldone:
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/* Restore interrupts */
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msr CPSR_fc, r0
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