bsps/arm: Invalidate branch predictors earlier

Make sure the branch predictors are invalidated before the first branch
is executed.

Update #4202.
This commit is contained in:
Sebastian Huber
2020-12-21 07:29:41 +01:00
parent 272534eb72
commit 76a1a53780
5 changed files with 11 additions and 5 deletions

View File

@@ -141,8 +141,6 @@ BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
(volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
uint32_t cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
arm_cp15_branch_predictor_invalidate_all();
if (cpu_id == 0) {
arm_a9mpcore_start_scu_enable(scu);
}

View File

@@ -110,7 +110,6 @@ void BSP_START_TEXT_SECTION bsp_start_hook_0(void)
rtems_cache_invalidate_entire_data();
}
rtems_cache_invalidate_entire_instruction();
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();

View File

@@ -181,6 +181,17 @@ _start:
mov r13, #0
#endif
#if __ARM_ARCH >= 7
/*
* Write to BPIALL (Branch Predictor Invalidate All) to invalidate all
* branch predictors. There is no need to use BPIALLIS (Branch
* Predictor Invalidate All, Inner Shareable) since this code is
* executed on all processors used by RTEMS.
*/
mov r0, #0
mcr p15, 0, r0, c7, c5, 6
#endif
#ifdef RTEMS_SMP
/* Read MPIDR and get current processor index */
mrc p15, 0, r7, c0, c0, 5

View File

@@ -66,7 +66,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
* are required there.
*/
arm_cp15_data_cache_invalidate_all_levels();
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
arm_a9mpcore_start_hook_0();

View File

@@ -72,7 +72,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
* are required there.
*/
arm_cp15_data_cache_invalidate_all_levels();
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
}