bsps: Remove gicvx_interrupt_dispatch()

Avoid one level of indirection.

Update #4202.

bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c

@@ -57,8 +57,3 @@ void arm_interrupt_facility_set_exception_handler(void)
     _AArch64_Exception_interrupt_nest
   );
 }
-
-void bsp_interrupt_dispatch(void)
-{
-  gicvx_interrupt_dispatch();
-}

bsps/arm/shared/irq/irq-arm-gicvx-aarch32.c

@@ -54,8 +54,3 @@ void arm_interrupt_facility_set_exception_handler(void)
     _ARMV4_Exception_interrupt
   );
 }
-
-void bsp_interrupt_dispatch(void)
-{
-  gicvx_interrupt_dispatch();
-}

bsps/include/dev/irq/arm-gic-irq.h

@@ -110,12 +110,6 @@ void arm_interrupt_facility_set_exception_handler(void);
  */
 void arm_interrupt_handler_dispatch(rtems_vector_number vector);
 
-/**
- * This is the GICv1/GICv2/GICv3 interrupt dispatcher that is to be called from the
- * architecture-specific implementation of the IRQ handler.
- */
-void gicvx_interrupt_dispatch(void);
-
 uint32_t arm_gic_irq_processor_count(void);
 
 void arm_gic_irq_initialize_secondary_cpu(void);

bsps/shared/dev/irq/arm-gicv2.c

@@ -49,7 +49,7 @@
 #define CPUIF_ICCICR GIC_CPUIF_ICCICR_ENABLE
 #endif
 
-void gicvx_interrupt_dispatch(void)
+void bsp_interrupt_dispatch(void)
 {
   volatile gic_cpuif *cpuif = GIC_CPUIF;
   uint32_t icciar = cpuif->icciar;

bsps/shared/dev/irq/arm-gicv3.c

@@ -143,7 +143,7 @@ static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
     ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
 }
 
-void gicvx_interrupt_dispatch(void)
+void bsp_interrupt_dispatch(void)
 {
   uint32_t icciar = READ_SR(ICC_IAR1);
   rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar);