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base: RTOS:contrib/bsps/arm/stm32h7/stm32h7xx_hal_driver/1.11.3
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RTOS:main RTOS:6 RTOS:5 RTOS:4.11 RTOS:4.10 RTOS:4.9 RTOS:4.8
RTOS:contrib/cpukit/uuid/1.45.5 RTOS:contrib/cpukit/xz-embedded/2015-11-03-e75f4eb RTOS:contrib/cpukit/zlib/1.3.1 RTOS:contrib/cpukit/utf8proc/1.1.5 RTOS:contrib/cpukit/fastlz/0.1.0 RTOS:contrib/bsps/arm/stm32u5/stm32u5xx-hal-driver/1.5.0 RTOS:contrib/bsps/arm/stm32h7/stm32h7xx_hal_driver/1.11.3 RTOS:contrib/bsps/arm/stm32h7/cmsis-device-h7/1.10.4 RTOS:6.1 RTOS:base/6 RTOS:5.3 RTOS:5.2 RTOS:5.1 RTOS:4.11.3 RTOS:4.11.2 RTOS:4.11.0 RTOS:4.11.1 RTOS:4.10.2 RTOS:4.9.6 RTOS:4.10.1 RTOS:4.10.0 RTOS:4.9.5 RTOS:4.8.2 RTOS:4.9.4 RTOS:4.9.3 RTOS:4.9.2 RTOS:4.9.1 RTOS:4.9.0 RTOS:4.8.1 RTOS:4.8.0 RTOS:4.7.3 RTOS:4.7.2 RTOS:4.7.1 RTOS:4.7.0 RTOS:4.6.6 RTOS:4.6.5 RTOS:4.6.4 RTOS:4.6.3 RTOS:4.6.2 RTOS:4.6.1 RTOS:4.6.0 RTOS:4.5.1-pre3 RTOS:4.5.1-pre2 RTOS:4.5.1-pre1 RTOS:4.5.0 RTOS:4.0.0 RTOS:3.6.0 RTOS:3.5.17 RTOS:3.5.16 RTOS:3.5.15 RTOS:3.5.14 RTOS:3.5.12 RTOS:3.5.1 RTOS:3.5.0-alpha Imagelibrary:base/6 Imagelibrary:4.10.2 Imagelibrary:4.9.6 Imagelibrary:4.10.1 Imagelibrary:4.10.0 Imagelibrary:4.9.5 Imagelibrary:4.8.2 Imagelibrary:4.9.4 Imagelibrary:4.9.3 Imagelibrary:4.9.2 Imagelibrary:4.9.1 Imagelibrary:4.9.0 Imagelibrary:4.8.1 Imagelibrary:4.8.0 Imagelibrary:4.7.3 Imagelibrary:4.7.2 Imagelibrary:4.7.1 Imagelibrary:4.7.0 Imagelibrary:4.6.6 Imagelibrary:4.6.5 Imagelibrary:4.6.4 Imagelibrary:4.6.3 Imagelibrary:4.6.2 Imagelibrary:4.6.1 Imagelibrary:4.6.0 Imagelibrary:4.5.1-pre3 Imagelibrary:4.5.1-pre2 Imagelibrary:4.5.1-pre1 Imagelibrary:4.5.0 Imagelibrary:4.0.0 Imagelibrary:3.6.0 Imagelibrary:3.5.17 Imagelibrary:3.5.16 Imagelibrary:3.5.15 Imagelibrary:3.5.14 Imagelibrary:3.5.12 Imagelibrary:3.5.1 Imagelibrary:3.5.0-alpha Imagelibrary:4.11.0 Imagelibrary:4.11.1 Imagelibrary:4.11.2 Imagelibrary:4.11.3 Imagelibrary:5.1 Imagelibrary:5.2 Imagelibrary:5.3 Imagelibrary:6.1 Imagelibrary:contrib/bsps/arm/stm32h7/cmsis-device-h7/1.10.4 Imagelibrary:contrib/bsps/arm/stm32h7/stm32h7xx_hal_driver/1.11.3 Imagelibrary:contrib/bsps/arm/stm32u5/stm32u5xx-hal-driver/1.5.0 Imagelibrary:contrib/cpukit/fastlz/0.1.0 Imagelibrary:contrib/cpukit/utf8proc/1.1.5 Imagelibrary:contrib/cpukit/uuid/1.45.5 Imagelibrary:contrib/cpukit/xz-embedded/2015-11-03-e75f4eb Imagelibrary:contrib/cpukit/zlib/1.3.1
..
compare: RTOS:6
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RTOS:main RTOS:6 RTOS:5 RTOS:4.11 RTOS:4.10 RTOS:4.9 RTOS:4.8 Imagelibrary:6 Imagelibrary:main Imagelibrary:5 Imagelibrary:4.11 Imagelibrary:4.10 Imagelibrary:4.9 Imagelibrary:4.8
RTOS:contrib/cpukit/uuid/1.45.5 RTOS:contrib/cpukit/xz-embedded/2015-11-03-e75f4eb RTOS:contrib/cpukit/zlib/1.3.1 RTOS:contrib/cpukit/utf8proc/1.1.5 RTOS:contrib/cpukit/fastlz/0.1.0 RTOS:contrib/bsps/arm/stm32u5/stm32u5xx-hal-driver/1.5.0 RTOS:contrib/bsps/arm/stm32h7/stm32h7xx_hal_driver/1.11.3 RTOS:contrib/bsps/arm/stm32h7/cmsis-device-h7/1.10.4 RTOS:6.1 RTOS:base/6 RTOS:5.3 RTOS:5.2 RTOS:5.1 RTOS:4.11.3 RTOS:4.11.2 RTOS:4.11.0 RTOS:4.11.1 RTOS:4.10.2 RTOS:4.9.6 RTOS:4.10.1 RTOS:4.10.0 RTOS:4.9.5 RTOS:4.8.2 RTOS:4.9.4 RTOS:4.9.3 RTOS:4.9.2 RTOS:4.9.1 RTOS:4.9.0 RTOS:4.8.1 RTOS:4.8.0 RTOS:4.7.3 RTOS:4.7.2 RTOS:4.7.1 RTOS:4.7.0 RTOS:4.6.6 RTOS:4.6.5 RTOS:4.6.4 RTOS:4.6.3 RTOS:4.6.2 RTOS:4.6.1 RTOS:4.6.0 RTOS:4.5.1-pre3 RTOS:4.5.1-pre2 RTOS:4.5.1-pre1 RTOS:4.5.0 RTOS:4.0.0 RTOS:3.6.0 RTOS:3.5.17 RTOS:3.5.16 RTOS:3.5.15 RTOS:3.5.14 RTOS:3.5.12 RTOS:3.5.1 RTOS:3.5.0-alpha Imagelibrary:base/6 Imagelibrary:4.10.2 Imagelibrary:4.9.6 Imagelibrary:4.10.1 Imagelibrary:4.10.0 Imagelibrary:4.9.5 Imagelibrary:4.8.2 Imagelibrary:4.9.4 Imagelibrary:4.9.3 Imagelibrary:4.9.2 Imagelibrary:4.9.1 Imagelibrary:4.9.0 Imagelibrary:4.8.1 Imagelibrary:4.8.0 Imagelibrary:4.7.3 Imagelibrary:4.7.2 Imagelibrary:4.7.1 Imagelibrary:4.7.0 Imagelibrary:4.6.6 Imagelibrary:4.6.5 Imagelibrary:4.6.4 Imagelibrary:4.6.3 Imagelibrary:4.6.2 Imagelibrary:4.6.1 Imagelibrary:4.6.0 Imagelibrary:4.5.1-pre3 Imagelibrary:4.5.1-pre2 Imagelibrary:4.5.1-pre1 Imagelibrary:4.5.0 Imagelibrary:4.0.0 Imagelibrary:3.6.0 Imagelibrary:3.5.17 Imagelibrary:3.5.16 Imagelibrary:3.5.15 Imagelibrary:3.5.14 Imagelibrary:3.5.12 Imagelibrary:3.5.1 Imagelibrary:3.5.0-alpha Imagelibrary:4.11.0 Imagelibrary:4.11.1 Imagelibrary:4.11.2 Imagelibrary:4.11.3 Imagelibrary:5.1 Imagelibrary:5.2 Imagelibrary:5.3 Imagelibrary:6.1 Imagelibrary:contrib/bsps/arm/stm32h7/cmsis-device-h7/1.10.4 Imagelibrary:contrib/bsps/arm/stm32h7/stm32h7xx_hal_driver/1.11.3 Imagelibrary:contrib/bsps/arm/stm32u5/stm32u5xx-hal-driver/1.5.0 Imagelibrary:contrib/cpukit/fastlz/0.1.0 Imagelibrary:contrib/cpukit/utf8proc/1.1.5 Imagelibrary:contrib/cpukit/uuid/1.45.5 Imagelibrary:contrib/cpukit/xz-embedded/2015-11-03-e75f4eb Imagelibrary:contrib/cpukit/zlib/1.3.1

36 Commits
contrib/bs ... 6

Author SHA1 Message Date
Kinsey Moore
a79813c96e cpukit/libdebugger/server: Use generic TLS accessor 
This updates the libdebugger server to use a generic TLS area access
mechanism so that it works across all supported architectures.

Closes #5313
 2025-07-31 11:10:56 +10:00
Chris Johns
0cf6de01df cpukit/libio: Support close with IOP references held 
- Provide an option for a file system to support close wtih
  references held. This can happen in more complex file systems
  and file descriptor handling with more complete reference
  handling implementations where an fd can hold other fds and
  close can be call on any fd and succeed.

- Fix open IOP leaks in the error paths.

- Provide better definition of the IOP flags to help clarify
  the code.

Fixes #5201
Closes #5311
 2025-07-26 21:23:36 -05:00
Kinsey Moore
1240e8f81b cpukit/libdebugger: Add support for TLS variables 
This adds support for the "vGetTLSAddr" GDB query which retrieves the
address of a TLS variable by offset from the beginning of the TLS memory
space for the given thread. This offset does not include the size of the
thread control block which is at the beginning of every TLS area as used
by RTEMS. Notably, the returned address is big-endian rather than the
little-endian typical with other responses.

This functionality does not include retrieval of addresses for TLS
variables hosted in loadable modules, only TLS variables in the host
binary.

Closes #5271
 2025-07-24 20:31:40 -05:00
Kinsey Moore
b1dbd9eeae bsps/dev/spi/xqspipsu-flash-helper: Explain source 
This adds a missing header block and better explains the provenance of
the xqspipsu-flash-helper files and their copyright status.

Closes #5309
 2025-07-23 15:18:13 -05:00
Kinsey Moore
84d4c11c30 bsps/include/dev/spi: Add missing extern and guard 
This adds missing extern "C" declarations and a missing header guard.

Updates #5309
 2025-07-23 15:17:59 -05:00
Matteo Concas
e7fa90ab0c cpu/riscv: Add Smdbltrp extension compatibility 
If the Double Trap Extension is implemented, the
MDT bit of the mstatus (or mstatush in RV32)
register will be set when a trap is to be taken.

The MIE (Machine Interrupt Enable) bit can only
be set to 1 if the MDT bit is zero.

Thus, we need to clear MDT first if we want to
enable interrupts when dispatching a thread.

MDT is also cleared in register a1 before
restoring the interrupt frame as writing 1 to MDT
will cause MIE to be set to 0. In RV64 this
happens regardless of the value written to MIE in
the same write.

In RV32, MDT is in the mstatush so we do not need
to clear during restore as this register is not
restored.

With this change all 60 SMP tests pass (compared
to 20/60 before the fix). The tests have been run
on hardware using two RV64 CPUs that implement
the double trap extension.

Close #5288

(cherry picked from commit 19f12d2dca)
 2025-07-03 10:07:39 +02:00
Matteo Concas
dd490c5c2d bsps/noelv: Fix using console in polled mode 
Before, the console driver needed
`BSP_CONSOLE_USE_INTERRUPTS` to be defined or it
would not build. The intent was to use polled
mode if the macro was equal to zero.

This change makes it so interrupt mode is used if
the macro is defined and polled mode is used if
the macro is not defined.

(cherry picked from commit 5e0a68d3ab)

Close #5283
 2025-06-27 09:41:33 +02:00
Matteo Concas
d010f6ae8b bsps/sparc/leon3: Fix GPTIMER timer index logic 
The old logic would lead to an error when
multiprocessing was enabled and
`LEON3_GPTIMER_BASE` was defined due to
`leon3_timer_core_index` being undefined.

The new logic fixes this and keeps the same
intent:
 - If multiprocessing is not enabled, the timer
   index is 0
 - If multiprocessing is enabled and
   `LEON3_GPTIMER_BASE` is defined, the timer
   index is twice the CPU boot index
 - If multiprocessing is enabled and
   `LEON3_GPTIMER_BASE` is not defined, we
   fallback to the old logic using the GPTIMER
   core index.

Close #5281
 2025-06-25 08:22:13 +02:00
Kinsey Moore
3d8b56f10c cpukit/libdebugger: Prevent hang on memory access 
When memory is accessed by the remote debugging client, the access is
sandboxed with setjmp/longjmp and appropriate exception handlers to
prevent the attempted access from causing a failure of the debugger or
otherwise altering execution. The existing implementation works as
expected when the context executing the memory access and the exception
context resulting from a failed access do not share a stack.

In the case of AArch64, a failed access when the debugger is already in
exception context causes a re-entry into exception context where the
machine state is pushed onto the same stack that was in use where the
exception occurred. When setjmp is called inside a stack frame and the
exception occurs outside that stack frame, the stack frame is unwound
before the exception occurs and the exception entry overwrites the area
previously occupied by the stack frame housing the setjmp and corrupting
the link register that is stored there. After restoration of state using
longjmp(), this corrupted link register information is loaded from the
stack frame and undesired behavior occurs.

In the instance of this bug that was encountered, the corrupted link
register contained an unaligned pointer which caused an unending cascade
of prefetch abort exceptions presenting as a hard hang.

Closes #5273
 2025-06-18 13:53:35 -05:00
Chris Johns
cb3fba0447 bsps/shared/dev/ide: Initalise ATA request links as off chain 
- Fixes the asserts when building with RTEMS_DEBUG

Closes #5254
 2025-05-28 13:01:00 +10:00
Chris Johns
6335d7e48a machine/timecounters: Add missing _Timecounter_ decls 
Add:

 - _Timecounter_Getboottime
 - _Timecounter_Getboottimebin

Closes #5212
 2025-05-09 08:37:01 +10:00
Chris Johns
f769b20c98 cpukit/libdl: Fix loading symbols from an object file at runtime 
- Assume a relocation record with a symbol name with a length of
  0 is resolved. ARM seems to create a symbol with no name for
  R_ARM_V4BX relocation records.

- Move the addition of the rtems_rtl_base_sym_global_add symbol
  to the global symbol table to the weak
  rtems_rtl_base_global_syms_init call. If symbols are
  embedded the support for runtime loading symbols is over
  loaded. This change is required so the base object has a
  valid global symbol table attached to track dependencies.

Fixes #5234
 2025-04-01 12:31:32 +11:00
Matteo Concas
9dae9f5fe8 spec: Install missing header files for GRLIB and SPARC 
The following files will be installed during SPARC/GRLIB builds:
- bsps/include/grlib/apbuart-regs.h
- bsps/include/grlib/gptimer-regs.h
- bsps/include/grlib/irqamp-regs.h
- bsps/sparc/include/grlib/io.h

Closes issue #5232
 2025-03-26 17:43:13 +01:00
Amar Takhar
b4149b2282 gitlab: Add link to CI 
This runs only the commit message and merge request checker.

Required so we can have 'all pipelines must pass' enabled due to a bug in
Gitlab
 2025-02-12 22:22:24 -05:00
Chris Johns
87bf49b715 Revert "build: Provide LDFLAGS for pkg-config" 
This reverts commit e36ba91110
 2025-02-11 05:38:19 +00:00
Sebastian Huber
e421c922a8 bsp/qoriq: Ignore spurious interrupts 
For example, with edge triggered external interrupts we may see spurious
interrupts.   Ignore them instead of issuing a fatal error.

Use eieio to synchronize access to the IACK and EOI registers.

Use a loop to immediately services the next pending interrupt without
having to go through the exception epiloge and prologue.

Close #5173.
 2025-02-07 16:18:23 -07:00
Sebastian Huber
e36ba91110 build: Provide LDFLAGS for pkg-config 
Some pkg-config variants perform transformations on the --libs options.
This may lead to completely broken linker options.  Provide the LDFLAGS
as a variable.  Remove "Ldflags:" since this is an unsupported field.

Update #5165.
 2025-02-07 18:28:01 +00:00
Jan Sommer
a0e4be53f4 grlib/occan: Fix baud rate calculation 
Fixes #5205
 2025-02-07 08:50:42 -07:00
Jan Sommer
9641e1e97d cpukit/termios: Fix ordering of baud rate table 
rtems_termios_set_best_baud expects a sorted baud rate table.

Fixes #5202
 2025-02-03 12:04:33 -07:00
Reinking, Janosch
f1c201c508 bsps/shared: NS16550 driver updates the line control register during operation 
Fixes: #5179
 2025-01-24 00:08:29 +00:00
Zhaoyue Wang
603c168a0b cpukit/libmisc: fix flag in capture.c 
The RTEMS_CAPTURE_OVERFLOW is an overflow flag for each CPU, and its
value is the same as RTEMS_CAPTURE_INIT. Executing rtems_capture_flush
will set the RTEMS_CAPTURE_INIT flag to 0 in the global flags.

Fixes #5184.
 2025-01-23 23:45:01 +00:00
Ranulfo Raphael
84c2cf3da9 cpukit/libdl/arm: Fix trampoline alignment 
This commit aligns trampolines for THUMB and ARM instructions
(CALL/JUMP24 and THM_JUMP24/THM_PC22).

According to the ARM technical reference in section "Register-relative
and PC-relative expressions":
    In Thumb code:
    - For B, BL, CBNZ, and CBZ instructions, the value of the PC is the
      address of the current instruction plus 4 bytes.
    - For all other instructions that use labels, the value of the PC is
      the address of the current instruction plus 4 bytes, with bit[1]
      of the result cleared to 0 to make it word-aligned.

Closes #5189
 2025-01-23 19:38:05 -03:00
Chris Johns
0a46769ba4 waf: Handle no version label in VERSION when a release 
Closes #5185
 2025-01-22 13:55:03 +11:00
Kinsey Moore
f7de6d5425 spec/pkgconfig: Account for separate compilation and linking 
When compilation and linking are performed separately, some platforms
(i.e. RISC-V) may require that ABI flags are provided during the linking
step as well as the compilation step.

Closes #5183
 2025-01-16 19:02:56 -06:00
Sebastian Huber
34ba74f4f4 score: Fix RTEMS_DEBUG build 
Close #5159.
 2025-01-08 06:41:12 +01:00
Chris Johns
d61a739e41 waf: Update to waf-2.1.4 
Closes #5167
 2024-12-22 10:42:40 +11:00
Sebastian Huber
a357119bd6 build: Improve Makefile.inc 
Support relocated BSP installations by letting the user provide
RTEMS_ROOT.

Close #5171.
 2024-12-05 04:11:45 +01:00
Sebastian Huber
e79dc64c8e rtems: Remove pre-qualified constraints 
The pre-qualified constraints are not applicable to mainline RTEMS.
 2024-11-27 04:47:26 +01:00
Sebastian Huber
7f00921b07 score: Support scheduler change inhibitors 
For example, the POSIX sporadic server adds a second priority to a
thread.  We cannot account for this priority in a scheduler change.

Update #5164.
 2024-11-27 02:17:14 +00:00
Sebastian Huber
63c5d062c3 score: Fix _Thread_Priority_change() 
The POSIX sporadic server may temporarily remove the real priority of a
thread.  Check that the priority node is active before the change is
propagated.

Update #5164.
 2024-11-27 02:17:14 +00:00
Sebastian Huber
65e480312c posix: Use real priority for sporadic server state 
This allows to other areas to use the real priority node state.

Update #5164.
 2024-11-27 02:17:14 +00:00
Sebastian Huber
78e5e76572 psxtests/psx09: Change prio while at low prio 
Update #5164.
 2024-11-27 02:17:14 +00:00
Sebastian Huber
5eb938283d psxtests/psx09: Improve sporadic server tests 
Drop thread parameter from get_current_prio().

Lock/unlock ceiling mutex while executing at low and high priority.

Update #5164.
 2024-11-27 02:17:14 +00:00
Sebastian Huber
e565dbba65 psxtests/psx09: Use local variables 
Update #5164.
 2024-11-27 02:17:14 +00:00
Kinsey Moore
106d00537e posix/lio_listio: corrected addition of system event 
Previously the system event used by lio_listio was manually added to
event.h and not using rtems-central. This patch corrects that and renames
the event to make it clearer.

Some related dead code has also been removed.


(cherry picked from commit cabc8c3a78)

Co-authored-by: alessandronardin <ale.daluch@gmail.com>
 2024-11-26 19:42:12 +00:00
Chris Johns
c529694656 cpukit/jffs2/rtime: Fix off-by-one error in decompression check 
Closes #5072


(cherry picked from commit abaea2b798)

Co-authored-by: Kinsey Moore <kinsey.moore@oarcorp.com>
 2024-11-22 02:22:32 +00:00
2292 changed files with 112526 additions and 821489 deletions
Expand all files Collapse all files

6
.gitlab/gitlab-ci.yml
View File

@@ -1,4 +1,4 @@
include:
- project: 'administration/integration'
file:
- 'ci/config/rtems.yml'
- project: 'administration/integration'
file:
- 'ci/config/rtems.yml'

294
.gitlab/ignore.toml
View File

@@ -1,294 +0,0 @@
["defaults"]
exclude = ["format", "spell"]
[[ignore."cpukit/dev"]]
files = ["cpukit/dev/iovprintf.c"]
[[ignore."cpukit/include"]]
files = [
"cpukit/include/arpa/ftp.h",
"cpukit/include/crypt.h",
"cpukit/include/dlfcn.h",
"cpukit/include/fdt.h",
"cpukit/include/libfdt_env.h",
"cpukit/include/libfdt.h",
"cpukit/include/link_elf.h",
"cpukit/include/link.h",
"cpukit/include/md4.h",
"cpukit/include/md5.h",
"cpukit/include/mghttpd/mongoose.h",
"cpukit/include/rtems/jffs2.h",
"cpukit/include/rtems/mouse_parser.h",
"cpukit/include/sha224.h",
"cpukit/include/sha256.h",
"cpukit/include/sha384.h",
"cpukit/include/sha512.h",
"cpukit/include/sha512t.h",
"cpukit/include/sys/_ffcounter.h",
"cpukit/include/sys/cdefs_elf.h",
"cpukit/include/sys/endian.h",
"cpukit/include/sys/event.h",
"cpukit/include/sys/exec_elf.h",
"cpukit/include/sys/priority.h",
"cpukit/include/sys/statvfs.h",
"cpukit/include/sys/timeffc.h",
"cpukit/include/sys/timepps.h",
"cpukit/include/sys/timetc.h",
"cpukit/include/sys/timex.h",
"cpukit/include/sys/utsname.h",
"cpukit/include/uuid/uuid.h",
"cpukit/include/xz.h",
"cpukit/include/zconf.h",
"cpukit/include/zlib.h"
]
[[ignore."cpukit/include/machine"]]
files = ["cpukit/include/machine/*.h"]
[[ignore."cpukit/jffs2"]]
files = [
"cpukit/libfs/src/jffs2/include/linux/jffs2.h",
"cpukit/libfs/src/jffs2/src/acl.h",
"cpukit/libfs/src/jffs2/src/build.c",
"cpukit/libfs/src/jffs2/src/compat-crc32.c",
"cpukit/libfs/src/jffs2/src/compr_rtime.c",
"cpukit/libfs/src/jffs2/src/compr_zlib.c",
"cpukit/libfs/src/jffs2/src/compr_rubin.c",
"cpukit/libfs/src/jffs2/src/compr.c",
"cpukit/libfs/src/jffs2/src/compr.h",
"cpukit/libfs/src/jffs2/src/debug.c",
"cpukit/libfs/src/jffs2/src/debug.h",
"cpukit/libfs/src/jffs2/src/dir-rtems.c",
"cpukit/libfs/src/jffs2/src/erase.c",
"cpukit/libfs/src/jffs2/src/flashio.c",
"cpukit/libfs/src/jffs2/src/fs-rtems.c",
"cpukit/libfs/src/jffs2/src/gc.c",
"cpukit/libfs/src/jffs2/src/jffs2_fs_i.h",
"cpukit/libfs/src/jffs2/src/jffs2_fs_sb.h",
"cpukit/libfs/src/jffs2/src/malloc-rtems.c",
"cpukit/libfs/src/jffs2/src/nodelist.c",
"cpukit/libfs/src/jffs2/src/nodelist.h",
"cpukit/libfs/src/jffs2/src/nodemgmt.c",
"cpukit/libfs/src/jffs2/src/read.c",
"cpukit/libfs/src/jffs2/src/readinode.c",
"cpukit/libfs/src/jffs2/src/scan.c",
"cpukit/libfs/src/jffs2/src/summary.h",
"cpukit/libfs/src/jffs2/src/wbuf.c",
"cpukit/libfs/src/jffs2/src/write.c",
"cpukit/libfs/src/jffs2/src/xattr.h"
]
[[ignore."cpukit/libcrypt"]]
files = ["cpukit/libcrypt/*.c"]
[[ignore."cpukit/libcsupport"]]
files = [
"cpukit/libcsupport/src/cfmakeraw.c",
"cpukit/libcsupport/src/cfmakesane.c",
"cpukit/libcsupport/src/realpath.c"
]
[[ignore."cpukit/libmd"]]
files = ["cpukit/libmd/*.c"]
[[ignore."cpukit/libdl"]]
files = [
"cpukit/libdl/fastlz.c",
"cpukit/libdl/fastlz.h"
]
[[ignore."cpukit/dtc"]]
files = [
"cpukit/dtc/libfdt/*.c",
"cpukit/dtc/libfdt/*.h",
"cpukit/dtc/README.license",
"cpukit/dtc/VERSION"
]
[[ignore."cpukit/mghttpd"]]
files = [
"cpukit/mghttpd/mongoose.c",
]
[[ignore."cpukit/mouse"]]
files = ["cpukit/libmisc/mouse/mouse_parser.c"]
[[ignore."cpukit/score/cpu"]]
files = [
"cpukit/score/cpu/i386/include/machine/elf_machdep.h",
"cpukit/score/cpu/m68k/include/machine/elf_machdep.h",
"cpukit/score/cpu/mips/include/machine/elf_machdep.h",
"cpukit/score/cpu/nios2/include/machine/elf_machdep.h",
"cpukit/score/cpu/sparc/include/machine/elf_machdep.h",
"cpukit/score/cpu/x86_64/include/machine/elf_machdep.h"
]
[[ignore."cpukit/score/kern"]]
files = [
"cpukit/score/src/kern_ntptime.c",
"cpukit/score/src/kern_tc.c"
]
[[ignore."cpukit/shell"]]
files = [
"cpukit/libmisc/shell/cat_file.c",
"cpukit/libmisc/shell/cmds.c",
"cpukit/libmisc/shell/cmp-ls.c",
"cpukit/libmisc/shell/dd-args.c",
"cpukit/libmisc/shell/dd-conv_tab.c",
"cpukit/libmisc/shell/dd-conv.c",
"cpukit/libmisc/shell/dd-misc.c",
"cpukit/libmisc/shell/dd-position.c",
"cpukit/libmisc/shell/dd.h",
"cpukit/libmisc/shell/err.c",
"cpukit/libmisc/shell/err.h",
"cpukit/libmisc/shell/errx.c",
"cpukit/libmisc/shell/extern-cp.h",
"cpukit/libmisc/shell/extern-dd.h",
"cpukit/libmisc/shell/extern-ls.h",
"cpukit/libmisc/shell/fdisk.c",
"cpukit/libmisc/shell/filemode.c",
"cpukit/libmisc/shell/fts.c",
"cpukit/libmisc/shell/fts.h",
"cpukit/libmisc/shell/hexdump-conv.c",
"cpukit/libmisc/shell/hexdump-display.c",
"cpukit/libmisc/shell/hexdump-odsyntax.c",
"cpukit/libmisc/shell/hexdump-parse.c",
"cpukit/libmisc/shell/hexdump.h",
"cpukit/libmisc/shell/hexsyntax.c",
"cpukit/libmisc/shell/login_check.c",
"cpukit/libmisc/shell/login_prompt.c",
"cpukit/libmisc/shell/main_alias.c",
"cpukit/libmisc/shell/main_blkstats.c",
"cpukit/libmisc/shell/main_blksync.c",
"cpukit/libmisc/shell/main_cat.c",
"cpukit/libmisc/shell/main_cd.c",
"cpukit/libmisc/shell/main_chdir.c",
"cpukit/libmisc/shell/main_chmod.c",
"cpukit/libmisc/shell/main_chroot.c",
"cpukit/libmisc/shell/main_cmdchmod.c",
"cpukit/libmisc/shell/main_cmdchown.c",
"cpukit/libmisc/shell/main_cmdls.c",
"cpukit/libmisc/shell/main_cp.c",
"cpukit/libmisc/shell/main_cpuinfo.c",
"cpukit/libmisc/shell/main_cpuuse.c",
"cpukit/libmisc/shell/main_date.c",
"cpukit/libmisc/shell/main_dd.c",
"cpukit/libmisc/shell/main_debugrfs.c",
"cpukit/libmisc/shell/main_df.c",
"cpukit/libmisc/shell/main_dir.c",
"cpukit/libmisc/shell/main_echo.c",
"cpukit/libmisc/shell/main_edit.c",
"cpukit/libmisc/shell/main_exit.c",
"cpukit/libmisc/shell/main_flashdev.c",
"cpukit/libmisc/shell/main_getenv.c",
"cpukit/libmisc/shell/main_halt.c",
"cpukit/libmisc/shell/main_help.c",
"cpukit/libmisc/shell/main_hexdump.c",
"cpukit/libmisc/shell/main_i2cdetect.c",
"cpukit/libmisc/shell/main_i2cget.c",
"cpukit/libmisc/shell/main_i2cset.c",
"cpukit/libmisc/shell/main_id.c",
"cpukit/libmisc/shell/main_ln.c",
"cpukit/libmisc/shell/main_logoff.c",
"cpukit/libmisc/shell/main_ls.c",
"cpukit/libmisc/shell/main_lsof.c",
"cpukit/libmisc/shell/main_mallocinfo.c",
"cpukit/libmisc/shell/main_md5.c",
"cpukit/libmisc/shell/main_mdump.c",
"cpukit/libmisc/shell/main_medit.c",
"cpukit/libmisc/shell/main_mfill.c",
"cpukit/libmisc/shell/main_mkdir.c",
"cpukit/libmisc/shell/main_mknod.c",
"cpukit/libmisc/shell/main_mkrfs.c",
"cpukit/libmisc/shell/main_mmove.c",
"cpukit/libmisc/shell/main_mount.c",
"cpukit/libmisc/shell/main_msdosfmt.c",
"cpukit/libmisc/shell/main_mv.c",
"cpukit/libmisc/shell/main_perioduse.c",
"cpukit/libmisc/shell/main_profreport.c",
"cpukit/libmisc/shell/main_pwd.c",
"cpukit/libmisc/shell/main_rm.c",
"cpukit/libmisc/shell/main_rmdir.c",
"cpukit/libmisc/shell/main_rtc.c",
"cpukit/libmisc/shell/main_rtems.c",
"cpukit/libmisc/shell/main_rtrace.c",
"cpukit/libmisc/shell/main_setenv.c",
"cpukit/libmisc/shell/main_sleep.c",
"cpukit/libmisc/shell/main_spi.c",
"cpukit/libmisc/shell/main_stackuse.c",
"cpukit/libmisc/shell/main_time.c",
"cpukit/libmisc/shell/main_top.c",
"cpukit/libmisc/shell/main_tty.c",
"cpukit/libmisc/shell/main_umask.c",
"cpukit/libmisc/shell/main_unmount.c",
"cpukit/libmisc/shell/main_unsetenv.c",
"cpukit/libmisc/shell/main_whoami.c",
"cpukit/libmisc/shell/main_wkspaceinfo.c",
"cpukit/libmisc/shell/mknod-pack_dev.h",
"cpukit/libmisc/shell/pathnames-mv.h",
"cpukit/libmisc/shell/print_heapinfo.c",
"cpukit/libmisc/shell/print-ls.c",
"cpukit/libmisc/shell/pwcache.c",
"cpukit/libmisc/shell/shell_cmdset.c",
"cpukit/libmisc/shell/shell_getchar.c",
"cpukit/libmisc/shell/shell_getprompt.c",
"cpukit/libmisc/shell/shell_makeargs.c",
"cpukit/libmisc/shell/shell_script.c",
"cpukit/libmisc/shell/shell-wait-for-input.c",
"cpukit/libmisc/shell/shell.c",
"cpukit/libmisc/shell/shellconfig.c",
"cpukit/libmisc/shell/sysexits.h",
"cpukit/libmisc/shell/utils-cp.c",
"cpukit/libmisc/shell/utils-ls.c",
"cpukit/libmisc/shell/verr.c",
"cpukit/libmisc/shell/verrx.c",
"cpukit/libmisc/shell/vis.c",
"cpukit/libmisc/shell/vis.h",
"cpukit/libmisc/shell/vwarn.c",
"cpukit/libmisc/shell/vwarnx.c",
"cpukit/libmisc/shell/warn.c",
"cpukit/libmisc/shell/warnx.c",
"cpukit/libmisc/shell/write_file.c",
"cpukit/libmisc/uuid/clear.c",
"cpukit/libmisc/uuid/compare.c",
"cpukit/libmisc/uuid/copy.c",
"cpukit/libmisc/uuid/gen_uuid.c",
"cpukit/libmisc/uuid/isnull.c",
"cpukit/libmisc/uuid/pack.c",
"cpukit/libmisc/uuid/parse.c",
"cpukit/libmisc/uuid/unpack.c",
"cpukit/libmisc/uuid/unparse.c",
"cpukit/libmisc/uuid/uuid_time.c",
"cpukit/libmisc/uuid/uuidd.h",
"cpukit/libmisc/uuid/uuidP.h"
]
[[ignore."cpukit/xz"]]
files = [
"cpukit/compression/xz/*.h",
"cpukit/compression/xz/*.c"
]
[[ignore."cpukit/zlib"]]
files = [
"cpukit/compression/zlib/*.c",
"cpukit/compression/zlib/*.h",
"cpukit/compression/zlib/doc/*",
"cpukit/compression/zlib/ChangeLog.zlib",
"cpukit/compression/zlib/FAQ"
]
# These files have test characters that fail the char test
[[ignore."testsuites/fstests/fsdosfsname01"]]
exclude = ["char"]
files = [
"testsuites/fstests/fsdosfsname01/init.c",
"testsuites/fstests/fsdosfsname01/create_files.cs",
"testsuites/fstests/fsdosfsname01/files.h"
]
[[ignore."yaml"]]
files = [
"yaml/*"
]

1286
LICENSE.md
View File

File diff suppressed because it is too large Load Diff

2
README.md
View File

@@ -40,7 +40,7 @@ RTEMS POSIX 1003.1 Compliance Guide:
RTEMS Mailing Lists for general purpose use the users list and for developers
use the devel list.
* https://lists.rtems.org/mailman/listinfo
* https://lists.rtems.org/mailman/listinfo
The version number for this software is indicated in the VERSION file.

6
bsps/aarch64/include/bsp/aarch64-mmu.h
View File

@@ -117,9 +117,13 @@ typedef struct {
.end = (uintptr_t) bsp_translation_table_end, \
.flags = AARCH64_MMU_DATA_RW_CACHED \
}, { \
/*
* The vector table must be in writable and executable memory as it stores both
* exception code and the mutable pointer to which it jumps
*/ \
.begin = (uintptr_t) bsp_start_vector_table_begin, \
.end = (uintptr_t) bsp_start_vector_table_end, \
.flags = AARCH64_MMU_CODE_CACHED \
.flags = AARCH64_MMU_CODE_RW_CACHED \
}
/**

79
bsps/aarch64/raspberrypi/fdt/bcm2711-rpi-4-b.dts
View File

@@ -1,79 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsAArch64Raspberrypi4
*
* @brief This file provides the base Raspberrypi4 device tree
*/
/*
* Copyright (C) 2024 Ning Yang
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <1>;
amba@7c000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x7c000000 0x00 0xfc000000 0x3800000>, <0x40000000 0x00 0xff800000 0x800000>;
interrupt-controller@40041000 {
compatible = "arm,gic-400";
#address-cells = <2>;
#interrupt-cells = <3>;
reg = <0x40041000 0x1000>, <0x40042000 0x2000>, <0x40044000 0x2000>, <0x40046000 0x2000>;
interrupt-controller;
phandle = <1>;
};
ethernet@7d580000 {
phy-mode = "rgmii-rxid";
phy-handle = <&phy0>;
compatible = "brcm,bcm2711-genet-v5";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x7d580000 0x10000>;
interrupt-parent = <1>;
interrupts = <0x0 0x9d 0x4> , <0x0 0x9e 0x4>;
mdio@e14 {
compatible = "brcm,genet-mdio-v5";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe14 0x8>;
phy0: ethernet-phy@1 {
reg = <0x1>;
};
};
};
};
};

88
bsps/aarch64/raspberrypi/fdt/rpi4b_dtb.c
View File

@@ -1,88 +0,0 @@
/*
* Declarations for C structure representing binary file bcm2711-rpi-4-b.dtb
*
* WARNING: Automatically generated -- do not edit!
*/
#include <sys/types.h>
const unsigned char bcm2711_rpi_4_b_dtb[] = {
0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x03, 0x8b, 0x00, 0x00, 0x00, 0x38,
0x00, 0x00, 0x02, 0xfc, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f,
0x00, 0x00, 0x02, 0xc4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
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0xfc, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x3e, 0x40, 0x04, 0x10, 0x00,
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0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
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0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9d, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x01, 0x6d, 0x64, 0x69, 0x6f, 0x40, 0x65, 0x31, 0x34,
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0x65, 0x74, 0x2d, 0x6d, 0x64, 0x69, 0x6f, 0x2d, 0x76, 0x35, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x0e, 0x14,
0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
0x72, 0x6e, 0x65, 0x74, 0x2d, 0x70, 0x68, 0x79, 0x40, 0x31, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64,
0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23,
0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63,
0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x72, 0x61,
0x6e, 0x67, 0x65, 0x73, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,
0x67, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70,
0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x6d,
0x6f, 0x64, 0x65, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x68, 0x61, 0x6e, 0x64,
0x6c, 0x65, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74,
0x2d, 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x69, 0x6e, 0x74, 0x65,
0x72, 0x72, 0x75, 0x70, 0x74, 0x73, 0x00,
};
const size_t bcm2711_rpi_4_b_dtb_size = sizeof(bcm2711_rpi_4_b_dtb);

361
bsps/aarch64/raspberrypi/i2c/raspberrypi-i2c.c
View File

@@ -1,361 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup raspberrypi_4_i2c
*
* @brief I2C Driver
*/
/*
* Copyright (C) 2025 Shaunak Datar
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp/irq.h>
#include <bsp/raspberrypi-i2c.h>
#include <bsp/raspberrypi.h>
#include <bsp/rpi-gpio.h>
#include <dev/i2c/i2c.h>
#define C_REG( bus ) BCM2835_REG( ( bus )->base_address + BCM2711_I2C_CONTROL )
#define C_I2CEN ( 1 << 15 )
#define C_INTR ( 1 << 10 )
#define C_INTT ( 1 << 9 )
#define C_INTD ( 1 << 8 )
#define C_ST ( 1 << 7 )
#define C_CLEAR ( 1 << 5 )
#define C_READ ( 1 << 0 )
#define BSC_CORE_CLK_HZ 150000000
#define S_REG( bus ) BCM2835_REG( ( bus )->base_address + BCM2711_I2C_STATUS )
#define S_CLKT ( 1 << 9 )
#define S_ERR ( 1 << 8 )
#define S_RXF ( 1 << 7 )
#define S_TXE ( 1 << 6 )
#define S_RXD ( 1 << 5 )
#define S_TXD ( 1 << 4 )
#define S_RXR ( 1 << 3 )
#define S_TXW ( 1 << 2 )
#define S_DONE ( 1 << 1 )
#define S_TA ( 1 << 0 )
#define S_ERROR ( S_CLKT | S_ERR | S_DONE )
typedef struct {
i2c_bus base;
uint32_t input_clock;
uintptr_t base_address;
raspberrypi_bsc_masters device;
uint32_t remaining_bytes;
uint32_t remaining_transfers;
uint8_t *current_buffer;
uint32_t current_buffer_size;
bool read_transfer;
} raspberrypi_i2c_bus;
static int i2c_polling_read( raspberrypi_i2c_bus *bus )
{
while ( !( S_REG( bus ) & S_DONE ) && ( bus->remaining_bytes > 0 ) ) {
while ( ( S_REG( bus ) & S_RXD ) && ( bus->remaining_bytes > 0 ) ) {
*bus->current_buffer = BCM2835_REG(
bus->base_address + BCM2711_I2C_FIFO
) &
BCM2711_I2C_FIFO_MASK;
bus->current_buffer++;
bus->remaining_bytes--;
/* Check for errors */
if ( S_REG( bus ) & ( S_CLKT | S_ERR ) ) {
return -EIO;
}
}
}
return 0;
}
static int i2c_polling_write( raspberrypi_i2c_bus *bus )
{
while ( !( S_REG( bus ) & S_DONE ) && ( bus->remaining_bytes > 0 ) ) {
while ( bus->remaining_bytes > 0 && ( S_REG( bus ) & S_TXD ) ) {
BCM2835_REG( bus->base_address + BCM2711_I2C_FIFO ) = *(
bus->current_buffer
);
bus->current_buffer++;
bus->remaining_bytes--;
/* Check for errors */
if ( S_REG( bus ) & ( S_CLKT | S_ERR ) ) {
return -EIO;
}
}
}
return 0;
}
static int rpi_i2c_bus_transfer( raspberrypi_i2c_bus *bus )
{
int rv;
if ( bus->read_transfer ) {
rv = i2c_polling_read( bus );
if ( rv < 0 ) {
return rv;
}
} else {
rv = i2c_polling_write( bus );
if ( rv < 0 ) {
return rv;
}
}
if ( ( S_REG( bus ) & S_ERR ) || ( S_REG( bus ) & S_CLKT ) ||
( bus->remaining_bytes != 0 ) ) {
return -EIO;
}
S_REG( bus ) = S_DONE;
return 0;
}
static void rpi_i2c_destroy( i2c_bus *base )
{
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
i2c_bus_destroy_and_free( &bus->base );
}
static int rpi_i2c_set_clock( i2c_bus *base, unsigned long clock )
{
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
uint32_t clock_rate;
uint16_t divider;
divider = BSC_CORE_CLK_HZ / clock;
clock_rate = BSC_CORE_CLK_HZ / divider;
while ( clock_rate > clock ) {
++divider;
clock_rate = BSC_CORE_CLK_HZ / divider;
}
BCM2835_REG( bus->base_address + BCM2711_I2C_DIV ) = divider;
return 0;
}
static int rpi_i2c_setup_and_transfer( raspberrypi_i2c_bus *bus )
{
int rv;
while ( bus->remaining_transfers > 0 ) {
bus->remaining_bytes = bus->remaining_transfers > 1 ?
BCM2711_I2C_DLEN_MASK :
( bus->current_buffer_size & BCM2711_I2C_DLEN_MASK
);
BCM2835_REG( bus->base_address + BCM2711_I2C_DLEN ) = bus->remaining_bytes;
/* Clear the error bits before starting new transfer */
S_REG( bus ) = S_ERROR;
rv = rpi_i2c_bus_transfer( bus );
if ( rv < 0 ) {
return rv;
}
--bus->remaining_transfers;
}
return 0;
}
static int rpi_i2c_transfer( i2c_bus *base, i2c_msg *msgs, uint32_t msg_count )
{
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
int rv = 0;
uint32_t i;
uint8_t msbs;
int supported_flags = I2C_M_TEN | I2C_M_RD;
for ( i = 0; i < msg_count; i++ ) {
if ( msgs[ i ].len == 0 || msgs[ i ].buf == NULL ) {
return -EINVAL;
}
if ( ( msgs[ i ].flags & ~supported_flags ) != 0 ) {
return -EINVAL;
}
}
for ( i = 0; i < msg_count; i++ ) {
bus->current_buffer = msgs[ i ].buf;
bus->current_buffer_size = msgs[ i ].len;
bus->remaining_transfers = ( bus->current_buffer_size +
( BCM2711_I2C_DLEN_MASK - 1 ) ) /
BCM2711_I2C_DLEN_MASK;
/* 10-bit slave address */
if ( msgs[ i ].flags & I2C_M_TEN ) {
/* Add the 8 lsbs of the 10-bit slave address to the fifo register */
BCM2835_REG(
bus->base_address + BCM2711_I2C_FIFO
) = msgs[ i ].addr & BCM2711_I2C_FIFO_MASK;
msbs = msgs[ i ].addr >> 8;
BCM2835_REG(
bus->base_address + BCM2711_I2C_SLAVE_ADDRESS
) = BCM2711_10_BIT_ADDR_MASK | msbs;
} else {
BCM2835_REG(
bus->base_address + BCM2711_I2C_SLAVE_ADDRESS
) = msgs[ i ].addr;
}
if ( msgs[ i ].flags & I2C_M_RD ) {
C_REG( bus ) |= C_CLEAR | C_READ | C_ST; // Read packet transfer
bus->read_transfer = true;
} else {
C_REG( bus ) |= C_CLEAR | C_ST; // Write packet transfer
bus->read_transfer = false;
}
/* Disable clock stretch timeout */
BCM2835_REG( bus->base_address + BCM2711_I2C_CLKT ) = 0;
rv = rpi_i2c_setup_and_transfer( bus );
if ( rv < 0 ) {
return rv;
}
}
return rv;
}
static rtems_status_code rpi_i2c_gpio_init(
raspberrypi_bsc_masters device,
raspberrypi_i2c_bus *bus
)
{
switch ( device ) {
case raspberrypi_bscm0:
raspberrypi_gpio_set_function( 0, GPIO_AF0 );
raspberrypi_gpio_set_function( 1, GPIO_AF0 );
bus->base_address = BCM2711_I2C0_BASE;
break;
case raspberrypi_bscm1:
raspberrypi_gpio_set_function( 2, GPIO_AF0 );
raspberrypi_gpio_set_function( 3, GPIO_AF0 );
bus->base_address = BCM2711_I2C1_BASE;
break;
case raspberrypi_bscm3:
raspberrypi_gpio_set_function( 4, GPIO_AF5 );
raspberrypi_gpio_set_function( 5, GPIO_AF5 );
bus->base_address = BCM2711_I2C3_BASE;
break;
case raspberrypi_bscm4:
raspberrypi_gpio_set_function( 6, GPIO_AF5 );
raspberrypi_gpio_set_function( 7, GPIO_AF5 );
bus->base_address = BCM2711_I2C4_BASE;
break;
case raspberrypi_bscm5:
raspberrypi_gpio_set_function( 10, GPIO_AF5 );
raspberrypi_gpio_set_function( 11, GPIO_AF5 );
bus->base_address = BCM2711_I2C5_BASE;
break;
case raspberrypi_bscm6:
raspberrypi_gpio_set_function( 22, GPIO_AF5 );
raspberrypi_gpio_set_function( 23, GPIO_AF5 );
bus->base_address = BCM2711_I2C6_BASE;
break;
default:
return RTEMS_INVALID_ADDRESS;
}
return RTEMS_SUCCESSFUL;
}
static char *rpi_select_bus( raspberrypi_bsc_masters device )
{
switch ( device ) {
case raspberrypi_bscm0:
return "/dev/i2c-0";
case raspberrypi_bscm1:
return "/dev/i2c-1";
case raspberrypi_bscm3:
return "/dev/i2c-3";
case raspberrypi_bscm4:
return "/dev/i2c-4";
case raspberrypi_bscm5:
return "/dev/i2c-5";
case raspberrypi_bscm6:
return "/dev/i2c-6";
default:
return NULL;
}
}
rtems_status_code rpi_i2c_init(
raspberrypi_bsc_masters device,
uint32_t bus_clock
)
{
raspberrypi_i2c_bus *bus;
rtems_status_code sc;
const char *bus_path;
if ( device != raspberrypi_bscm0 && device != raspberrypi_bscm1 &&
device != raspberrypi_bscm3 && device != raspberrypi_bscm4 &&
device != raspberrypi_bscm5 && device != raspberrypi_bscm6 ) {
return RTEMS_INVALID_NUMBER;
}
bus_path = rpi_select_bus( device );
if ( bus_path == NULL ) {
return RTEMS_INVALID_NUMBER;
}
bus = (raspberrypi_i2c_bus *) i2c_bus_alloc_and_init( sizeof( *bus ) );
if ( bus == NULL ) {
return RTEMS_NO_MEMORY;
}
sc = rpi_i2c_gpio_init( device, bus );
if ( sc != RTEMS_SUCCESSFUL ) {
i2c_bus_destroy_and_free( &bus->base );
return sc;
}
/* Enable I2C */
C_REG( bus ) = C_CLEAR;
C_REG( bus ) = C_I2CEN;
sc = rpi_i2c_set_clock( &bus->base, bus_clock );
if ( sc != RTEMS_SUCCESSFUL ) {
i2c_bus_destroy_and_free( &bus->base );
return sc;
}
bus->base.transfer = rpi_i2c_transfer;
bus->base.set_clock = rpi_i2c_set_clock;
bus->base.destroy = rpi_i2c_destroy;
bus->base.functionality = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
return i2c_bus_register( &bus->base, bus_path );
}

5
bsps/aarch64/raspberrypi/include/bsp.h
View File

@@ -54,16 +54,11 @@
/*Raspberry pi MMU initialization */
BSP_START_TEXT_SECTION void raspberrypi_4_setup_mmu_and_cache(void);
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void );
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define BSP_FDT_IS_SUPPORTED
extern const unsigned char bcm2711_rpi_4_b_dtb[];
extern const size_t bcm2711_rpi_4_b_dtb_size;
#define BSP_ARM_GIC_CPUIF_BASE 0xFF842000
#define BSP_ARM_GIC_DIST_BASE 0xFF841000

25
bsps/aarch64/raspberrypi/include/bsp/irq.h
View File

@@ -1,5 +1,3 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
@@ -13,26 +11,11 @@
* Copyright (c) 2022 Mohd Noor Aman
* Copyright (c) 2024 Ning Yang
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.org/license/LICENSE
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H

92
bsps/aarch64/raspberrypi/include/bsp/raspberrypi-i2c.h
View File

@@ -1,92 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup raspberrypi_4_i2c
*
* @brief Raspberry Pi specific I2C definitions.
*/
/*
* Copyright (C) 2025 Shaunak Datar
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_AARCH64_RASPBERRYPI_I2C_H
#define LIBBSP_AARCH64_RASPBERRYPI_I2C_H
#include <bsp/raspberrypi.h>
#include <bsp/rpi-gpio.h>
#include <bsp/utility.h>
#include <dev/i2c/i2c.h>
/**
* @brief I2C controller instances on Raspberry Pi 4.
*/
typedef enum {
/**
* @brief BSC Master 0 (GPIO 0/1)
*/
raspberrypi_bscm0,
/**
* @brief BSC Master 1 (GPIO 2/3)
*/
raspberrypi_bscm1,
/**
* @brief BSC Master 3 (GPIO 4/5)
*/
raspberrypi_bscm3,
/**
* @brief BSC Master 4 (GPIO 6/7)
*/
raspberrypi_bscm4,
/**
* @brief BSC Master 5 (GPIO 10/11)
*/
raspberrypi_bscm5,
/**
* @brief BSC Master 6 (GPIO 22/23)
*/
raspberrypi_bscm6
} raspberrypi_bsc_masters;
/**
* @brief Initialize the I2C bus for a specified master.
*
* @param device The BSC master to initialize.
* @param bus_clock The desired bus clock frequency in Hz.
*
* @return RTEMS status code indicating success or failure.
*/
rtems_status_code rpi_i2c_init(
raspberrypi_bsc_masters device,
uint32_t bus_clock
);
#endif /* LIBBSP_AARCH64_RASPBERRYPI_I2C_H */

110
bsps/aarch64/raspberrypi/include/bsp/raspberrypi-pwm.h
View File

@@ -1,110 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsAArch64Raspberrypi4
*
* @brief Raspberry Pi specific PWM definitions.
*/
/*
* Copyright (C) 2025 Shaunak Datar
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H
#define LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H
#include "bsp/raspberrypi.h"
#include "bsp/rpi-gpio.h"
#include "bsp/utility.h"
typedef enum { raspberrypi_pwm0, raspberrypi_pwm1 } raspberrypi_pwm_channel;
typedef enum {
raspberrypi_pwm_master0,
raspberrypi_pwm_master1
} raspberrypi_pwm_master;
/**
* @name PWM_CONTROL register bits
* @{
*/
#define C_MSEN2 BSP_BIT32( 15 ) /**< Channel 2 Mark-Space enable */
#define C_USEF2 BSP_BIT32( 13 ) /**< Channel 2 use FIFO */
#define C_POLA2 BSP_BIT32( 12 ) /**< Channel 2 invert polarity */
#define C_SBIT2 BSP_BIT32( 11 ) /**< Channel 2 silence bit high */
#define C_RPTL2 BSP_BIT32( 10 ) /**< Channel 2 repeat on underrun */
#define C_MODE2 BSP_BIT32( 9 ) /**< Channel 2 serializer mode */
#define C_PWEN2 BSP_BIT32( 8 ) /**< Channel 2 enable output */
#define C_MSEN1 BSP_BIT32( 7 ) /**< Channel 1 Mark-Space enable */
#define C_CLRF BSP_BIT32( 6 ) /**< Clear FIFO */
#define C_USEF1 BSP_BIT32( 5 ) /**< Channel 1 use FIFO */
#define C_POLA1 BSP_BIT32( 4 ) /**< Channel 1 invert polarity */
#define C_SBIT1 BSP_BIT32( 3 ) /**< Channel 1 silence bit high */
#define C_RPTL1 BSP_BIT32( 2 ) /**< Channel 1 repeat underrun */
#define C_MODE1 BSP_BIT32( 1 ) /**< Channel 1 serializer mode */
#define C_PWEN1 BSP_BIT32( 0 ) /**< Channel 1 enable output */
/** @} */
/**
* @brief Set PWM clock divider.
* @param divisor 1 – 4095; PWMCLK = 19.2 MHz / @p divisor.
* @retval RTEMS_SUCCESSFUL OK
* @retval RTEMS_INVALID_NUMBER 0 or >4095
*/
rtems_status_code rpi_pwm_set_clock( uint32_t divisor );
/**
* @brief Update duty-cycle register.
* @param master Selects the hardware instance to be used
* (raspberrypi_pwm_master0 = PWM0, raspberrypi_pwm_master1 = PWM1)
* @param channel Selects the channel for @p master (raspberrypi_pwm0 = PWMx_0,
* raspberrypi_pwm1 = PWMx_1)
* @param data Initial duty count, 1 – current range value.(0 rejected)
*/
rtems_status_code rpi_pwm_set_data(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel,
uint32_t data
);
/**
* @brief Main PWM initialization function. This functions sets up the PWM
* master, channel, duty cycle and GPIO pin.
* @param master Selects the hardware instance to be used
* (raspberrypi_pwm_master0 = PWM0, raspberrypi_pwm_master1 = PWM1)
* @param channel Selects the channel for @p master (raspberrypi_pwm0 = PWMx_0,
* raspberrypi_pwm1 = PWMx_1)
* @param range Period register value (> 0)
* @param data Initial duty count, 1 – @p range (0 rejected)
*/
rtems_status_code rpi_pwm_init(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel,
uint32_t range,
uint32_t data
);
#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H */

685
bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
View File

@@ -1,5 +1,3 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
@@ -9,38 +7,25 @@
*/
/*
* Copyright (c) 2022 Mohd Noor Aman
* Copyright (c) 2024 Ning Yang
* Copyright (c) 2025 Shaunak Datar
* Copyright (c) 2022 Mohd Noor Aman
* Copyright (c) 2024 Ning Yang
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.org/license/LICENSE
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
#include <bsp/utility.h>
#include <bspopts.h>
#include <stdint.h>
#include <bsp/utility.h>
/**
* @defgroup raspberrypi_reg Register Definitions
@@ -58,9 +43,9 @@
* @{
*/
#define BCM2711_REG( x ) ( *(volatile uintptr_t *) ( x ) )
#define BCM2711_BIT( n ) ( 1 << ( n ) )
#define BCM2835_REG( addr ) ( *(volatile uint32_t *) (uintptr_t) ( addr ) )
#define BCM2711_REG(x) (*(volatile uint64_t *)(x))
#define BCM2711_BIT(n) (1 << (n))
#define BCM2835_REG(addr) (*(volatile uint32_t*)(addr))
/** @} */
@@ -70,16 +55,16 @@
* @{
*/
#define RPI_PERIPHERAL_BASE 0xFE000000
#define BASE_OFFSET 0xFE000000
#define RPI_PERIPHERAL_SIZE 0x01800000
#define RPI_PERIPHERAL_BASE 0xFE000000
#define BASE_OFFSET 0xFE000000
#define RPI_PERIPHERAL_SIZE 0x01800000
/**
* @name Bus to Physical address translation
* Macro.
* @{
*/
#define BUS_TO_PHY( x ) ( ( x ) - BASE_OFFSET )
#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)
/** @} */
@@ -89,21 +74,21 @@
* @{
*/
#define BCM2711_CLOCK_FREQ 250000000
#define BCM2711_CLOCK_FREQ 250000000
#define BCM2711_TIMER_BASE ( RPI_PERIPHERAL_BASE + 0xB400 )
#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
#define BCM2711_TIMER_LOD ( BCM2711_TIMER_BASE + 0x00 )
#define BCM2711_TIMER_VAL ( BCM2711_TIMER_BASE + 0x04 )
#define BCM2711_TIMER_CTL ( BCM2711_TIMER_BASE + 0x08 )
#define BCM2711_TIMER_CLI ( BCM2711_TIMER_BASE + 0x0C )
#define BCM2711_TIMER_RIS ( BCM2711_TIMER_BASE + 0x10 )
#define BCM2711_TIMER_MIS ( BCM2711_TIMER_BASE + 0x14 )
#define BCM2711_TIMER_RLD ( BCM2711_TIMER_BASE + 0x18 )
#define BCM2711_TIMER_DIV ( BCM2711_TIMER_BASE + 0x1C )
#define BCM2711_TIMER_CNT ( BCM2711_TIMER_BASE + 0x20 )
#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)
#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)
#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)
#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)
#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)
#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)
#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)
#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)
#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)
#define BCM2711_TIMER_PRESCALE 0xF9
#define BCM2711_TIMER_PRESCALE 0xF9
/** @} */
@@ -113,56 +98,57 @@
* @{
*/
#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
#define BCM2711_PM_BASE ( RPI_PERIPHERAL_BASE + 0x100000 )
#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
#define BCM2711_PM_GNRIC ( BCM2711_PM_BASE + 0x00 )
#define BCM2711_PM_GNRIC_POWUP 0x00000001
#define BCM2711_PM_GNRIC_POWOK 0x00000002
#define BCM2711_PM_GNRIC_ISPOW 0x00000004
#define BCM2711_PM_GNRIC_MEMREP 0x00000008
#define BCM2711_PM_GNRIC_MRDONE 0x00000010
#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
#define BCM2711_PM_GNRIC_ENAB 0x00001000
#define BCM2711_PM_GNRIC_CFG 0x007f0000
#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)
#define BCM2711_PM_GNRIC_POWUP 0x00000001
#define BCM2711_PM_GNRIC_POWOK 0x00000002
#define BCM2711_PM_GNRIC_ISPOW 0x00000004
#define BCM2711_PM_GNRIC_MEMREP 0x00000008
#define BCM2711_PM_GNRIC_MRDONE 0x00000010
#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
#define BCM2711_PM_GNRIC_ENAB 0x00001000
#define BCM2711_PM_GNRIC_CFG 0x007f0000
#define BCM2711_PM_AUDIO ( BCM2711_PM_BASE + 0x04 )
#define BCM2711_PM_AUDIO_APSM 0x000fffff
#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
#define BCM2711_PM_AUDIO_RSTN 0x00200000
#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)
#define BCM2711_PM_AUDIO_APSM 0x000fffff
#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
#define BCM2711_PM_AUDIO_RSTN 0x00200000
#define BCM2711_PM_STATUS ( BCM2711_PM_BASE + 0x18 )
#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)
#define BCM2711_PM_RSTC ( BCM2711_PM_BASE + 0x1c )
#define BCM2711_PM_RSTC_DRCFG 0x00000003
#define BCM2711_PM_RSTC_WRCFG 0x00000030
#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
#define BCM2711_PM_RSTC_WRCFG_CLR 0xffffffcf
#define BCM2711_PM_RSTC_SRCFG 0x00000300
#define BCM2711_PM_RSTC_QRCFG 0x00003000
#define BCM2711_PM_RSTC_FRCFG 0x00030000
#define BCM2711_PM_RSTC_HRCFG 0x00300000
#define BCM2711_PM_RSTC_RESET 0x00000102
#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)
#define BCM2711_PM_RSTC_DRCFG 0x00000003
#define BCM2711_PM_RSTC_WRCFG 0x00000030
#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
#define BCM2711_PM_RSTC_WRCFG_CLR 0xffffffcf
#define BCM2711_PM_RSTC_SRCFG 0x00000300
#define BCM2711_PM_RSTC_QRCFG 0x00003000
#define BCM2711_PM_RSTC_FRCFG 0x00030000
#define BCM2711_PM_RSTC_HRCFG 0x00300000
#define BCM2711_PM_RSTC_RESET 0x00000102
#define BCM2711_PM_RSTS ( BCM2711_PM_BASE + 0x20 )
#define BCM2711_PM_RSTS_HADDRQ 0x00000001
#define BCM2711_PM_RSTS_HADDRF 0x00000002
#define BCM2711_PM_RSTS_HADDRH 0x00000004
#define BCM2711_PM_RSTS_HADWRQ 0x00000010
#define BCM2711_PM_RSTS_HADWRF 0x0000002
#define BCM2711_PM_RSTS_HADWRH 0x00000040
#define BCM2711_PM_RSTS_HADSRQ 0x00000100
#define BCM2711_PM_RSTS_HADSRF 0x00000200
#define BCM2711_PM_RSTS_HADSRH 0x00000400
#define BCM2711_PM_RSTS_HADPOR 0x00001000
#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)
#define BCM2711_PM_RSTS_HADDRQ 0x00000001
#define BCM2711_PM_RSTS_HADDRF 0x00000002
#define BCM2711_PM_RSTS_HADDRH 0x00000004
#define BCM2711_PM_RSTS_HADWRQ 0x00000010
#define BCM2711_PM_RSTS_HADWRF 0x0000002
#define BCM2711_PM_RSTS_HADWRH 0x00000040
#define BCM2711_PM_RSTS_HADSRQ 0x00000100
#define BCM2711_PM_RSTS_HADSRF 0x00000200
#define BCM2711_PM_RSTS_HADSRH 0x00000400
#define BCM2711_PM_RSTS_HADPOR 0x00001000
#define BCM2711_PM_WDOG ( BCM2711_PM_BASE + 0x24 )
#define BCM2711_PM_WDOG_MASK 0x000fffff
#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)
#define BCM2711_PM_WDOG_MASK 0x000fffff
/** @} */
/** @} */
/**
@@ -171,20 +157,20 @@
* @{
*/
#define BCM2711_AUX_BASE ( RPI_PERIPHERAL_BASE + 0x215000 )
#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
#define AUX_ENABLES ( BCM2711_AUX_BASE + 0x04 )
#define AUX_MU_IO_REG ( BCM2711_AUX_BASE + 0x40 )
#define AUX_MU_IER_REG ( BCM2711_AUX_BASE + 0x44 )
#define AUX_MU_IIR_REG ( BCM2711_AUX_BASE + 0x48 )
#define AUX_MU_LCR_REG ( BCM2711_AUX_BASE + 0x4C )
#define AUX_MU_MCR_REG ( BCM2711_AUX_BASE + 0x50 )
#define AUX_MU_LSR_REG ( BCM2711_AUX_BASE + 0x54 )
#define AUX_MU_MSR_REG ( BCM2711_AUX_BASE + 0x58 )
#define AUX_MU_SCRATCH ( BCM2711_AUX_BASE + 0x5C )
#define AUX_MU_CNTL_REG ( BCM2711_AUX_BASE + 0x60 )
#define AUX_MU_STAT_REG ( BCM2711_AUX_BASE + 0x64 )
#define AUX_MU_BAUD_REG ( BCM2711_AUX_BASE + 0x68 )
#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)
#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)
#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)
#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)
#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)
#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)
#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)
#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)
#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)
#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)
#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)
#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)
/** @} */
@@ -193,19 +179,19 @@
*
* @{
*/
#define BCM2711_PL011_BASE ( RPI_PERIPHERAL_BASE + 0x201000 )
#define BCM2711_PL011_SIZE 0xc00
#define BCM2711_PL011_BASE (RPI_PERIPHERAL_BASE + 0x201000)
#define BCM2711_PL011_SIZE 0xc00
#define BCM2711_PL011_DEVICE_SIZE 0x200
#define BCM2711_UART0_BASE ( BCM2711_PL011_BASE + 0x000 )
#define BCM2711_UART0_BASE (BCM2711_PL011_BASE + 0x000)
#define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
#define BCM2711_UART2_BASE ( BCM2711_PL011_BASE + 0x400 )
#define BCM2711_UART2_BASE (BCM2711_PL011_BASE + 0x400)
#define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
#define BCM2711_UART3_BASE ( BCM2711_PL011_BASE + 0x600 )
#define BCM2711_UART3_BASE (BCM2711_PL011_BASE + 0x600)
#define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
#define BCM2711_UART4_BASE ( BCM2711_PL011_BASE + 0x800 )
#define BCM2711_UART4_BASE (BCM2711_PL011_BASE + 0x800)
#define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
#define BCM2711_UART5_BASE ( BCM2711_PL011_BASE + 0xa00 )
#define BCM2711_UART5_BASE (BCM2711_PL011_BASE + 0xa00)
#define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
/** @} */
@@ -220,27 +206,27 @@
* it's own RTOS. 1 and 3 are available for use in
* RTEMS.
*/
#define BCM2711_GPU_TIMER_BASE ( RPI_PERIPHERAL_BASE + 0x3000 )
#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
#define BCM2711_GPU_TIMER_CS ( BCM2711_GPU_TIMER_BASE + 0x00 )
#define BCM2711_GPU_TIMER_CS_M0 0x00000001
#define BCM2711_GPU_TIMER_CS_M1 0x00000002
#define BCM2711_GPU_TIMER_CS_M2 0x00000004
#define BCM2711_GPU_TIMER_CS_M3 0x00000008
#define BCM2711_GPU_TIMER_CLO ( BCM2711_GPU_TIMER_BASE + 0x04 )
#define BCM2711_GPU_TIMER_CHI ( BCM2711_GPU_TIMER_BASE + 0x08 )
#define BCM2711_GPU_TIMER_C0 ( BCM2711_GPU_TIMER_BASE + 0x0C )
#define BCM2711_GPU_TIMER_C1 ( BCM2711_GPU_TIMER_BASE + 0x10 )
#define BCM2711_GPU_TIMER_C2 ( BCM2711_GPU_TIMER_BASE + 0x14 )
#define BCM2711_GPU_TIMER_C3 ( BCM2711_GPU_TIMER_BASE + 0x18 )
#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)
#define BCM2711_GPU_TIMER_CS_M0 0x00000001
#define BCM2711_GPU_TIMER_CS_M1 0x00000002
#define BCM2711_GPU_TIMER_CS_M2 0x00000004
#define BCM2711_GPU_TIMER_CS_M3 0x00000008
#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)
#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)
#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)
#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)
#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)
#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)
/**
* NOTE: compatible with the BCM2835 system timer
*/
#define BCM2835_GPU_TIMER_CS_M3 BCM2711_GPU_TIMER_CS_M3
#define BCM2835_GPU_TIMER_C3 BCM2711_GPU_TIMER_C3
#define BCM2835_GPU_TIMER_CLO BCM2711_GPU_TIMER_CLO
#define BCM2835_GPU_TIMER_CS BCM2711_GPU_TIMER_CS
#define BCM2835_GPU_TIMER_CS_M3 BCM2711_GPU_TIMER_CS_M3
#define BCM2835_GPU_TIMER_C3 BCM2711_GPU_TIMER_C3
#define BCM2835_GPU_TIMER_CLO BCM2711_GPU_TIMER_CLO
#define BCM2835_GPU_TIMER_CS BCM2711_GPU_TIMER_CS
/** @} */
/**
@@ -249,7 +235,7 @@
* @{
*/
#define BCM2711_GPIO_BASE ( RPI_PERIPHERAL_BASE + 0x200000 )
#define BCM2711_GPIO_BASE (RPI_PERIPHERAL_BASE + 0x200000)
#define BCM2711_GPIO_SIZE 0xf4
#define BCM2711_GPIO_PIN_COUNT 58
@@ -267,129 +253,76 @@
* the rtems-libbsd tree already provides the remaining registers.
*/
#define BCM2711_EMMC_BASE ( RPI_PERIPHERAL_BASE + 0x300000 )
#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
/** @} */
/**
* @name SPI Registers
*
* @{
*/
* @name SPI Registers
*
* @{
*/
#define BCM2711_SPI0_BASE ( RPI_PERIPHERAL_BASE + 0x204000 )
#define BCM2711_SPI3_BASE ( RPI_PERIPHERAL_BASE + 0x204600 )
#define BCM2711_SPI4_BASE ( RPI_PERIPHERAL_BASE + 0x204800 )
#define BCM2711_SPI5_BASE ( RPI_PERIPHERAL_BASE + 0x204A00 )
#define BCM2711_SPI6_BASE ( RPI_PERIPHERAL_BASE + 0x204C00 )
/** @} */
/**
* @name PWM Clock Manager Register and Offsets
*
* @{
*/
#define BCM2711_CM_PWM_BASE ( RPI_PERIPHERAL_BASE + 0x00101000 )
#define BCM2711_CM_PWM_CTL 0xA0
#define BCM2711_CM_PWM_DIV 0xA4
#define CM_PWM_PASSWD ( 0x5A << 24 )
#define CM_PWM_CTL_SRC_OSC BSP_BIT32( 0 )
#define CM_PWM_CTL_BUSY BSP_BIT32( 7 )
#define CM_PWM_CTL_ENAB BSP_BIT32( 4 )
#define CM_PWM_DIV_MASK 0xFFF
/** @} */
/**
* @name PWM Registers and offsets
*
* @{
*/
#define BCM2711_PWM0_BASE ( RPI_PERIPHERAL_BASE + 0x0020C000 )
#define BCM2711_PWM1_BASE ( RPI_PERIPHERAL_BASE + 0x0020C800 )
#define BCM2711_PWM_CONTROL 0x00
#define BCM2711_PWM_STATUS 0x04
#define BCM2711_PWM_DMAC 0x08
#define BCM2711_PWM_RNG1 0x10
#define BCM2711_PWM_DAT1 0x14
#define BCM2711_PWM_FIFO 0x18
#define BCM2711_PWM_RNG2 0x20
#define BCM2711_PWM_DAT2 0x24
/** @} */
/**
* @name I2C Registers
*
* @{
*/
#define BCM2711_I2C0_BASE ( RPI_PERIPHERAL_BASE + 0x00205000 )
#define BCM2711_I2C1_BASE ( RPI_PERIPHERAL_BASE + 0x00804000 )
#define BCM2711_I2C3_BASE ( RPI_PERIPHERAL_BASE + 0x00205600 )
#define BCM2711_I2C4_BASE ( RPI_PERIPHERAL_BASE + 0x00205800 )
#define BCM2711_I2C5_BASE ( RPI_PERIPHERAL_BASE + 0x00205a80 )
#define BCM2711_I2C6_BASE ( RPI_PERIPHERAL_BASE + 0x00205c00 )
#define BCM2711_I2C_CONTROL 0x0
#define BCM2711_I2C_STATUS 0x4
#define BCM2711_I2C_DLEN 0x8
#define BCM2711_I2C_SLAVE_ADDRESS 0xc
#define BCM2711_I2C_FIFO 0x10
#define BCM2711_I2C_DIV 0x14
#define BCM2711_DELAY 0x18
#define BCM2711_I2C_CLKT 0x1c
#define BCM2711_I2C_FIFO_MASK 0xFF
#define BCM2711_I2C_DLEN_MASK 0xFFFF
#define BCM2711_10_BIT_ADDR_MASK 0x78
/** @} */
/**
* @name Mailbox Registers
*
* @{
*/
#define BCM2711_MBOX_BASE ( RPI_PERIPHERAL_BASE + 0xB880 )
#define BCM2711_MBOX_READ ( BCM2711_MBOX_BASE + 0x00 )
#define BCM2711_MBOX_PEEK ( BCM2711_MBOX_BASE + 0x10 )
#define BCM2711_MBOX_SENDER ( BCM2711_MBOX_BASE + 0x14 )
#define BCM2711_MBOX_STATUS ( BCM2711_MBOX_BASE + 0x18 )
#define BCM2711_MBOX_WRITE ( BCM2711_MBOX_BASE + 0x20 )
#define BCM2711_MBOX_CONFIG ( BCM2711_MBOX_BASE + 0x1C )
#define BCM2711_MBOX_RESPONSE 0x80000000
#define BCM2711_MBOX_FULL 0x80000000
#define BCM2711_MBOX_EMPTY 0x40000000
#define BCM2711_SPI0_BASE (RPI_PERIPHERAL_BASE + 0x204000)
#define BCM2711_SPI3_BASE (RPI_PERIPHERAL_BASE + 0x204600)
#define BCM2711_SPI4_BASE (RPI_PERIPHERAL_BASE + 0x204800)
#define BCM2711_SPI5_BASE (RPI_PERIPHERAL_BASE + 0x204A00)
#define BCM2711_SPI6_BASE (RPI_PERIPHERAL_BASE + 0x204C00)
/** @} */
/**
* @name Mailbox Channels
*
* @{
*/
* @name Mailbox Registers
*
* @{
*/
#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)
#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)
#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)
#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)
#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)
#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)
#define BCM2711_MBOX_RESPONSE 0x80000000
#define BCM2711_MBOX_FULL 0x80000000
#define BCM2711_MBOX_EMPTY 0x40000000
/** @} */
/**
* @name Mailbox Channels
*
* @{
*/
/* Power Manager channel */
#define BCM2711_MBOX_CHANNEL_PM 0
#define BCM2711_MBOX_CHANNEL_PM 0
/* Framebuffer channel */
#define BCM2711_MBOX_CHANNEL_FB 1
/* Virtual UART channel */
#define BCM2711_MBOX_CHANNEL_VUART 2
/* VCHIQ channel */
#define BCM2711_MBOX_CHANNEL_VCHIQ 3
/* LEDs channel */
#define BCM2711_MBOX_CHANNEL_LED 4
/* Button channel */
#define BCM2711_MBOX_CHANNEL_BUTTON 5
/* Touch screen channel */
#define BCM2711_MBOX_CHANNEL_TOUCHS 6
#define BCM2711_MBOX_CHANNEL_FB 1
/* Virtual UART channel */
#define BCM2711_MBOX_CHANNEL_VUART 2
/* VCHIQ channel */
#define BCM2711_MBOX_CHANNEL_VCHIQ 3
/* LEDs channel */
#define BCM2711_MBOX_CHANNEL_LED 4
/* Button channel */
#define BCM2711_MBOX_CHANNEL_BUTTON 5
/* Touch screen channel */
#define BCM2711_MBOX_CHANNEL_TOUCHS 6
#define BCM2711_MBOX_CHANNEL_COUNT 7
#define BCM2711_MBOX_CHANNEL_COUNT 7
/* Property tags (ARM <-> VC) channel */
#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
/* Property tags (VC <-> ARM) channel */
#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
/* Property tags (VC <-> ARM) channel */
#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
/** @} */
/**
* @name Raspberry Pi 2 Interrupt Register Defines
*
@@ -397,13 +330,14 @@
*/
/* Timers interrupt control registers */
#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
(BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
#define BCM2711_CORE_TIMER_IRQ_CTRL( cpuidx ) \
( BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * ( cpuidx ) )
/**
* @name Raspberry Pi 4 ARM_LOCAL registers
@@ -411,37 +345,37 @@
* @{
*/
#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
#define BCM2711_LOCAL_REGS_SIZE 0x100
#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
#define BCM2711_LOCAL_REGS_SIZE 0x100
#define BCM2711_LOCAL_ARM_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x00 )
#define BCM2711_LOCAL_CORE_IRQ_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x0c )
#define BCM2711_LOCAL_PMU_CONTROL_SET ( BCM2711_LOCAL_REGS_BASE + 0x10 )
#define BCM2711_LOCAL_PMU_CONTROL_CLR ( BCM2711_LOCAL_REGS_BASE + 0x14 )
#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 ( BCM2711_LOCAL_REGS_BASE + 0x24 )
#define BCM2711_LOCAL_AXI_QUIET_TIME ( BCM2711_LOCAL_REGS_BASE + 0x30 )
#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x34 )
#define BCM2711_LOCAL_LOCAL_TIMER_IRQ ( BCM2711_LOCAL_REGS_BASE + 0x38 )
#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)
#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)
#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)
#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)
#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)
#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)
#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)
#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)
#define BCM2711_LOCAL_TIMER_CNTRL0 ( BCM2711_LOCAL_REGS_BASE + 0x40 )
#define BCM2711_LOCAL_TIMER_CNTRL1 ( BCM2711_LOCAL_REGS_BASE + 0x44 )
#define BCM2711_LOCAL_TIMER_CNTRL2 ( BCM2711_LOCAL_REGS_BASE + 0x48 )
#define BCM2711_LOCAL_TIMER_CNTRL3 ( BCM2711_LOCAL_REGS_BASE + 0x4c )
#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)
#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)
#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)
#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)
#define BCM2711_LOCAL_MAILBOX_CNTRL0 ( BCM2711_LOCAL_REGS_BASE + 0x50 )
#define BCM2711_LOCAL_MAILBOX_CNTRL1 ( BCM2711_LOCAL_REGS_BASE + 0x54 )
#define BCM2711_LOCAL_MAILBOX_CNTRL2 ( BCM2711_LOCAL_REGS_BASE + 0x58 )
#define BCM2711_LOCAL_MAILBOX_CNTRL3 ( BCM2711_LOCAL_REGS_BASE + 0x5c )
#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)
#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)
#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)
#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)
#define BCM2711_LOCAL_IRQ_SOURCE0 ( BCM2711_LOCAL_REGS_BASE + 0x60 )
#define BCM2711_LOCAL_IRQ_SOURCE1 ( BCM2711_LOCAL_REGS_BASE + 0x64 )
#define BCM2711_LOCAL_IRQ_SOURCE2 ( BCM2711_LOCAL_REGS_BASE + 0x68 )
#define BCM2711_LOCAL_IRQ_SOURCE3 ( BCM2711_LOCAL_REGS_BASE + 0x6c )
#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)
#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)
#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)
#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)
#define BCM2711_LOCAL_FIQ_SOURCE0 ( BCM2711_LOCAL_REGS_BASE + 0x70 )
#define BCM2711_LOCAL_FIQ_SOURCE1 ( BCM2711_LOCAL_REGS_BASE + 0x74 )
#define BCM2711_LOCAL_FIQ_SOURCE2 ( BCM2711_LOCAL_REGS_BASE + 0x78 )
#define BCM2711_LOCAL_FIQ_SOURCE3 ( BCM2711_LOCAL_REGS_BASE + 0x7c )
#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)
#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)
#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)
#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)
/**
* @name Raspberry Pi 4 Mailbox registers
@@ -449,39 +383,42 @@
* @{
*/
#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
/**
* @name Raspberry Pi 4 ARM_C FIQ and IRQ registers
@@ -489,96 +426,102 @@
* @{
*/
#define BCM2711_ARMC_REGS_BASE ( RPI_PERIPHERAL_BASE + 0xB200 )
#define BCM2711_ARMC_REGS_SIZE 0x200
#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)
#define BCM2711_ARMC_REGS_SIZE 0x200
#define BCM2711_ARMC_IRQ0_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x00 )
#define BCM2711_ARMC_IRQ0_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x04 )
#define BCM2711_ARMC_IRQ0_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x08 )
#define BCM2711_ARMC_IRQ0_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x10 )
#define BCM2711_ARMC_IRQ0_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x14 )
#define BCM2711_ARMC_IRQ0_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x18 )
#define BCM2711_ARMC_IRQ0_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x20 )
#define BCM2711_ARMC_IRQ0_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x24 )
#define BCM2711_ARMC_IRQ0_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x28 )
#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00)
#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04)
#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08)
#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10)
#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14)
#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18)
#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20)
#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24)
#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28)
#define BCM2711_ARMC_IRQ_STATUS0 ( BCM2711_ARMC_REGS_BASE + 0x30 )
#define BCM2711_ARMC_IRQ_STATUS1 ( BCM2711_ARMC_REGS_BASE + 0x34 )
#define BCM2711_ARMC_IRQ_STATUS2 ( BCM2711_ARMC_REGS_BASE + 0x38 )
#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30)
#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34)
#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)
#define BCM2711_ARMC_IRQ1_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x40 )
#define BCM2711_ARMC_IRQ1_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x44 )
#define BCM2711_ARMC_IRQ1_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x48 )
#define BCM2711_ARMC_IRQ1_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x50 )
#define BCM2711_ARMC_IRQ1_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x54 )
#define BCM2711_ARMC_IRQ1_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x58 )
#define BCM2711_ARMC_IRQ1_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x60 )
#define BCM2711_ARMC_IRQ1_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x64 )
#define BCM2711_ARMC_IRQ1_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x68 )
#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40)
#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44)
#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48)
#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50)
#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54)
#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58)
#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60)
#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64)
#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68)
#define BCM2711_ARMC_IRQ2_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x80 )
#define BCM2711_ARMC_IRQ2_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x84 )
#define BCM2711_ARMC_IRQ2_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x88 )
#define BCM2711_ARMC_IRQ2_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x90 )
#define BCM2711_ARMC_IRQ2_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x94 )
#define BCM2711_ARMC_IRQ2_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x98 )
#define BCM2711_ARMC_IRQ2_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xA0 )
#define BCM2711_ARMC_IRQ2_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xA4 )
#define BCM2711_ARMC_IRQ2_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xA8 )
#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80)
#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84)
#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88)
#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90)
#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94)
#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98)
#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0)
#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4)
#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8)
#define BCM2711_ARMC_IRQ3_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0xC0 )
#define BCM2711_ARMC_IRQ3_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0xC4 )
#define BCM2711_ARMC_IRQ3_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0xC8 )
#define BCM2711_ARMC_IRQ3_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xD0 )
#define BCM2711_ARMC_IRQ3_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xD4 )
#define BCM2711_ARMC_IRQ3_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xD8 )
#define BCM2711_ARMC_IRQ3_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xE0 )
#define BCM2711_ARMC_IRQ3_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xE4 )
#define BCM2711_ARMC_IRQ3_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xE8 )
#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0)
#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4)
#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8)
#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0)
#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4)
#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8)
#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0)
#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4)
#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)
#define BCM2711_ARMC_FIQ0_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x100 )
#define BCM2711_ARMC_FIQ0_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x104 )
#define BCM2711_ARMC_FIQ0_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x108 )
#define BCM2711_ARMC_FIQ0_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x110 )
#define BCM2711_ARMC_FIQ0_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x114 )
#define BCM2711_ARMC_FIQ0_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x118 )
#define BCM2711_ARMC_FIQ0_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x120 )
#define BCM2711_ARMC_FIQ0_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x124 )
#define BCM2711_ARMC_FIQ0_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x128 )
#define BCM2711_ARMC_FIQ1_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x140 )
#define BCM2711_ARMC_FIQ1_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x144 )
#define BCM2711_ARMC_FIQ1_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x148 )
#define BCM2711_ARMC_FIQ1_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x150 )
#define BCM2711_ARMC_FIQ1_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x154 )
#define BCM2711_ARMC_FIQ1_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x158 )
#define BCM2711_ARMC_FIQ1_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x160 )
#define BCM2711_ARMC_FIQ1_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x164 )
#define BCM2711_ARMC_FIQ1_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x168 )
#define BCM2711_ARMC_FIQ2_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x180 )
#define BCM2711_ARMC_FIQ2_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x184 )
#define BCM2711_ARMC_FIQ2_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x188 )
#define BCM2711_ARMC_FIQ2_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x190 )
#define BCM2711_ARMC_FIQ2_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x194 )
#define BCM2711_ARMC_FIQ2_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x198 )
#define BCM2711_ARMC_FIQ2_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1A0 )
#define BCM2711_ARMC_FIQ2_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1A4 )
#define BCM2711_ARMC_FIQ2_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1A8 )
#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100)
#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104)
#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108)
#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110)
#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114)
#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118)
#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120)
#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124)
#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)
#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140)
#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144)
#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148)
#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150)
#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154)
#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158)
#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160)
#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164)
#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)
#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180)
#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184)
#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188)
#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190)
#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194)
#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198)
#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0)
#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4)
#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)
#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0)
#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4)
#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8)
#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0)
#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4)
#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8)
#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0)
#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4)
#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)
#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0)
#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4)
#define BCM2711_ARMC_FIQ3_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x1C0 )
#define BCM2711_ARMC_FIQ3_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x1C4 )
#define BCM2711_ARMC_FIQ3_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x1C8 )
#define BCM2711_ARMC_FIQ3_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1D0 )
#define BCM2711_ARMC_FIQ3_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1D4 )
#define BCM2711_ARMC_FIQ3_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1D8 )
#define BCM2711_ARMC_FIQ3_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1E0 )
#define BCM2711_ARMC_FIQ3_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1E4 )
#define BCM2711_ARMC_FIQ3_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1E8 )
#define BCM2711_ARMC_SWIRQ_SET ( BCM2711_ARMC_REGS_BASE + 0x1F0 )
#define BCM2711_ARMC_SWIRQ_CLEAR ( BCM2711_ARMC_REGS_BASE + 0x1F4 )
/** @} */
#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */

198
bsps/aarch64/raspberrypi/pwm/raspberrypi-pwm.c
View File

@@ -1,198 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsAArch64Raspberrypi4
*
* @brief PWM Support
*/
/*
* Copyright (C) 2025 Shaunak Datar
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "bsp/raspberrypi-pwm.h"
// Clock manager macros
#define BCM2711_CM_PWM( x ) BCM2835_REG( BCM2711_CM_PWM_BASE + ( x ) )
#define CM_PWM_CTL_ENABLE_OSC \
( CM_PWM_PASSWD | CM_PWM_CTL_ENAB | CM_PWM_CTL_SRC_OSC )
#define CM_PWM_CTL_DISABLE ( CM_PWM_PASSWD | CM_PWM_CTL_SRC_OSC )
static inline bool rpi_pwm_validate(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel
)
{
return ( ( master == raspberrypi_pwm_master0 ) ||
( master == raspberrypi_pwm_master1 ) ) &&
( ( channel == raspberrypi_pwm0 ) || ( channel == raspberrypi_pwm1 ) );
}
rtems_status_code rpi_pwm_set_clock( uint32_t divisor )
{
if ( !( divisor > 0 && divisor < 4096 ) ) {
return RTEMS_INVALID_NUMBER;
}
/* Stop Clock */
BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) = CM_PWM_CTL_DISABLE;
while ( BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) & CM_PWM_CTL_BUSY );
/* Set divisor */
divisor &= CM_PWM_DIV_MASK;
BCM2711_CM_PWM( BCM2711_CM_PWM_DIV ) = CM_PWM_PASSWD | ( divisor << 12 );
/* Select src = osc(1) and enable */
BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) = CM_PWM_CTL_ENABLE_OSC;
while ( !( BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) & CM_PWM_CTL_BUSY ) );
return RTEMS_SUCCESSFUL;
}
static rtems_status_code rpi_pwm_set_control(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel
)
{
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
BCM2711_PWM0_BASE :
BCM2711_PWM1_BASE;
uint32_t control_reg = pwm_base + BCM2711_PWM_CONTROL;
uint32_t control = BCM2835_REG( control_reg );
if ( channel == raspberrypi_pwm0 ) {
control &= ~( C_MODE1 | C_POLA1 | C_SBIT1 | C_RPTL1 | C_USEF1 );
control |= ( C_PWEN1 | C_CLRF | C_MSEN1 );
} else {
control &= ~( C_MODE2 | C_POLA2 | C_SBIT2 | C_RPTL2 | C_USEF2 );
control |= ( C_PWEN2 | C_CLRF | C_MSEN2 );
}
BCM2835_REG( control_reg ) = control;
return RTEMS_SUCCESSFUL;
}
static rtems_status_code rpi_pwm_set_range(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel,
uint32_t range
)
{
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
BCM2711_PWM0_BASE :
BCM2711_PWM1_BASE;
uint32_t range_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_RNG1 :
BCM2711_PWM_RNG2;
BCM2835_REG( pwm_base + range_offset ) = range;
return RTEMS_SUCCESSFUL;
}
rtems_status_code rpi_pwm_set_data(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel,
uint32_t data
)
{
if ( !( rpi_pwm_validate( master, channel ) ) || data == 0 ) {
return RTEMS_INVALID_NUMBER;
}
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
BCM2711_PWM0_BASE :
BCM2711_PWM1_BASE;
uint32_t range_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_RNG1 :
BCM2711_PWM_RNG2;
if ( data > BCM2835_REG( pwm_base + range_offset ) ) {
return RTEMS_INVALID_NUMBER;
}
uint32_t data_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_DAT1 :
BCM2711_PWM_DAT2;
BCM2835_REG( pwm_base + data_offset ) = data;
return RTEMS_SUCCESSFUL;
}
static rtems_status_code rpi_pwm_set_gpio(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel
)
{
rtems_status_code sc;
if ( master == raspberrypi_pwm_master0 ) {
if ( channel == raspberrypi_pwm0 ) {
sc = raspberrypi_gpio_set_function( 18, GPIO_AF5 );
} else {
sc = raspberrypi_gpio_set_function( 19, GPIO_AF5 );
}
} else {
if ( channel == raspberrypi_pwm0 ) {
sc = raspberrypi_gpio_set_function( 40, GPIO_AF0 );
} else {
sc = raspberrypi_gpio_set_function( 41, GPIO_AF0 );
}
}
return sc;
}
rtems_status_code rpi_pwm_init(
raspberrypi_pwm_master master,
raspberrypi_pwm_channel channel,
uint32_t range,
uint32_t data
)
{
rtems_status_code sc;
if ( !( rpi_pwm_validate( master, channel ) ) || range == 0 ) {
return RTEMS_INVALID_NUMBER;
}
sc = rpi_pwm_set_gpio( master, channel );
if ( sc != RTEMS_SUCCESSFUL ) {
return sc;
}
sc = rpi_pwm_set_range( master, channel, range );
if ( sc != RTEMS_SUCCESSFUL ) {
return sc;
}
sc = rpi_pwm_set_data( master, channel, data );
if ( sc != RTEMS_SUCCESSFUL ) {
return sc;
}
sc = rpi_pwm_set_control( master, channel );
if ( sc != RTEMS_SUCCESSFUL ) {
return sc;
}
return RTEMS_SUCCESSFUL;
}

29
bsps/aarch64/raspberrypi/start/bspstarthooks.c
View File

@@ -39,15 +39,7 @@
#include <bsp/start.h>
#include <rtems/score/cpu.h>
#ifdef RTEMS_SMP
#include <rtems/score/aarch64-system-registers.h>
#include <rtems/score/smpimpl.h>
#include <rtems/score/smp.h>
#include <bsp/irq-generic.h>
#endif
#ifdef BSP_START_ENABLE_EL3_START_SUPPORT
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
/* Do nothing */
@@ -56,27 +48,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
{
#ifdef RTEMS_SMP
uint32_t cpu_index_self = _SMP_Get_current_processor();
if ( cpu_index_self != 0 ) {
if (
cpu_index_self >= rtems_configuration_get_maximum_processors()
|| !_SMP_Should_start_processor( cpu_index_self )
) {
while ( true ) {
_AARCH64_Wait_for_event();
}
}
AArch64_start_set_vector_base();
arm_gic_irq_initialize_secondary_cpu();
rpi_setup_secondary_cpu_mmu_and_cache();
bsp_interrupt_vector_enable( ARM_GIC_IRQ_SGI_0 );
_SMP_Start_multitasking_on_secondary_processor(
_Per_CPU_Get_by_index( cpu_index_self )
);
}
#endif
AArch64_start_set_vector_base();
bsp_start_copy_sections();
raspberrypi_4_setup_mmu_and_cache();

28
bsps/aarch64/raspberrypi/start/bspstartmmu.c
View File

@@ -57,22 +57,10 @@ raspberrypi_4_mmu_config_table[] = {
.flags = AARCH64_MMU_DEVICE
},
{ /* RPI firmware-owned addresses including spintables */
.begin = (unsigned)0x0,
.end = (unsigned)0x1000,
.flags = AARCH64_MMU_DEVICE
},
{ /* RPI GIC Interface address */
.begin = 0xFF800000U,
.end = 0xFFA00000U,
.flags = AARCH64_MMU_DEVICE
},
{ /* RPI genet address */
.begin = (unsigned)0xFD580000,
.end = (unsigned)0xFD580000 + (unsigned)0x10000,
.flags = AARCH64_MMU_DEVICE
}
};
@@ -97,19 +85,3 @@ raspberrypi_4_setup_mmu_and_cache( void )
aarch64_mmu_enable( control );
}
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void )
__attribute__ ( ( weak ) );
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void )
{
aarch64_mmu_control *control = &aarch64_mmu_instance;
/* Perform basic MMU setup */
aarch64_mmu_setup();
/* Use the existing root page table already configured by CPU0 */
_AArch64_Write_ttbr0_el1( (uintptr_t) bsp_translation_table_base );
aarch64_mmu_enable( control );
}

2
bsps/aarch64/shared/clock/arm-generic-timer-aarch64.c
View File

@@ -106,7 +106,7 @@ void arm_generic_timer_get_config( uint32_t *frequency, uint32_t *irq )
);
*frequency = val;
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
#ifdef ARM_GENERIC_TIMER_USE_VIRTUAL
*irq = BSP_TIMER_VIRT_PPI;
#elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
*irq = BSP_TIMER_PHYS_S_PPI;

23
bsps/aarch64/shared/start/start.S
View File

@@ -37,35 +37,12 @@
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
#include <bsp.h>
#include <bspopts.h>
/* Global symbols */
.globl _start
.section ".bsp_start_text", "ax"
#ifdef BSP_START_IMAGE_HEADER
/*
* This format is defined by:
* https://www.kernel.org/doc/Documentation/arm64/booting.txt
*/
mov x0, x0
b _start
/*
* This must be defined by the BSP as different environments may not treat it
* the same. Xen treats it as an offset from 0x40000000 while QEMU treats it
* as an absolute offset (RAM origin + load offset).
*/
.dword BSP_START_IMAGE_HEADER_LOAD_OFFSET
.dword 0 /* image size */
.dword 0 /* kernel flags, LE, page size unspecified, place near RAM start */
.dword 0 /* reserved 2 */
.dword 0 /* reserved 3 */
.dword 0 /* reserved 4 */
.word 0x644d5241 /* magic, ascii ['A', 'R', 'M', 64] LE */
.word 0 /* reserved 5, PE COFF offset */
#endif /* BSP_START_IMAGE_HEADER */
/* Start entry */
_start:

70
bsps/aarch64/xen/start/mmu-config.c
View File

@@ -1,70 +0,0 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSBSPsAArch64Xen
*
* @brief This source file contains the definition of ::aarch64_mmu_config_table
* and ::aarch64_mmu_config_table_size.
*/
/*
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
#include <bsp/aarch64-mmu.h>
#include <bsp/start.h>
#include <libcpu/mmu-vmsav8-64.h>
BSP_START_DATA_SECTION const aarch64_mmu_config_entry
aarch64_mmu_config_table[] = {
AARCH64_MMU_DEFAULT_SECTIONS,
{
.begin = 0xf9000000U,
.end = 0xf9100000U,
.flags = AARCH64_MMU_DEVICE
}, {
.begin = 0xfd000000U,
.end = 0xffc00000U,
.flags = AARCH64_MMU_DEVICE
}, {
.begin = BSP_XEN_VPL011_BASE,
.end = BSP_XEN_VPL011_BASE + BSP_XEN_VPL011_LENGTH,
.flags = AARCH64_MMU_DEVICE
}, {
.begin = BSP_ARM_GIC_CPUIF_BASE,
.end = BSP_ARM_GIC_CPUIF_BASE + BSP_ARM_GIC_CPUIF_LENGTH,
.flags = AARCH64_MMU_DEVICE
}, {
.begin = BSP_ARM_GIC_DIST_BASE,
.end = BSP_ARM_GIC_DIST_BASE + BSP_ARM_GIC_DIST_LENGTH,
.flags = AARCH64_MMU_DEVICE
}
};
BSP_START_DATA_SECTION const size_t aarch64_mmu_config_table_size =
RTEMS_ARRAY_SIZE(aarch64_mmu_config_table);

1
bsps/arm/altera-cyclone-v/config/altcycv_devkit.cfg Normal file
View File

@@ -0,0 +1 @@
include $(RTEMS_ROOT)/make/custom/altcycv.inc

27
bsps/arm/atsam/config/atsamv-testsuite.tcfg Normal file
View File

@@ -0,0 +1,27 @@
#
# The ATSAMV BSP has too little memory for some tests.
#
exclude: fileio
exclude: flashdisk01
exclude: fsdosfsname01
exclude: ftp01
exclude: jffs2_fserror
exclude: jffs2_fslink
exclude: jffs2_fspatheval
exclude: jffs2_fspermission
exclude: jffs2_fsrdwr
exclude: jffs2_fsscandir01
exclude: jffs2_fssymlink
exclude: jffs2_fstime
exclude: linpack
exclude: mghttpd01
exclude: pppd
exclude: psxconfig01
exclude: record02
exclude: sp16
exclude: sp25
exclude: sp48
exclude: spregion_err01
exclude: spstkalloc02
exclude: tmfine01

9
bsps/arm/atsam/config/atsamv.cfg Normal file
View File

@@ -0,0 +1,9 @@
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -mthumb -mcpu=cortex-m7 -mfpu=fpv5-d16 -mfloat-abi=hard
CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

8
bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c
View File

@@ -196,7 +196,7 @@ void BOARD_ConfigureSdram(void)
SDRAMC->SDRAMC_MDR = BOARD_Sdram_Config.sdramc_mdr;
#endif /* __rtems__ */
/* 4. A minimum pause of 200 us is provided to precede any signal toggle.*/
/* 4. A minimum pause of 200 <EFBFBD><EFBFBD>s is provided to precede any signal toggle.*/
for (i = 0; i < 100000; i++);
/* 5. (1)A NOP command is issued to the SDRAM devices. The application must
@@ -277,10 +277,10 @@ void BOARD_ConfigureSdram(void)
/* 11. Write the refresh rate into the count field in the SDRAMC Refresh
Timer register. (Refresh rate = delay between refresh cycles).
The SDRAM device requires a refresh every 15.625 us or 7.81 us.
The SDRAM device requires a refresh every 15.625 <EFBFBD><EFBFBD>s or 7.81 <EFBFBD><EFBFBD>s.
With a 100 MHz frequency, the Refresh Timer Counter Register must be set
with the value 1562(15.625 us x 100 MHz) or 781(7.81 us x 100 MHz). */
// For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 us
with the value 1562(15.625 <EFBFBD><EFBFBD>s x 100 MHz) or 781(7.81 <EFBFBD><EFBFBD>s x 100 MHz). */
// For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 <EFBFBD><EFBFBD>s
/* ((32 x 10(^-3))/2048) x150 x (10^6) */
#ifndef __rtems__
SDRAMC->SDRAMC_TR = 1562;

2
bsps/arm/atsam/contrib/libraries/libchip/source/aes.c
View File

@@ -249,7 +249,7 @@ void AES_SetGcmHash(uint32_t *hash)
/**
* \brief Get The four 32-bit Tag which contain the final 128-bit GCM
* Authentication tag T when GCM processing is complete.
* Authentication tag <EFBFBD><EFBFBD>T<EFBFBD><EFBFBD> when GCM processing is complete.
* \param tag point to the word of the tag.
*/
void AES_GetGcmTag(uint32_t *tag)

2
bsps/arm/atsam/contrib/libraries/libchip/source/sdramc.c
View File

@@ -128,7 +128,7 @@ extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
/* Step 4 */
/* A minimum pause of 200 us is provided to precede any signal toggle.
/* A minimum pause of 200 <EFBFBD><EFBFBD>s is provided to precede any signal toggle.
(6 core cycles per iteration) */
for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);

2
bsps/arm/beagle/config/beagleboardorig.cfg Normal file
View File

@@ -0,0 +1,2 @@
# Config file for Original BeagleBoard
include $(RTEMS_ROOT)/make/custom/beagle.inc

2
bsps/arm/beagle/config/beagleboardxm.cfg Normal file
View File

@@ -0,0 +1,2 @@
# Config file for BeagleBoard XM
include $(RTEMS_ROOT)/make/custom/beagle.inc

17
bsps/arm/beagle/config/beagleboneblack-testsuite.tcfg Normal file
View File

@@ -0,0 +1,17 @@
#
# Beagleboneblack RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
expected-fail: dl06
expected-fail: i2c01
expected-fail: psxfenv01
expected-fail: spcache01
expected-fail: spintrcritical05
expected-fail: spintrcritical10
expected-fail: spintrcritical20
expected-fail: spintrcritical21
expected-fail: spsysinit01
expected-fail: tmcontext01
expected-fail: tmtimer01

2
bsps/arm/beagle/config/beagleboneblack.cfg Normal file
View File

@@ -0,0 +1,2 @@
# Config file for BeagleBone Black
include $(RTEMS_ROOT)/make/custom/beagle.inc

2
bsps/arm/beagle/config/beaglebonewhite.cfg Normal file
View File

@@ -0,0 +1,2 @@
# Config file for Original BeagleBone (aka BeagleBone White)
include $(RTEMS_ROOT)/make/custom/beagle.inc

174
bsps/arm/beagle/simscripts/bbxm.cfg Normal file
View File

@@ -0,0 +1,174 @@
# Start with: openocd -f interface/ftdi/flyswatter.cfg -f bbxm.cfg -c 'reset init'
# or with: openocd -f interface/ftdi/flyswatter2.cfg -f bbxm.cfg -c 'reset init'
source [find board/ti_beagleboard_xm.cfg]
#
# Use the MLO file from uboot to initialise the board.
#
proc beagleboard_xm_mlo { file } {
global _CHIPNAME
adapter_khz 10
catch { mww phys 0x48307250 0x00000004 }
reset init
icepick_c_wreset $_CHIPNAME.jrc
halt
dm37x.cpu arm core_state arm
puts "Beagleboard xM MLO: $file"
load_image $file 0x402005f8 bin
resume 0x40200800
sleep 500
halt
}
proc beagleboard_xm_init {} {
global _CHIPNAME
adapter_khz 10
catch { mww phys 0x48307250 0x00000004 }
reset init
icepick_c_wreset $_CHIPNAME.jrc
halt
dm37x.cpu arm core_state arm
mwh 0x6e00007c 0x000000ff ;# omap-gpmc
mwh 0x6e00007c 0x00000090 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e00007c 0x00000000 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e000080 0x00000000 ;# omap-gpmc
mwh 0x6e00007c 0x00000030 ;# omap-gpmc
mww 0x48004c00 0x00000020 ;# omap3_cm
mww 0x48004c10 0x00000020 ;# omap3_cm
mww 0x48314048 0x0000aaaa ;# omap3_mpu_wdt
mww 0x48314048 0x00005555 ;# omap3_mpu_wdt
mww 0x6c000048 0xffffffff ;# omap3_sms
mww 0x48004c40 0x00000013 ;# omap3_cm
mww 0x48004c10 0x00000025 ;# omap3_cm
mww 0x48004c00 0x00000021 ;# omap3_cm
mww 0x48306d40 0x00000003 ;# omap3_prm
mww 0x48307270 0x00000083 ;# omap3_prm
mww 0x48307270 0x00000080 ;# omap3_prm
mww 0x48004904 0x00000015 ;# omap3_cm
mww 0x48004d00 0x00110016 ;# omap3_cm
mww 0x48005140 0x10020a50 ;# omap3_cm
mww 0x48004d40 0x08000040 ;# omap3_cm
mww 0x48004d40 0x09900040 ;# omap3_cm
mww 0x48004d40 0x09900c40 ;# omap3_cm
mww 0x48004d40 0x09900c00 ;# omap3_cm
mww 0x48004a40 0x00001305 ;# omap3_cm
mww 0x48004a40 0x00001125 ;# omap3_cm
mww 0x48004a40 0x00001109 ;# omap3_cm
mww 0x48004a40 0x0000110a ;# omap3_cm
mww 0x48004b40 0x00000005 ;# omap3_cm
mww 0x48004c40 0x00000015 ;# omap3_cm
mww 0x48004d00 0x00110006 ;# omap3_cm
mww 0x48004d00 0x00110007 ;# omap3_cm
mww 0x48004d00 0x00110007 ;# omap3_cm
mww 0x48005140 0x03020a50 ;# omap3_cm
mww 0x48004f40 0x00000004 ;# omap3_cm
mww 0x48004e40 0x00000409 ;# omap3_cm
mww 0x48004e40 0x00001009 ;# omap3_cm
mww 0x48004d48 0x00000009 ;# omap3_cm
mww 0x48004d44 0x02436000 ;# omap3_cm
mww 0x48004d44 0x0243600c ;# omap3_cm
mww 0x48004a40 0x0000110a ;# omap3_cm
mww 0x48004d00 0x00170007 ;# omap3_cm
mww 0x48004d04 0x00000011 ;# omap3_cm
mww 0x48004d50 0x00000001 ;# omap3_cm
mww 0x48004d4c 0x00007800 ;# omap3_cm
mww 0x48004d4c 0x0000780c ;# omap3_cm
mww 0x48004d00 0x00170037 ;# omap3_cm
mww 0x48004d04 0x00000017 ;# omap3_cm
mww 0x48004004 0x00000011 ;# omap3_cm
mww 0x48004044 0x00000001 ;# omap3_cm
mww 0x48004040 0x00081400 ;# omap3_cm
mww 0x48004040 0x00081400 ;# omap3_cm
mww 0x48004004 0x00000017 ;# omap3_cm
mww 0x48004944 0x00000001 ;# omap3_cm
mww 0x48004940 0x000a5800 ;# omap3_cm
mww 0x48004940 0x000a580c ;# omap3_cm
mww 0x48004904 0x00000017 ;# omap3_cm
mww 0x48005040 0x000000ff ;# omap3_cm
mww 0x48004c40 0x00000015 ;# omap3_cm
mww 0x48005040 0x000000ff ;# omap3_cm
mww 0x48005010 0x00000008 ;# omap3_cm
mww 0x48005000 0x00000008 ;# omap3_cm
mww 0x48004a00 0x00002000 ;# omap3_cm
mww 0x48004a10 0x00002042 ;# omap3_cm
mww 0x48005000 0x00000808 ;# omap3_cm
mww 0x48005010 0x00000808 ;# omap3_cm
mww 0x48004a00 0x0003a000 ;# omap3_cm
mww 0x48004a10 0x0003a042 ;# omap3_cm
mww 0x48004c10 0x00000025 ;# omap3_cm
mww 0x48004000 0x00000001 ;# omap3_cm
mww 0x48004a00 0x03fffe29 ;# omap3_cm
mww 0x48004a10 0x3ffffffb ;# omap3_cm
mww 0x48004a14 0x0000001f ;# omap3_cm
mww 0x48004c00 0x000000e9 ;# omap3_cm
mww 0x48004c10 0x0000003f ;# omap3_cm
mww 0x48004e00 0x00000005 ;# omap3_cm
mww 0x48004e10 0x00000001 ;# omap3_cm
mww 0x48004f00 0x00000001 ;# omap3_cm
mww 0x48004f10 0x00000001 ;# omap3_cm
mww 0x48005000 0x0003ffff ;# omap3_cm
mww 0x48005010 0x0003ffff ;# omap3_cm
mww 0x48005410 0x00000001 ;# omap3_cm
mww 0x48005400 0x00000003 ;# omap3_cm
mww 0x48004a18 0x00000004 ;# omap3_cm
mww 0x48004a08 0x00000004 ;# omap3_cm
mww 0x6e000060 0x00001800 ;# omap-gpmc
mww 0x6e000064 0x00141400 ;# omap-gpmc
mww 0x6e000068 0x00141400 ;# omap-gpmc
mww 0x6e00006c 0x0f010f01 ;# omap-gpmc
mww 0x6e000070 0x010c1414 ;# omap-gpmc
mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc
mww 0x6e000078 0x00000870 ;# omap-gpmc
mwb 0x6e00007c 0x000000ff ;# omap-gpmc
mwb 0x6e00007c 0x00000070 ;# omap-gpmc
mwb 0x6e00007c 0x00000090 ;# omap-gpmc
mwb 0x6e000080 0x00000000 ;# omap-gpmc
mww 0x6d000010 0x00000002 ;# omap.sdrc
mww 0x6d000010 0x00000000 ;# omap.sdrc
mww 0x6d000044 0x00000100 ;# omap.sdrc
mww 0x6d000070 0x04000081 ;# omap.sdrc
mww 0x6d000060 0x0000000a ;# omap.sdrc
mww 0x6d000080 0x04590099 ;# omap.sdrc
mww 0x6d00009c 0xc29dc4c6 ;# omap.sdrc
mww 0x6d0000a0 0x00022322 ;# omap.sdrc
mww 0x6d0000a4 0x0004e201 ;# omap.sdrc
mww 0x6d0000a8 0x00000000 ;# omap.sdrc
mww 0x6d0000a8 0x00000001 ;# omap.sdrc
mww 0x6d0000a8 0x00000002 ;# omap.sdrc
mww 0x6d0000a8 0x00000002 ;# omap.sdrc
mww 0x6d000084 0x00000032 ;# omap.sdrc
mww 0x6d000040 0x00000004 ;# omap.sdrc
mww 0x6d0000b0 0x04590099 ;# omap.sdrc
mww 0x6d0000c4 0xc29dc4c6 ;# omap.sdrc
mww 0x6d0000c8 0x00022322 ;# omap.sdrc
mww 0x6d0000d4 0x0004e201 ;# omap.sdrc
mww 0x6d0000d8 0x00000000 ;# omap.sdrc
mww 0x6d0000d8 0x00000001 ;# omap.sdrc
mww 0x6d0000d8 0x00000002 ;# omap.sdrc
mww 0x6d0000d8 0x00000002 ;# omap.sdrc
mww 0x6d0000b4 0x00000032 ;# omap.sdrc
mww 0x6d0000b0 0x00000000 ;# omap.sdrc
mww 0x6e00001c 0x00000000 ;# omap-gpmc
mww 0x6e000040 0x00000000 ;# omap-gpmc
mww 0x6e000050 0x00000000 ;# omap-gpmc
mww 0x6e000078 0x00000000 ;# omap-gpmc
mww 0x6e000078 0x00000000 ;# omap-gpmc
mww 0x6e000060 0x00001800 ;# omap-gpmc
mww 0x6e000064 0x00141400 ;# omap-gpmc
mww 0x6e000068 0x00141400 ;# omap-gpmc
mww 0x6e00006c 0x0f010f01 ;# omap-gpmc
mww 0x6e000070 0x010c1414 ;# omap-gpmc
mww 0x6e000074 0x1f0f0a80 ;# omap-gpmc
mww 0x6e000078 0x00000870 ;# omap-gpmc
mww 0x48004a00 0x437ffe00 ;# omap3_cm
mww 0x48004a10 0x637ffed2 ;# omap3_cm
puts "Beagleboard xM initialised"
}
init

26
bsps/arm/beagle/start/bspstartmmu.c
View File

@@ -1,27 +1,11 @@
/*
* Copyright (C) 2013 embedded brains GmbH & Co. KG
* Copyright (C) 2014 Chris Johns <chrisj@rtems.org>
* Copyright (c) 2013 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Copyright (c) 2014 Chris Johns. All rights reserved.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <bsp.h>

18
bsps/arm/csb336/config/csb336.cfg Normal file
View File

@@ -0,0 +1,18 @@
#
# Config file for Cogent CSB337 - AT91RM9200 SBC
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=arm
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -mcpu=arm920
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
# Add CFLAGS and LDFLAGS for compiling and linking with per item sections
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

34
bsps/arm/csb336/include/bsp/irq.h
View File

@@ -1,31 +1,13 @@
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Interrupt handler Header file
*
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IRQ_H__

34
bsps/arm/csb336/irq/irq.c
View File

@@ -1,31 +1,13 @@
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Motorola MC9328MXL Interrupt handler
*
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/armv4.h>

18
bsps/arm/csb337/config/csb337.cfg Normal file
View File

@@ -0,0 +1,18 @@
#
# Config file for Cogent CSB337 - AT91RM9200 SBC
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=arm
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -mcpu=arm920
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
# Add CFLAGS and LDFLAGS for compiling and linking with per item sections
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

5
bsps/arm/csb337/config/csb637.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for Cogent CSB637 - AT91RM9200 SBC
#
include $(RTEMS_ROOT)/make/custom/csb337.cfg

6
bsps/arm/csb337/config/kit637_v6.cfg Normal file
View File

@@ -0,0 +1,6 @@
#
# Config file for Cogent KIT637_V6 (CSB637) - AT91RM9200 SBC
# As a KIT637, the package includes a number of peripherals
# not normally on a CSB637.
include $(RTEMS_ROOT)/make/custom/csb337.cfg

2
bsps/arm/csb337/include/at91rm9200.h
View File

@@ -141,7 +141,7 @@ typedef volatile unsigned long vulong;
#define USART3_BASE 0xFFFCC000
/*
* WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!!
* Manual revision: Rev. 1768H-ATARM-16-Jun-09
* Manual revision: Rev. 1768H-ATARM–16-Jun-09
* USART3_BASE is NOT 0xFFECC000
*/

28
bsps/arm/csb337/include/bsp/irq.h
View File

@@ -7,29 +7,15 @@
*/
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
* Interrupt handler Header file
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IRQ_H__

34
bsps/arm/csb337/irq/irq.c
View File

@@ -1,31 +1,13 @@
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Atmel AT91RM9200 Interrupt handler
*
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/armv4.h>

8
bsps/arm/csb337/umon/tfsDriver.c
View File

@@ -135,7 +135,7 @@ int rtems_initialize_tfs_filesystem(
return -1;
}
strncpy( TFS_PATHNAME_PREFIX, path, sizeof(TFS_PATHNAME_PREFIX)-1 );
strncpy( TFS_PATHNAME_PREFIX, path, sizeof(TFS_PATHNAME_PREFIX) );
status = mkdir( TFS_PATHNAME_PREFIX, S_IRWXU | S_IRWXG | S_IRWXO );
if ( status == -1 ) {
@@ -606,9 +606,9 @@ static int rtems_tfs_ftruncate(
}
static int rtems_tfs_ioctl(
rtems_libio_t *iop,
ioctl_command_t cmd,
void *buf
rtems_libio_t *iop,
uint32_t cmd,
void *buf
)
{
int ret;

19
bsps/arm/edb7312/config/edb7312.cfg Normal file
View File

@@ -0,0 +1,19 @@
#
# Config file for Cirrus/Cogent EDB7312 eval board
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=arm
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
#
CPU_CFLAGS = -mcpu=arm7tdmi
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
# Add CFLAGS and LDFLAGS for compiling and linking with per item sections
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

18
bsps/arm/gumstix/config/gumstix.cfg Normal file
View File

@@ -0,0 +1,18 @@
#
# Config file for Gumstix (http://www.gumstix.com)
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU=arm
# This contains the compiler options necessary to select the CPU model
# and (hopefully) optimize for it.
CPU_CFLAGS = -mcpu=xscale
# optimize flag: typically -O2
CFLAGS_OPTIMIZE_V = -O2 -g
# Add CFLAGS and LDFLAGS for compiling and linking with per item sections
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections

27
bsps/arm/gumstix/include/bsp/irq.h
View File

@@ -1,27 +1,12 @@
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __IRQ_H__

31
bsps/arm/gumstix/irq/irq.c
View File

@@ -1,31 +1,12 @@
/*
* Copyright (C) 2010 embedded brains GmbH & Co. KG
* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
* Copyright (c) 2010 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#include <rtems/score/armv4.h>

16
bsps/arm/imx/config/imx7.cfg Normal file
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@@ -0,0 +1,16 @@
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a7
LDFLAGS = -Wl,--gc-sections
CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections
# define bsp-post-link
# $(OBJCOPY) -O binary '$@' '$(basename $@).bin'
# gzip -f -9 '$(basename $@).bin'
# mkimage -A arm -O linux -T kernel -a 0x80200000 -e 0x80200000 -name '$(notdir $@)' -d '$(basename $@).bin.gz' '$(basename $@).img'
# $(default-bsp-post-link)
# endef

2
bsps/arm/imxrt/mcux-sdk/drivers/dac12/fsl_dac12.h
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@@ -112,7 +112,7 @@ typedef enum _dac12_fifo_trigger_mode
* @brief DAC internal reference current source.
*
* Analog module needs reference current to keep working . Such reference current can generated by IP itself, or by
* on-chip PMC's "reference part". If no current reference be selected, analog module can't working normally ,even when
* on-chip PMC's "reference part". If no current reference be selected, analog module can’t working normally ,even when
* other register can still be assigned, DAC would waste current but no function.
* To make the DAC work, either kDAC12_ReferenceCurrentSourceAltx should be selected.
*/

2
bsps/arm/imxrt/mcux-sdk/drivers/semc/fsl_semc.h
View File

@@ -313,7 +313,7 @@ typedef enum _semc_ipcmd_nand_addrmode
kSEMC_NANDAM_RawRA0RA1RA2 /*!< Address mode: row address only(3 Byte-RA0). */
} semc_ipcmd_nand_addrmode_t;
/*! @brief SEMC IP command for NAND: command mode. */
/*! @brief SEMC IP command for NAND： command mode. */
typedef enum _semc_ipcmd_nand_cmdmode
{
kSEMC_NANDCM_Command = 0x2U, /*!< command. */

26
bsps/arm/include/bsp/arm-cp15-start.h
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@@ -6,30 +6,14 @@
* @brief Arm CP15 start.
*/
/*
* Copyright (C) 2013 Hesham AL-Matary
* Copyright (c) 2013 Hesham AL-Matary.
* Copyright (C) 2009, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H

3312
bsps/arm/include/core_cm33.h
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File diff suppressed because it is too large Load Diff

431
bsps/arm/include/mpu_armv8.h
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@@ -1,431 +0,0 @@
/*
* The file was modified by RTEMS contributors.
*/
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.9.0
* @date 11. April 2023
******************************************************************************/
/*
* Copyright (c) 2017-2022 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for Normal memory, Outer and Inner cacheability.
* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Normal memory outer-cacheable and inner-cacheable attributes
* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
*/
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/* \brief Specifies MAIR_ATTR number */
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
/**
* Shareability
*/
/** \brief Normal memory, non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory, outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory, inner shareable */
#define ARM_MPU_SH_INNER (3U)
/**
* Access permissions
* AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
*/
/** \brief Normal memory, read/write */
#define ARM_MPU_AP_RW (0U)
/** \brief Normal memory, read-only */
#define ARM_MPU_AP_RO (1U)
/** \brief Normal memory, any privilege level */
#define ARM_MPU_AP_NP (1U)
/** \brief Normal memory, privileged access only */
#define ARM_MPU_AP_PO (0U)
/*
* Execute-never
* XN = Execute-never, EX = Executable
*/
/** \brief Normal memory, Execution only permitted if read permitted */
#define ARM_MPU_XN (1U)
/** \brief Normal memory, Execution only permitted if read permitted */
#define ARM_MPU_EX (0U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/**
\brief Read MPU Type Register
\return Number of MPU regions
*/
#ifndef __rtems__
__STATIC_INLINE uint32_t ARM_MPU_TYPE()
#else /* __rtems__ */
__STATIC_INLINE uint32_t ARM_MPU_TYPE(void)
#endif /* __rtems__ */
{
return ((MPU->TYPE) >> 8);
}
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
const uint32_t val = (uint32_t)attr << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | (val & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

48
bsps/arm/lm3s69xx/config/lm3s3749-testsuite.tcfg Normal file
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@@ -0,0 +1,48 @@
#
# lm3s3749 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/disable-mrfs-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: capture
exclude: cdtest
exclude: iostream
exclude: dl01
exclude: dl02
exclude: dl04
exclude: dl05
exclude: dl06
exclude: dl07
exclude: dl08
exclude: dl09
exclude: ftp01
exclude: fileio
exclude: flashdisk01
exclude: fsdosfsname01
exclude: fsdosfsformat01
exclude: fsrfsbitmap01
exclude: linpack
exclude: loopback
exclude: mghttpd01
exclude: mdosfs_fserror
exclude: mdosfs_fsrdwr
exclude: monitor02
exclude: paranoia
exclude: pppd
exclude: psxconfig01
exclude: record01
exclude: rtems++
exclude: shell01
exclude: sp47
exclude: spcxx01
exclude: spstkalloc02
exclude: sptls02
exclude: syscall01
exclude: telnetd01
exclude: ttest01
exclude: utf8proc01

5
bsps/arm/lm3s69xx/config/lm3s3749.cfg Normal file
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@@ -0,0 +1,5 @@
#
# Config file for LM3S3749.
#
include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc

22
bsps/arm/lm3s69xx/config/lm3s6965-testsuite.tcfg Normal file
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@@ -0,0 +1,22 @@
#
# lm3s6965 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: fileio
exclude: iostream
exclude: flashdisk01
exclude: fsdosfsname01
exclude: ftp01
exclude: linpack
exclude: mghttpd01
exclude: monitor02
exclude: utf8proc01
exclude: pppd
exclude: rtems++
exclude: spstkalloc02

5
bsps/arm/lm3s69xx/config/lm3s6965.cfg Normal file
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@@ -0,0 +1,5 @@
#
# Config file for LM3S6965.
#
include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc

5
bsps/arm/lm3s69xx/config/lm3s6965_qemu.cfg Normal file
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@@ -0,0 +1,5 @@
#
# Config file for QEMU LM3S6965 emulation.
#
include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc

39
bsps/arm/lm3s69xx/config/lm4f120-testsuite.tcfg Normal file
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@@ -0,0 +1,39 @@
#
# lm4f120 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: block08
exclude: capture
exclude: iostream
exclude: fileio
exclude: flashdisk01
exclude: fsdosfsname01
exclude: ftp01
exclude: linpack
exclude: loopback
exclude: mghttpd01
exclude: ostream
exclude: pppd
exclude: psxaio01
exclude: psxaio02
exclude: psxaio03
exclude: psxconfig01
exclude: psxsignal07
exclude: sp16
exclude: sp25
exclude: sp42
exclude: sp47
exclude: sp48
exclude: sp71
exclude: spstkalloc02
exclude: sptimecounter02
exclude: sptimecounter03
exclude: tmcontext01
exclude: top
exclude: utf8proc01

5
bsps/arm/lm3s69xx/config/lm4f120.cfg Normal file
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@@ -0,0 +1,5 @@
#
# Config file for LM4F120XL.
#
include $(RTEMS_ROOT)/make/custom/lm3s69xx.inc

40
bsps/arm/lpc176x/config/lpc1768_mbed-testsuite.tcfg Normal file
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@@ -0,0 +1,40 @@
#
# lpc1768 mbed RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: dl07
exclude: flashdisk01
exclude: ftp01
exclude: utf8proc01
exclude: spstkalloc02
exclude: fsdosfsname01
exclude: linpack
exclude: pppd
exclude: mghttpd01
exclude: tmfine01
exclude: iostream
exclude: rtems++
# When debug
exclude: block08
exclude: capture
exclude: fileio
exclude: loopback
exclude: psxaio01
exclude: psxaio02
exclude: psxaio03
exclude: psxsignal07
exclude: sp16
exclude: sp25
exclude: sp42
exclude: sp48
exclude: sptimecounter02
exclude: sptimecounter03
exclude: tmcontext01
exclude: top

22
bsps/arm/lpc176x/config/lpc1768_mbed.cfg Normal file
View File

@@ -0,0 +1,22 @@
#
# Config file for mbed LPC1768 board.
#
include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = arm
CPU_CFLAGS = -mthumb -mcpu=cortex-m3
CFLAGS_OPTIMIZE_V = -O2 -ggdb3
CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
LDFLAGS = -Wl,--gc-sections
BINEXT?=.bin
# This defines the operations performed on the linked executable.
# is currently required.
define bsp-post-link
$(OBJCOPY) -O binary --strip-all \
$(basename $@)$(EXEEXT) $(basename $@)$(BINEXT)
$(SIZE) $(basename $@)$(EXEEXT)
endef

37
bsps/arm/lpc176x/config/lpc1768_mbed_ahb_ram-testsuite.tcfg Normal file
View File

@@ -0,0 +1,37 @@
#
# lpc1768_mbed_ahb_ram RTEMS Test Database
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: block08
exclude: capture
exclude: dl07
exclude: fileio
exclude: flashdisk01
exclude: fsdosfsname01
exclude: ftp01
exclude: linpack
exclude: loopback
exclude: mghttpd01
exclude: pppd
exclude: psxaio01
exclude: psxaio02
exclude: sp16
exclude: sp25
exclude: sp42
exclude: sp48
exclude: spstkalloc02
exclude: sptimecounter02
exclude: sptimecounter03
exclude: sptls02
exclude: tmcontext01
exclude: tmfine01
exclude: top
exclude: utf8proc01
exclude: iostream
exclude: rtems++

5
bsps/arm/lpc176x/config/lpc1768_mbed_ahb_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for mbed LPC1768 board.
#
include $(RTEMS_ROOT)/make/custom/lpc1768_mbed.cfg

140
bsps/arm/lpc176x/config/lpc1768_mbed_ahb_ram_eth-testsuite.tcfg Normal file
View File

@@ -0,0 +1,140 @@
#
# lpc1768_mbed_ahb_ram_eth RTEMS Test Database
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/disable-mrfs-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: block08
exclude: calloc
exclude: capture
exclude: cdtest
exclude: clock_gettime
exclude: close
exclude: debugger01
exclude: defaultconfig01
exclude: dhrystone
exclude: dl07
exclude: dup2
exclude: fcntl
exclude: fileio
exclude: flashdisk01
exclude: flockfile
exclude: fork
exclude: free
exclude: fsdosfsname01
exclude: fsdosfswrite01
exclude: fsrfsbitmap01
exclude: fstat
exclude: ftp01
exclude: ftrylockfile
exclude: funlockfile
exclude: getlogin
exclude: getpwnam
exclude: getpwuid
exclude: gettimeofday
exclude: getuid
exclude: heapwalk
exclude: htonl
exclude: imfs_fserror
exclude: imfs_fslink
exclude: imfs_fspatheval
exclude: imfs_fspermission
exclude: imfs_fsrdwr
exclude: imfs_fsscandir01
exclude: imfs_fssymlink
exclude: imfs_fstime
exclude: iostream
exclude: kill
exclude: linpack
exclude: longjmp
exclude: loopback
exclude: lseek
exclude: lstat
exclude: malloc
exclude: mdosfs_fserror
exclude: mdosfs_fspatheval
exclude: mdosfs_fsrdwr
exclude: mdosfs_fsscandir01
exclude: mdosfs_fsstatvfs
exclude: mdosfs_fstime
exclude: mghttpd01
exclude: mimfs_fserror
exclude: mimfs_fslink
exclude: mimfs_fspatheval
exclude: mimfs_fspermission
exclude: mimfs_fsrdwr
exclude: mimfs_fsrename
exclude: mimfs_fsscandir01
exclude: mimfs_fssymlink
exclude: mimfs_fstime
exclude: monitor
exclude: monitor01
exclude: monitor02
exclude: nanosleep
exclude: open
exclude: pipe
exclude: posix_memalign
exclude: pppd
exclude: psxaio01
exclude: psxaio02
exclude: psxaio03
exclude: psxbarrier01
exclude: psxconfig01
exclude: psxkey07
exclude: psxkey08
exclude: psxsignal02
exclude: psxsignal07
exclude: rbheap01
exclude: read
exclude: readv
exclude: realloc
exclude: rtems++
exclude: setjmp
exclude: sigaddset
exclude: sigdelset
exclude: sigemptyset
exclude: sigfillset
exclude: sigismember
exclude: sigprocmask
exclude: sp16
exclude: sp20
exclude: sp25
exclude: sp35
exclude: sp42
exclude: sp48
exclude: spclock_err01
exclude: spevent_err03
exclude: spintr_err01
exclude: spmsgq_err01
exclude: spmsgq_err02
exclude: spport_err01
exclude: spratemon_err01
exclude: spregion_err01
exclude: spsem_err01
exclude: spsem_err02
exclude: spsignal_err01
exclude: spstkalloc
exclude: spstkalloc02
exclude: sptask_err01
exclude: sptask_err03
exclude: sptimecounter02
exclude: sptimecounter03
exclude: sptls02
exclude: stat
exclude: telnetd01
exclude: tm21
exclude: tmcontext01
exclude: tmfine01
exclude: top
exclude: unlink
exclude: utf8proc01
exclude: vfork
exclude: wait
exclude: waitpid
exclude: write
exclude: writev

5
bsps/arm/lpc176x/config/lpc1768_mbed_ahb_ram_eth.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for mbed LPC1768 board.
#
include $(RTEMS_ROOT)/make/custom/lpc1768_mbed.cfg

5
bsps/arm/lpc24xx/config/lpc17xx_ea_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC1788 OEM Board from Embedded Artists.
#
include $(RTEMS_ROOT)/make/custom/lpc17xx.inc

8
bsps/arm/lpc24xx/config/lpc17xx_ea_rom_int-testsuite.tcfg Normal file
View File

@@ -0,0 +1,8 @@
#
# lpc17xx_ea_rom_int RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fsdosfsname01

5
bsps/arm/lpc24xx/config/lpc17xx_ea_rom_int.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC1788 OEM Board from Embedded Artists.
#
include $(RTEMS_ROOT)/make/custom/lpc17xx.inc

5
bsps/arm/lpc24xx/config/lpc17xx_plx800_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC17XX (PLX800).
#
include $(RTEMS_ROOT)/make/custom/lpc17xx.inc

8
bsps/arm/lpc24xx/config/lpc17xx_plx800_rom_int-testsuite.tcfg Normal file
View File

@@ -0,0 +1,8 @@
#
# lpc17xx_plx800_rom_int RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fsdosfsname01

5
bsps/arm/lpc24xx/config/lpc17xx_plx800_rom_int.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC17XX (PLX800).
#
include $(RTEMS_ROOT)/make/custom/lpc17xx.inc

64
bsps/arm/lpc24xx/config/lpc2362-testsuite.tcfg Normal file
View File

@@ -0,0 +1,64 @@
#
# lpc2362 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/disable-mrfs-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: block08
exclude: capture
exclude: cdtest
exclude: dl01
exclude: dl02
exclude: dl04
exclude: dl05
exclude: dl06
exclude: dl07
exclude: fileio
exclude: flashdisk01
exclude: fsrofs01
exclude: fsdosfsname01
exclude: fsdosfsformat01
exclude: fsrfsbitmap01
exclude: ftp01
exclude: iostream
exclude: linpack
exclude: loopback
exclude: math
exclude: mdosfs_fserror
exclude: mghttpd01
exclude: monitor
exclude: monitor02
exclude: mdosfs_fsrdwr
exclude: paranoia
exclude: pppd
exclude: psxaio01
exclude: psxaio02
exclude: psxaio03
exclude: psxmsgq01
exclude: psxsignal07
exclude: record01
exclude: rtems++
exclude: shell01
exclude: spstkalloc02
exclude: sp16
exclude: sp25
exclude: sp42
exclude: sp48
exclude: spcxx01
exclude: sptimecounter02
exclude: sptimecounter03
exclude: sptls02
exclude: syscall01
exclude: telnetd01
exclude: tmcontext01
exclude: tmfine01
exclude: top
exclude: ttest01
exclude: utf8proc01

5
bsps/arm/lpc24xx/config/lpc2362.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC2362.
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

72
bsps/arm/lpc24xx/config/lpc23xx_tli800-testsuite.tcfg Normal file
View File

@@ -0,0 +1,72 @@
#
# lpc23xx_tli800 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/disable-mrfs-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: block08
exclude: capture
exclude: cdtest
exclude: complex
exclude: crypt01
exclude: dl01
exclude: dl02
exclude: dl04
exclude: dl05
exclude: dl06
exclude: dl07
exclude: fileio
exclude: flashdisk01
exclude: fsdosfsformat01
exclude: fsdosfsname01
exclude: fsdosfswrite01
exclude: fsrfsbitmap01
exclude: fsrofs01
exclude: ftp01
exclude: iostream
exclude: linpack
exclude: loopback
exclude: math
exclude: mathf
exclude: mdosfs_fserror
exclude: mdosfs_fsscandir01
exclude: mghttpd01
exclude: monitor
exclude: monitor02
exclude: mdosfs_fsrdwr
exclude: mdosfs_fspatheval
exclude: mdosfs_fstime
exclude: paranoia
exclude: pppd
exclude: psxaio01
exclude: psxaio02
exclude: psxaio03
exclude: psxmsgq01
exclude: psxsignal07
exclude: record01
exclude: rtems++
exclude: shell01
exclude: sp16
exclude: sp25
exclude: sp42
exclude: sp48
exclude: spcxx01
exclude: sptimecounter02
exclude: sptimecounter03
exclude: sptls02
exclude: spstkalloc02
exclude: syscall01
exclude: tar01
exclude: telnetd01
exclude: termios
exclude: tmcontext01
exclude: tmfine01
exclude: top
exclude: ttest01
exclude: utf8proc01

5
bsps/arm/lpc24xx/config/lpc23xx_tli800.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for TLI800.
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

12
bsps/arm/lpc24xx/config/lpc24xx_ea.cfg Normal file
View File

@@ -0,0 +1,12 @@
#
# Config file for LPC24XX (QVGA Base Board from Embedded Artists).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc
# define bsp-post-link
# $(OBJCOPY) -O binary '$@' '$(basename $@).bin'
# gzip -f -9 '$(basename $@).bin'
# mkimage -A arm -O rtems -T kernel -C gzip -a a0000000 -e a0000040 -name '$(notdir $@)' -d '$(basename $@).bin.gz' '$(basename $@).img'
# $(default-bsp-post-link)
# endef

5
bsps/arm/lpc24xx/config/lpc24xx_ncs_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC24XX (NCS).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

5
bsps/arm/lpc24xx/config/lpc24xx_ncs_rom_ext.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC24XX (NCS).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

9
bsps/arm/lpc24xx/config/lpc24xx_ncs_rom_int-testsuite.tcfg Normal file
View File

@@ -0,0 +1,9 @@
#
# lpc24xx_ncs_rom_int RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fsdosfsname01
exclude: record02

5
bsps/arm/lpc24xx/config/lpc24xx_ncs_rom_int.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC24XX (NCS).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

5
bsps/arm/lpc24xx/config/lpc24xx_plx800_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC24XX (PLX800).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

9
bsps/arm/lpc24xx/config/lpc24xx_plx800_rom_int-testsuite.tcfg Normal file
View File

@@ -0,0 +1,9 @@
#
# lpc24xx_plx800_rom_int RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fsdosfsname01
exclude: record02

5
bsps/arm/lpc24xx/config/lpc24xx_plx800_rom_int.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC24XX (PLX800).
#
include $(RTEMS_ROOT)/make/custom/lpc24xx.inc

5
bsps/arm/lpc24xx/config/lpc40xx_ea_ram.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC40XX OEM Board from Embedded Artists.
#
include $(RTEMS_ROOT)/make/custom/lpc40xx.inc

8
bsps/arm/lpc24xx/config/lpc40xx_ea_rom_int-testsuite.tcfg Normal file
View File

@@ -0,0 +1,8 @@
#
# lpc40xx_ea_rom_int RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
exclude: fsdosfsname01

5
bsps/arm/lpc24xx/config/lpc40xx_ea_rom_int.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for LPC40XX OEM Board from Embedded Artists.
#
include $(RTEMS_ROOT)/make/custom/lpc40xx.inc

3
bsps/arm/lpc24xx/console/console-config.c
View File

@@ -43,8 +43,6 @@
#include <bsp/io.h>
#include <bsp/console-termios.h>
#if defined(LPC24XX_CONFIG_CONSOLE) || defined(LPC24XX_CONFIG_UART_1) || \
defined(LPC24XX_CONFIG_UART_2) || defined(LPC24XX_CONFIG_UART_3)
static uint8_t lpc24xx_uart_get_register(uintptr_t addr, uint8_t i)
{
volatile uint32_t *reg = (volatile uint32_t *) addr;
@@ -58,7 +56,6 @@ static void lpc24xx_uart_set_register(uintptr_t addr, uint8_t i, uint8_t val)
reg [i] = val;
}
#endif
#ifdef LPC24XX_CONFIG_CONSOLE
static ns16550_context lpc24xx_uart_context_0 = {

5
bsps/arm/lpc32xx/config/lpc32xx_mzx.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for MZX application.
#
include $(RTEMS_ROOT)/make/custom/lpc32xx.inc

24
bsps/arm/lpc32xx/config/lpc32xx_mzx_stage_1-testsuite.tcfg Normal file
View File

@@ -0,0 +1,24 @@
#
# lpc32xx_mzx_stage_1 RTEMS Test Database.
#
# Format is one line per test that is _NOT_ built.
#
include: testdata/disable-iconv-tests.tcfg
include: testdata/disable-jffs2-tests.tcfg
include: testdata/small-memory-testsuite.tcfg
exclude: dl05
exclude: dl08
exclude: fileio
exclude: ftp01
exclude: fsdosfsname01
exclude: iostream
exclude: linpack
exclude: mghttpd01
exclude: monitor02
exclude: pppd
exclude: rtems++
exclude: sp71
exclude: ttest01
exclude: utf8proc01

7
bsps/arm/lpc32xx/config/lpc32xx_mzx_stage_1.cfg Normal file
View File

@@ -0,0 +1,7 @@
#
# Config file for MZX stage-1 program.
#
CFLAGS_OPTIMIZE_V = -Os -g
include $(RTEMS_ROOT)/make/custom/lpc32xx.inc

5
bsps/arm/lpc32xx/config/lpc32xx_mzx_stage_2.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for MZX stage-2 program.
#
include $(RTEMS_ROOT)/make/custom/lpc32xx.inc

5
bsps/arm/lpc32xx/config/lpc32xx_phycore.cfg Normal file
View File

@@ -0,0 +1,5 @@
#
# Config file for Phycore LPC3250 board.
#
include $(RTEMS_ROOT)/make/custom/lpc32xx.inc

4
bsps/arm/lpc32xx/include/bsp.h
View File

@@ -187,9 +187,9 @@ extern uint32_t lpc32xx_magic_zero_end [];
*/
extern uint32_t lpc32xx_magic_zero_size [];
#if LPC32XX_SCRATCH_AREA_SIZE
#ifdef LPC32XX_SCRATCH_AREA_SIZE
/**
* @brief Scratch area.
* @rief Scratch area.
*
* The usage is application specific.
*/

17
bsps/arm/lpc32xx/include/bsp/lpc32xx.h
View File

@@ -238,51 +238,39 @@
#define LPC32XX_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
typedef struct {
uint32_t unused;
} lpc32xx_nand_slc;
typedef struct {
uint32_t unused;
} lpc32xx_ssp;
typedef struct {
uint32_t unused;
} lpc32xx_spi;
typedef struct {
uint32_t unused;
} lpc32xx_sd_card;
typedef struct {
uint32_t unused;
} lpc32xx_usb;
typedef struct {
uint32_t unused;
} lpc32xx_lcd;
typedef struct {
uint32_t unused;
} lpc32xx_etb;
typedef struct {
uint32_t unused;
} lpc32xx_syscon;
typedef struct {
uint32_t unused;
} lpc32xx_uart_ctrl;
typedef struct {
uint32_t unused;
} lpc32xx_uart;
typedef struct {
uint32_t unused;
} lpc32xx_ms_timer;
typedef struct {
uint32_t unused;
} lpc32xx_hs_timer;
/**
@@ -357,23 +345,18 @@ typedef struct {
} lpc32xx_wdt;
typedef struct {
uint32_t unused;
} lpc32xx_debug;
typedef struct {
uint32_t unused;
} lpc32xx_adc;
typedef struct {
uint32_t unused;
} lpc32xx_keyscan;
typedef struct {
uint32_t unused;
} lpc32xx_pwm;
typedef struct {
uint32_t unused;
} lpc32xx_mcpwm;
typedef struct {

6
bsps/arm/lpc32xx/nand/nand-mlc-write-blocks.c
View File

@@ -61,7 +61,7 @@ rtems_status_code lpc32xx_mlc_write_blocks(
uint32_t block_end,
const void *src,
size_t src_size,
uint32_t page_buffer [MLC_LARGE_DATA_WORD_COUNT]
uint32_t *page_data_buffer
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
@@ -92,10 +92,10 @@ rtems_status_code lpc32xx_mlc_write_blocks(
size_t delta = remainder < page_size ? remainder : page_size;
if (remainder > 0) {
memcpy(page_buffer, current, delta);
memcpy(page_data_buffer, current, delta);
sc = lpc32xx_mlc_write_page_with_ecc(
page,
page_buffer,
page_data_buffer,
ones_spare
);
if (sc != RTEMS_SUCCESSFUL) {

2
bsps/arm/lpc32xx/start/bspstarthooks.c
View File

@@ -68,7 +68,7 @@
.begin = (uint32_t) bsp_section_fast_data_begin,
.end = (uint32_t) bsp_section_fast_data_end,
.flags = LPC32XX_MMU_READ_WRITE_DATA
#if LPC32XX_SCRATCH_AREA_SIZE
#ifdef LPC32XX_SCRATCH_AREA_SIZE
}, {
.begin = (uint32_t) &lpc32xx_scratch_area [0],
.end = (uint32_t) &lpc32xx_scratch_area [LPC32XX_SCRATCH_AREA_SIZE],

7
bsps/arm/raspberrypi/config/raspberrypi.cfg Normal file
View File

@@ -0,0 +1,7 @@
#
# Config file for RASPBERRYPI
#
include $(RTEMS_ROOT)/make/custom/raspberrypi.inc
CPU_CFLAGS = -mcpu=arm1176jzf-s

6
bsps/arm/raspberrypi/config/raspberrypi2.cfg Normal file
View File

@@ -0,0 +1,6 @@
#
# Config file for RASPBERRYPI 2
#
include $(RTEMS_ROOT)/make/custom/raspberrypi.inc
CPU_CFLAGS = -march=armv7-a -mthumb -mfpu=neon -mfloat-abi=hard -mtune=cortex-a7

2
bsps/arm/raspberrypi/console/outch.c
View File

@@ -10,7 +10,7 @@
*
* Copyright (c) 2015 Yang Qiao
* based on work by:
* Copyright (C) 1998 Eric Valette (eric.valette@free.fr)
* Copyright (C) 1998 Eric Valette (valette@crf.canon.fr)
* Canon Centre Recherche France.
*
* The license and distribution terms for this file may be

28
bsps/arm/raspberrypi/include/bsp/mmu.h
View File

@@ -7,29 +7,15 @@
*/
/*
* Copyright (C) 2013 Alan Cudmore
* Copyright (C) 2009 embedded brains GmbH & Co. KG
* Copyright (c) 2013 Alan Cudmore.
* based on work by:
* Copyright (c) 2009 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.org/license/LICENSE
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef LIBBSP_ARM_RASPBERRYPI_MMU_H

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