forked from Imagelibrary/rtems
213 lines
8.5 KiB
C
213 lines
8.5 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) 2015, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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/** \addtogroup sdram_module
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* The SDRAMC driver provides the Interface to configure the SDRAM Controller
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* (SDRAMC).
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* \section Usage
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* <ul>
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* <li> Configure SDRAM using SDRAMC_Configure().</li>
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* </ul>
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* For more accurate information, please look at the SDRAMC section of the
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* Datasheet.
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* Related files :\n
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* \ref sdramc.c\n
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* \ref sdramc.h.\n
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*/
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/**
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* \file
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*
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* \section Purpose
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*
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* Interface for configuring and using SDRAM Controller (SDRAMC).
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*
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*/
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/**
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* \file
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*
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* Implementation of memories configuration on board.
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*
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*/
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/*----------------------------------------------------------------------------
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* Headers
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*----------------------------------------------------------------------------*/
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#include "chip.h"
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#include "sdramc.h"
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/*----------------------------------------------------------------------------
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* Local functions
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*----------------------------------------------------------------------------*/
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/**
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* \brief Calculate the sdram controller config register value.
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* \param pMemory Pointer to the sdram structure.
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* \return Configure register value.
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*/
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static uint32_t SDRAMC_compute_CR_value(SSdramc_Memory *pMemory)
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{
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uint32_t dw = 0;
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dw |= pMemory->cfg.dwColumnBits;
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dw |= pMemory->cfg.dwRowBits;
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dw |= pMemory->cfg.dwBanks; //NB, number of banks
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dw |= pMemory->cfg.dwCAS; //CAS, CAS latency
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dw |= pMemory->cfg.dwDataBusWidth; //DBW, data bus width
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dw |= SDRAMC_CR_TWR(pMemory->cfg.dwWriteRecoveryDelay);
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//TWR, Write Recovery Delay
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dw |= SDRAMC_CR_TRC_TRFC(pMemory->cfg.dwRowCycleDelay_RowRefreshCycle);
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//TRC_TRFC,Row Cycle Delay and Row Refresh Cycle
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dw |= SDRAMC_CR_TRP(pMemory->cfg.dwRowPrechargeDelay);
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//TRP, Row Precharge Delay
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dw |= SDRAMC_CR_TRCD(pMemory->cfg.dwRowColumnDelay);
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//TRCD, Row to Column Delay
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dw |= SDRAMC_CR_TRAS(pMemory->cfg.dwActivePrechargeDelay);
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//TRAS, Active to Precharge Delay
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dw |= SDRAMC_CR_TXSR(pMemory->cfg.dwExitSelfRefreshActiveDelay);
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//TXSR, Exit Self Refresh to Active Delay
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return dw;
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}
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/*----------------------------------------------------------------------------
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* Exported functions
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*----------------------------------------------------------------------------*/
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/**
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* \brief Configure and initialize the SDRAM controller.
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* \param pMemory Pointer to the sdram structure.
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* \param dwClockFrequency SDRAM clock frequency.
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*/
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extern void SDRAMC_Configure(SSdramc_Memory *pMemory,
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uint32_t dwClockFrequency)
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{
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volatile uint32_t dw;
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/* SDRAM hardware init */
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/* Enable peripheral clock */
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PMC_EnablePeripheral(ID_SMC);
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/* SDRAM device configure */
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/* Step 1. */
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/* Program the features of SDRAM device into the Configuration Register.*/
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SDRAMC->SDRAMC_CR = SDRAMC_compute_CR_value(pMemory);
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/* Step 2. */
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/* For low-power SDRAM, temperature-compensated self refresh (TCSR),
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drive strength (DS) and partial array self refresh (PASR) must be set
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in the Low-power Register.*/
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SDRAMC->SDRAMC_LPR = 0;
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/* Step 3. */
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/* Program the memory device type into the Memory Device Register */
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SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
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/* Step 4 */
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/* A minimum pause of 200 <20><>s is provided to precede any signal toggle.
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(6 core cycles per iteration) */
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for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);
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/* Step 5. */
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/* A NOP command is issued to the SDR-SDRAM. Program NOP command into
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Mode Register, the application must set Mode to 1 in the Mode Register.
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Perform a write access to any SDR-SDRAM address to acknowledge this command.
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Now the clock which drives SDR-SDRAM device is enabled.*/
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
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*(uint16_t *)(EBI_SDRAMC_ADDR) = 0;
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/* Step 6. */
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/* An all banks precharge command is issued to the SDR-SDRAM. Program all
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banks precharge command into Mode Register, the application must set Mode to
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2 in the Mode Register . Perform a write access to any SDRSDRAM address to
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acknowledge this command. */
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
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*(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0;
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/* add some delays after precharge */
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for (dw = 0; dw < ((dwClockFrequency / 1000000) * 200 / 6); dw++);
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/* Step 7. */
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/* Eight auto-refresh (CBR) cycles are provided. Program the auto refresh
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command (CBR) into Mode Register, the application must set Mode to 4 in
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the Mode Register. Once in the idle state, eight AUTO REFRESH cycles must
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be performed. */
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x1;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x2;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x3;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x4;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x5;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x6;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x7;
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x8;
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/* Step 8. */
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/* A Mode Register set (MRS) cycle is issued to program the parameters of
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the SDRAM devices, in particular CAS latency and burst length. */
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
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*(uint16_t *)(EBI_SDRAMC_ADDR + 0x22) = 0xcafe;
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/* Step 9. */
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/* For low-power SDR-SDRAM initialization, an Extended Mode Register set
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(EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS).
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The write address must be chosen so that BA[1] is set to 1 and BA[0] is set
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to 0 */
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
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*((uint16_t *)(EBI_SDRAMC_ADDR + (1 << pMemory->cfg.dwBK1))) = 0;
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/* Step 10. */
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/* The application must go into Normal Mode, setting Mode to 0 in the Mode
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Register and perform a write access at any location in the SDRAM to
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acknowledge this command. */
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SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
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*(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0;
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/* Step 11. */
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/* Write the refresh rate into the count field in the SDRAMC Refresh
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Timer register. Set Refresh timer 15.625 us*/
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dw = dwClockFrequency / 1000u;
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dw *= 15625u;
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dw /= 1000000u;
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SDRAMC->SDRAMC_TR = SDRAMC_TR_COUNT(dw);
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}
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