forked from Imagelibrary/rtems
ab8817ca03
Add directives to get and set the priority of an interrupt vector. Implement the directives for the following BSP families: * arm/lpc24xx * arm/lpc32xx * powerpc/mpc55xxevb * powerpc/qoriq Implement the directives for the following interrupt controllers: * GICv2 and GICv3 (arm and aarch64) * NVIC (arm) * PLIC (riscv) Update #5002.
118 lines
2.7 KiB
C
118 lines
2.7 KiB
C
/*
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* Atmel AT91RM9200 Interrupt handler
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*
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* Copyright (c) 2010 embedded brains GmbH & Co. KG
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*
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* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/score/armv4.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <at91rm9200.h>
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void bsp_interrupt_dispatch(void)
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{
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rtems_vector_number vector = AIC_CTL_REG(AIC_IVR);
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bsp_interrupt_handler_dispatch(vector);
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AIC_CTL_REG(AIC_EOICR) = 0;
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}
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rtems_status_code bsp_interrupt_get_attributes(
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rtems_vector_number vector,
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rtems_interrupt_attributes *attributes
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)
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{
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_is_pending(
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rtems_vector_number vector,
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bool *pending
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(pending != NULL);
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*pending = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_raise(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_clear(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_is_enabled(
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rtems_vector_number vector,
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bool *enabled
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(enabled != NULL);
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*enabled = false;
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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AIC_CTL_REG(AIC_IECR) = 1 << vector;
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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AIC_CTL_REG(AIC_IDCR) = 1 << vector;
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return RTEMS_SUCCESSFUL;
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}
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rtems_status_code bsp_interrupt_set_priority(
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rtems_vector_number vector,
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uint32_t priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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return RTEMS_UNSATISFIED;
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}
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rtems_status_code bsp_interrupt_get_priority(
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rtems_vector_number vector,
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uint32_t *priority
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)
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{
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bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
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bsp_interrupt_assert(priority != NULL);
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return RTEMS_UNSATISFIED;
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}
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void bsp_interrupt_facility_initialize(void)
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{
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unsigned long i = 0;
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for (i = 0; i < 32; ++i) {
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AIC_SVR_REG(i<<2) = i;
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}
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/* disable all interrupts */
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AIC_CTL_REG(AIC_IDCR) = 0xffffffff;
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_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
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}
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