This removes the xilinx and lp64 identifiers from the ZynqMP BSPs and
updates those names throughout the build system. The xilinx identifier
is being removed because it is implied by zynqmp and lp64 is being
removed because it is the default for AArch64.
This also renames grp_zu3eg.yml to grp_hardware.yml to more accurately
reflect its purpose.
Updates #5119
Now that minimum.exe is minimum.norun.exe, the tester will not attempt
to run this sample test and will therefore not categorize it as a
failure since it includes no output. BSP-level test configurations for
this test can now be removed since those configurations only existed to
prevent it from being run.
Make the support for starting in EL2/EL3 customizable. A boot loader or
the Arm Trusted Firmware should start RTEMS in non-secure EL1 mode.
In start.S, use local labels.
For the aarch64/xilinx-zynqmp the support for starting in EL2/EL3 is
disabled by default. For the Qemu xlnx-zcu102 machine, the default is
to start in non-secure EL1 mode. This can be controlled by options, for
example "-machine xlnx-zcu102,secure=on,virtualization=on".
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
- Refactor the pl011 driver to be extensible.
- Add IRQ support and baudrate configuration support for pl011 driver.
- Modify related BSP.
- Add doxygen comments for arm-pl011.
Close#5026
Co-authored-by: Ning Yang <yangn0@qq.com>
The IRQ list in this file are specific to PC hardware and should be
part of the BSP. Further, there are paravirtualized environments which
do not follow the PC hardware IRQ list. Moving this avoids collisions.
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
This reverts commit d81bf04501.
The commit is reverted as this is only partial solution and remaining part
to fix properly is extremely hard and usually done in completely diffetrent
way. Hence let's not enforce compiler but rather enforce RTEMS/H7 users.
This commit adds support for lio_listio().
psxaio05 has been added to test the new method.
To avoid code duplication, the body of aio_read and aio_write has been
moved in two helper methods. In this way i can use it also in lio_listio().
In addition to that, a limit on the number of total aio operation enqueued
has been added.
Updates rtems/programs/gsoc#29
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
