arm/xilinx-zynqmp-rpu: Simplify MPU configuration

Use the PMSAv7 support from <rtems/score/armv7-pmsa.h> instead of the
one from the Xilinx support.

bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c

@@ -35,43 +35,47 @@
  */
 
 #include <bsp/start.h>
+
+#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
+#define ARMV7_PMSA_TEXT_SECTION BSP_START_TEXT_SECTION
+
 #include <bsp/memory.h>
+#include <libcpu/arm-cp15.h>
 
 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
 {
-    /*
-     * On reset, V will be set.  This points the exceptions to the FSBL's vectors.  The FSBL
-     * should clear this bit before booting RTEMS but in some debugging
-     * configurations the bit may not be.  The other bits should already be clear
-     * on reset.  Since the correct settings in these bits are critical,
-     * make sure SCTLR[M, I, A, C, V] are cleared.  Afterwards, exceptions are
-     * handled by RTEMS.
-     * After setting the SCTLR, invalidate the caches.
-     * Note 1: The APU also does these steps in start.S in _start in the #if block:
-     *         `#if (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8`
-     * Note 2: Not all Arm R cores need this (like the TMS570).  So, this probably should
-     *         be in this hook and not in start.S
-     *
-     * Ref: https://developer.arm.com/documentation/ddi0460/c/System-Control/Register-descriptions/c1--System-Control-Register?lang=en
-     */
-
-    __asm__ volatile(
-      "mrc p15, 0, r0, c1, c0, 0 \n"
-      "bic r1, r0, #0x3000 \n"     /* Clear V[13] and I[12] */
-      "bic r1, r1, #0x7 \n"        /* Clear C[2] A[1] and M[0] */
-      "mcr p15, 0, r1, c1, c0, 0 \n"
-
-      /* Invalidate caches */
-      "mov      r0,#0 \n"
-      "dsb \n"
-      "mcr      p15, 0, r0, c7, c5, 0 \n"
-      "mcr      p15, 0, r0, c15, c5, 0 \n"
-      "isb \n"
-        : :);
+  /* Do nothing */
 }
 
 BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
 {
-  zynqmp_setup_mpu_and_cache();
+  uint32_t index = 0;
+
+  for (size_t i = 0; i < zynqmp_mpu_region_count; ++i) {
+    const ARMV7_PMSA_Region *region = &zynqmp_mpu_regions[i];
+    index = _ARMV7_PMSA_Add_regions(
+      index,
+      region->begin,
+      region->size,
+      region->attributes
+    );
+  }
+
+  arm_cp15_instruction_cache_invalidate();
+  arm_cp15_data_cache_all_invalidate();
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+
+  uint32_t control = arm_cp15_get_control();
+  control &= ~ARM_CP15_CTRL_A;
+  control &= ~ARM_CP15_CTRL_V;
+  control |= ARM_CP15_CTRL_M;
+  control |= ARM_CP15_CTRL_C;
+  control |= ARM_CP15_CTRL_I;
+  control |= ARM_CP15_CTRL_Z;
+  arm_cp15_set_control(control);
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+
   bsp_start_clear_bss();
 }

bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c

@@ -1,58 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/**
- * @file
- *
- * @ingroup RTEMSBSPsARMZynqMPRPU
- *
- * @brief This source file contains the implementation of
- * zynqmp_setup_mpu_and_cache().
- */
-
-/*
- * Copyright (C) 2023 Reflex Aerospace GmbH
- *
- * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <bsp/memory.h>
-#include <bsp/start.h>
-
-#include <xil_mpu.h>
-#include <xil_cache.h>
-#include <xreg_cortexr5.h>
-
-BSP_START_TEXT_SECTION void zynqmp_setup_mpu_and_cache(void)
-{
-  for (size_t i = 0; i < zynqmp_mpu_region_count; ++i) {
-    const ARMV7_PMSA_Region *region = &zynqmp_mpu_regions[i];
-    if (region->size > 0) {
-      Xil_SetMPURegion(region->begin, region->size, region->attributes);
-    }
-  }
-
-  Xil_EnableMPU();
-  Xil_DCacheEnable();
-  Xil_ICacheEnable();
-}

bsps/arm/xilinx-zynqmp-rpu/start/mpu-config.c

@@ -39,42 +39,36 @@
 #include <bsp/memory.h>
 #include <bsp/start.h>
 
-#include <xreg_cortexr5.h>
-
 BSP_START_DATA_SECTION const ARMV7_PMSA_Region
 zynqmp_mpu_regions[] = {
   {
     .begin = (uintptr_t)zynqmp_memory_atcm_begin,
     .size = (uintptr_t)zynqmp_memory_atcm_size,
-    .attributes = NORM_NSHARED_NCACHE | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
   }, {
     .begin = (uintptr_t)zynqmp_memory_btcm_begin,
     .size = (uintptr_t)zynqmp_memory_btcm_size,
-    .attributes = NORM_NSHARED_NCACHE | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
   }, {
     .begin = (uintptr_t)zynqmp_memory_ddr_begin,
     .size = (uintptr_t)zynqmp_memory_ddr_size,
-    .attributes = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_READ_WRITE_CACHED
   }, {
     .begin = (uintptr_t)zynqmp_memory_devpl_begin,
     .size = (uintptr_t)zynqmp_memory_devpl_size,
-    .attributes = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_SHAREABLE_DEVICE
   }, {
     .begin = (uintptr_t)zynqmp_memory_devps_begin,
     .size = (uintptr_t)zynqmp_memory_devps_size,
-    .attributes = DEVICE_NONSHARED | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_NON_SHAREABLE_DEVICE
   }, {
     .begin = (uintptr_t)zynqmp_memory_ocm_begin,
     .size = (uintptr_t)zynqmp_memory_ocm_size,
-    .attributes = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW,
-  }, {
-    .begin = (uintptr_t)bsp_section_rodata_begin,
-    .size = (uintptr_t)bsp_section_rodata_size,
-    .attributes = NORM_NSHARED_WB_WA | PRIV_RO_USER_RO,
+    .attributes = ARMV7_PMSA_NON_SHAREABLE_DEVICE
   }, {
     .begin = (uintptr_t)zynqmp_memory_nocache_begin,
     .size = (uintptr_t)zynqmp_memory_nocache_size,
-    .attributes = NORM_SHARED_NCACHE | PRIV_RW_USER_RW,
+    .attributes = ARMV7_PMSA_READ_WRITE_UNCACHED
   }
 };
 

spec/build/bsps/arm/xilinx-zynqmp-rpu/linkcmds.yml

@@ -26,10 +26,6 @@ content: |
   bsp_vector_table_in_start_section = 1;
 
   INCLUDE linkcmds.armv4
-
-  # define symbols needed by the R5 xil_cache.c
-  _stack_end = bsp_section_stack_end;
-  __undef_stack = bsp_section_stack_begin;
 copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 enabled-by: true

spec/build/bsps/arm/xilinx-zynqmp-rpu/obj.yml

@@ -28,7 +28,6 @@ source:
 - bsps/arm/xilinx-zynqmp-rpu/start/bspreset.c
 - bsps/arm/xilinx-zynqmp-rpu/start/bspstart.c
 - bsps/arm/xilinx-zynqmp-rpu/start/bspstarthooks.c
-- bsps/arm/xilinx-zynqmp-rpu/start/bspstartmpu.c
 - bsps/arm/xilinx-zynqmp-rpu/start/mpu-config.c
 - bsps/shared/dev/clock/xil-ttc.c
 - bsps/shared/dev/btimer/btimer-cpucounter.c