bsps/aarch64: Add AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS

This avoids dead code in the MMU setup.

bsps/aarch64/shared/mmu/mmu-setup.c

@@ -229,6 +229,9 @@ BSP_START_TEXT_SECTION static inline rtems_status_code aarch64_mmu_map_block(
 BSP_START_TEXT_SECTION static inline uint64_t
 aarch64_mmu_get_cpu_pa_bits( void )
 {
+#ifdef AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS
+  return AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS;
+#else
   uint64_t id_reg = _AArch64_Read_id_aa64mmfr0_el1();
 
   switch ( AARCH64_ID_AA64MMFR0_EL1_PARANGE_GET( id_reg ) ) {
@@ -250,6 +253,7 @@ aarch64_mmu_get_cpu_pa_bits( void )
 	  return 48;
   }
   return 48;
+#endif
 }
 
 BSP_START_TEXT_SECTION rtems_status_code

spec/build/bsps/aarch64/optmmupabits.yml

@@ -0,0 +1,30 @@
+SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
+actions:
+- get-integer: null
+- assert-in-set:
+  - 32
+  - 36
+  - 40
+  - 42
+  - 44
+  - 48
+  - 52
+  - 48
+- format-and-define: null
+build-type: option
+copyrights:
+- Copyright (C) 2024 embedded brains GmbH & Co. KG
+default:
+- enabled-by: bsps/aarch64/xilinx-zynqmp
+  value: 40
+- enabled-by: true
+  value: null
+description: |
+  If defined, then it specifies the physical address range bits of the EL1 MMU.
+  If not defined, then the value is obtained at runtime by reading the AArch64
+  Memory Model Feature Register 0 (ID_AA64MMFR0_EL1).
+enabled-by: true
+format: '{}'
+links: []
+name: AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS
+type: build

spec/build/bsps/aarch64/xilinx-zynqmp/grp.yml

@@ -14,6 +14,8 @@ links:
   uid: ../grp
 - role: build-dependency
   uid: ../start
+- role: build-dependency
+  uid: ../optmmupabits
 - role: build-dependency
   uid: ../optmmupages
 - role: build-dependency