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riscv: add bsp for beagle v fire

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Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
This commit is contained in:
Francescodario Cuzzocrea
2023-12-19 22:22:25 +01:00
committed by Gedare Bloom
parent 0e3792edbf
commit 9d45cf1b44
15 changed files with 981 additions and 0 deletions
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9
bsps/riscv/riscv/config/bvf.cfg Normal file
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include $(RTEMS_ROOT)/make/custom/default.cfg
RTEMS_CPU = riscv
CPU_CFLAGS = -march=rv64imafdc -mabi=lp64d -mcmodel=medany
LDFLAGS = -Wl,--gc-sections
CFLAGS_OPTIMIZE_V ?= -O2 -g -ffunction-sections -fdata-sections

364
bsps/riscv/riscv/dts/bvf.dts Normal file
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@@ -0,0 +1,364 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (C) Francescodario Cuzzocrea <bosconovic@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "BeagleBoard BeagleV-Fire";
compatible = "beagle,beaglev-fire", "microchip,mpfs";
aliases {
serial0 = &uart0;
ethernet0 = &emac1;
};
chosen {
stdout-path = "serial0";
};
cpucomplex: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <1000000>;
cpu0: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
status = "disabled";
cpu0intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu1: cpu@1 {
clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
cpu1intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu2: cpu@2 {
clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
cpu2intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu3: cpu@3 {
clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
cpu3intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
cpu4: cpu@4 {
clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <32768>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <32768>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
tlb-split;
status = "okay";
cpu4intc: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
refclk: refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
clock-output-names = "msspllclk";
};
ddr: memory@1000000000 {
device_type = "memory";
reg = <0x00000010 0x00000000 0x00000000 0x10000000>;
};
soc: soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "microchip,mpfs-soc", "simple-bus";
ranges;
clint0: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&cpu0intc 3 &cpu0intc 7
&cpu1intc 3 &cpu1intc 7
&cpu2intc 3 &cpu2intc 7
&cpu3intc 3 &cpu3intc 7
&cpu4intc 3 &cpu4intc 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
clock-frequency = <1000000>;
};
cachecontroller: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1 2 3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,max-priority = <7>;
riscv,ndev = <186>;
interrupt-controller;
interrupts-extended = <
&cpu0intc 11
&cpu1intc 11 &cpu1intc 9
&cpu2intc 11 &cpu2intc 9
&cpu3intc 11 &cpu3intc 9
&cpu4intc 11 &cpu4intc 9>;
};
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
reg-names = "mss_sysreg";
clocks = <&refclk>;
#clock-cells = <1>;
clock-output-names = "cpu", "axi", "ahb", "envm",
"mac0", "mac1", "mmc", "timer",
"mmuart0", "mmuart1", "mmuart2",
"mmuart3", "mmuart4", "spi0", "spi1",
"i2c0", "i2c1", "can0", "can1", "usb",
"reserved", "rtc", "qspi", "gpio0",
"gpio1", "gpio2", "ddrc", "fic0",
"fic1", "fic2", "fic3", "athena",
"cfm";
};
/* Common node entry for eMMC/SD */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc","cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
clocks = <&clkcfg 6>;
interrupt-parent = <&plic>;
interrupts = <88 89>;
max-frequency = <200000000>;
bus-width = <4>;
disable-wp;
cap-mmc-highspeed;
cap-sd-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "disabled";
};
uart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
clock-frequency = <150000000>;
clocks = <&clkcfg 8>;
status = "okay";
};
spi0: spi@20108000 {
compatible = "microchip,mpfs-spi";
reg = <0x0 0x20108000 0x0 0x1000>;
clocks = <&clkcfg 13>;
interrupt-parent = <&plic>;
interrupts = <54>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@2010b000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "microchip,mpfs-i2c";
reg = <0x0 0x2010b000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <61>;
clocks = <&clkcfg 16>;
clock-frequency = <100000>;
status = "okay";
pac193x@10 {
compatible = "microchip,pac1934";
reg = <0x10>;
samp-rate = <64>;
status = "disabled";
ch1: channel0 {
uohms-shunt-res = <10000>;
rail-name = "VDD";
channel_enabled;
};
ch2: channel1 {
uohms-shunt-res = <10000>;
rail-name = "VDDA25";
channel_enabled;
};
ch3: channel2 {
uohms-shunt-res = <10000>;
rail-name = "VDD25";
channel_enabled;
};
ch4: channel3 {
uohms-shunt-res = <10000>;
rail-name = "VDDA";
channel_enabled;
};
};
};
emac1: ethernet@20112000 {
compatible = "microchip,mpfs-macb","cdns,gem";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
interrupts = <70 71 72 73>;
local-mac-address = [00 04 A3 00 00 02];
phy-mode = "sgmii";
clocks = <&clkcfg 5>, <&clkcfg 1>;
clock-names = "pclk", "hclk";
clock-frequency = <150000000>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
};
};
gpio: gpio@20122000 {
compatible = "microchip,mpfs-gpio";
interrupt-parent = <&plic>;
interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36 37 38 39
40 41 42 43 44>;
gpio-controller;
clocks = <&clkcfg 25>;
reg = <0x00 0x20122000 0x0 0x1000>;
reg-names = "control";
#gpio-cells = <2>;
status = "disabled";
};
};
};

572
bsps/riscv/riscv/include/bsp/bvf.h Normal file
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@@ -0,0 +1,572 @@
/*
* Declarations for C structure representing binary file mpfs.dtb
*
* WARNING: Automatically generated -- do not edit!
*/
#ifndef __system_dtb_h
#define __system_dtb_h
#include <rtems/score/basedefs.h>
#include <sys/types.h>
const unsigned char system_dtb[] RTEMS_ALIGNED(8) = {
0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x38,
0x00, 0x00, 0x16, 0xd8, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x37,
0x00, 0x00, 0x16, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x1b,
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0x68, 0x79, 0x2d, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x63, 0x6c, 0x6f, 0x63,
0x6b, 0x2d, 0x6e, 0x61, 0x6d, 0x65, 0x73, 0x00, 0x70, 0x68, 0x79, 0x2d,
0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x67, 0x70, 0x69, 0x6f, 0x2d,
0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x23,
0x67, 0x70, 0x69, 0x6f, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00,
};
#endif /* __system_dtb_h */

1
spec/build/bsps/optdtb.yml
View File

@@ -7,6 +7,7 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- riscv/bvf
- riscv/mpfs64imafdc
- riscv/kendrytek210
value: true

2
spec/build/bsps/optdtbheaderpath.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
default:
- enabled-by: riscv/bvf
value: bsp/bvf.h
- enabled-by: riscv/mpfs64imafdc
value: bsp/mpfs-dtb.h
- enabled-by: riscv/kendrytek210

2
spec/build/bsps/riscv/optextirqmax.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: riscv/bvf
value: 187
- enabled-by: riscv/mpfs64imafdc
value: 187
- enabled-by: true

2
spec/build/bsps/riscv/optrambegin.yml
View File

@@ -18,6 +18,8 @@ default:
value: 0x00000000
- enabled-by: riscv/griscv
value: 0x40000000
- enabled-by: riscv/bvf
value: 0x1000000000
- enabled-by: riscv/mpfs64imafdc
value: 0x1000000000
- enabled-by: true

1
spec/build/bsps/riscv/optramsize.yml
View File

@@ -10,6 +10,7 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- riscv/bvf
- riscv/frdme310arty
- riscv/mpfs64imafdc
value: 0x10000000

1
spec/build/bsps/riscv/riscv/abi.yml
View File

@@ -8,6 +8,7 @@ copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by:
- riscv/bvf
- riscv/mpfs64imafdc
- riscv/rv64imafdc
- riscv/kendrytek210

19
spec/build/bsps/riscv/riscv/bspbvf.yml Normal file
View File

@@ -0,0 +1,19 @@
SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause
arch: riscv
bsp: bvf
build-type: bsp
cflags: []
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
cppflags: []
enabled-by: true
family: riscv
includes: []
install: []
links:
- role: build-dependency
uid: ../../opto2
- role: build-dependency
uid: grp
source: []
type: build

2
spec/build/bsps/riscv/riscv/optmpfs.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: riscv/bvf
value: true
- enabled-by: riscv/mpfs64imafdc
value: true
- enabled-by: true

2
spec/build/bsps/riscv/riscv/optns16550max.yml
View File

@@ -10,6 +10,8 @@ default:
- riscv/frdme310arty
- riscv/kendrytek210
value: null
- enabled-by: riscv/bvf
value: 1
- enabled-by: riscv/mpfs64imafdc
value: 1
- enabled-by: true

1
spec/build/cpukit/optarchbits.yml
View File

@@ -8,6 +8,7 @@ copyrights:
- Copyright (C) 2020 Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk>
default:
- enabled-by:
- riscv/bvf
- riscv/mpfs64imafdc
- riscv/noel64imac
- riscv/noel64imafd

2
spec/build/cpukit/optboothartid.yml
View File

@@ -6,6 +6,8 @@ build-type: option
copyrights:
- Copyright (C) 2020 embedded brains GmbH & Co. KG
default:
- enabled-by: riscv/bvf
value: 1
- enabled-by: riscv/mpfs64imafdc
value: 1
- enabled-by: true

1
spec/build/cpukit/optsmp.yml
View File

@@ -28,6 +28,7 @@ enabled-by:
- powerpc/qoriq_e500
- powerpc/qoriq_e6500_32
- powerpc/qoriq_e6500_64
- riscv/bvf
- riscv/griscv
- riscv/grv32imac
- riscv/grv32imafdc