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Author SHA1 Message Date
Chris Johns
5f9c208084 libfs: Fix the warning in the RFS. 
Return the first error if one or more happen when deleting an inode.
 2014-09-03 13:15:24 +10:00
Joel Sherrill
2617cd3e04 or1ksim/Makefile.am: Install shared tm27.h and regenerate preinstall.am 2014-09-02 10:57:18 -05:00
Hesham ALMatary
305357eda5 or1k: Implement context validate and context volatile clobber functions. 
score/cpu/or1k: Add two new assembly functions: _CPU_Context_validate
and _CPU_Context_volatile_clobber; their implementation follows
corresponding ARM functions.
 2014-09-02 09:29:08 -05:00
Hesham ALMatary
23e8f3dd03 Add missing r31 load instruction _ISR_Handler 
_ISR_Handler: r31 was not loaded in restore function. This patch
adds this load.
 2014-09-02 09:28:14 -05:00
Sebastian Huber
fe826e23d4 sapi: Add profiling report begin/end message 2014-09-02 14:11:47 +02:00
Sebastian Huber
8ae6f264af samples/iostream: Produce proper begin/end message 2014-09-01 17:16:53 +02:00
Sebastian Huber
5689d723a8 smptests/smplock01: Update screen file 2014-09-01 16:12:42 +02:00
Sebastian Huber
5cb5342c49 libtests/capture01: Fix test name 2014-09-01 13:28:30 +02:00
Sebastian Huber
979d95e470 libtests/capture01: Force error if SMP enabled 
This prevents infinite test runs on SMP due to the recursive interrupt
lock acquire.
 2014-09-01 10:08:12 +02:00
Sebastian Huber
4030cccfef tests: Add documentation 2014-09-01 11:01:04 +02:00
Sebastian Huber
c147a139c6 smptests/smpfatal08: Fix link error 2014-09-01 08:45:23 +02:00
Daniel Cederman
fecaeca18b score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in general 
Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that
it is LEON specific
 2014-09-01 08:11:11 +02:00
Sebastian Huber
aacb7e6aff bsp/ngmp: Use -mcpu=leon3 GCC option 
There is support for the LEON3 processor available in Binutils 2.24 and
the GCC 4.8 branch and GCC mainline.

GCC 4.8 branch:

http://gcc.gnu.org/viewcvs/gcc/branches/?view=log&pathrev=205331

GCC mainline:

http://gcc.gnu.org/viewcvs/gcc/trunk/?view=log&pathrev=202664

It is mandatory to use this option for SMP on LEON3 since it enables
usage of C11 atomic operations.  It makes it also possible to use an
inline function for _CPU_SMP_Get_current_processor() which avoids the
function call overhead in critical sections.
 2014-09-01 08:00:35 +02:00
Chris Johns
59990cc975 Regenerate all preinstall.am files. 
With this patch the preinstall.am files are in a set order and not
dependent on now perl implements a hash.
 2014-08-29 12:48:01 +10:00
Chris Johns
93d0ddd41b bootstrap: Sort the various hash keys used in generating preinstall.am. 
Something must have changed in perl to change the way the keys are
ordered by default.
 2014-08-29 11:39:29 +10:00
Joel Sherrill
b597c0d60c Regenerate all preinstall.am files. 
Apparently, at some point automake output changed and these were
not updated.
 2014-08-28 08:44:52 -05:00
Chris Johns
d04cb1242d arm: Add tests which fail to build with C++ enabled. 2014-08-28 14:34:10 +10:00
Chris Johns
5826a1b284 preinstall: Regenerated files differ from the repo. 2014-08-28 10:08:28 +10:00
Joel Sherrill
bfa2b8c39e virtex5/.../bsp.h: Add BSP_Convert_decrementer() macro required by MPC6xx timer driver 2014-08-27 12:50:36 -05:00
Joel Sherrill
6e60140daf nds/Makefile.am: Rework to avoid creating ltos of .rel files 
This was necessary to enable all tests to link.
 2014-08-27 11:00:12 -05:00
Joel Sherrill
7d3a345630 lpc40xx_ea_rom_int-testsuite.tcfg: New file 2014-08-27 10:20:12 -05:00
Sebastian Huber
34db8ec932 rtems: SMP fix for timer server 2014-08-27 14:06:10 +02:00
Chris Johns
614a0889b6 arm/lm3s3749: Add tests that do not fit. 
You need --enable-c++ for the c++ tests.
 2014-08-27 20:04:26 +10:00
Hesham ALMatary
2cd68a8bf6 Add or1ksim (sim.cfg) configuration file and edit README. 
OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW
capabilities that the current RTEMS/or1ksim BSP supports.

README: HOWTO run the or1ksim simulator.
 2014-08-26 15:32:44 -05:00
Sebastian Huber
76386c1047 bsp/altera-cyclone-v: Add DMA support hwlib files 2014-08-26 17:10:18 +02:00
Sebastian Huber
9907ddeb5a bsp/altera-cyclone-v: Update to hwlib 13.1 
This version is distributed with SoC EDS 14.0.0.200.
 2014-08-26 17:10:18 +02:00
Sebastian Huber
96ec8ee80a rtems: Add more clock tick functions 
Add rtems_clock_tick_later(), rtems_clock_tick_later_usec() and
rtems_clock_tick_before().
 2014-08-26 10:21:27 +02:00
Joel Sherrill
8f1bdcb9ad or1k/Makefile.am: libbsp_a_CPPFLAGS was defined twice 2014-08-25 17:07:12 -05:00
Joel Sherrill
3d99c17deb gensh4: Improve ROM vs RAM startup configuration 2014-08-25 17:00:49 -05:00
Joel Sherrill
bf1f876483 gensh4/bsp_specs: Account for big/little endian 2014-08-25 17:00:48 -05:00
Joel Sherrill
e75907d58e simsh4-testsuite.tcfg: new file 2014-08-25 17:00:48 -05:00
Joel Sherrill
d26cded81b simsh2e-testsuite.tcfg: new file 2014-08-25 17:00:48 -05:00
Joel Sherrill
a4d355b426 shsim/bsp_specs: Account for big/little endian 2014-08-25 17:00:48 -05:00
Hesham ALMatary
baa3c91ecb or1ksim BSP: Include cache manager stubs, and re-generate preinstall.am files. 2014-08-25 11:13:55 -05:00
Hesham ALMatary
e5f6ca87e1 Add or1k to the list of targets that use IEEE 754 in xdr_float.c 2014-08-25 11:13:36 -05:00
Hesham ALMatary
9d92a43ff7 Rename or1k_or1ksim BSP to or1ksim 2014-08-25 11:13:14 -05:00
Hesham ALMatary
eeea9e30a2 libcpu: Add new entry for or1k cpu and include cache manager stubs. 2014-08-25 11:12:20 -05:00
Hesham ALMatary
23b14f87cf sptests/spcache01: Make inline assembly conditional to account for OpenRISC l.nop instruction. 2014-08-25 11:12:16 -05:00
Sebastian Huber
4b104834eb bsp/mpc55xx: Fix comment 2014-08-25 13:40:20 +02:00
Sebastian Huber
f3237a3c3b bsp/mpc55xx: Add defines for MPC5668 2014-08-25 09:30:53 +02:00
Sebastian Huber
0a31483901 bsp/mpc55xx: Limit flash support to MPC55[56]X 2014-08-25 09:11:05 +02:00
Sebastian Huber
f553c6ebbe rtems: Inline rtems_clock_get_ticks_since_boot() 
Update documentation.
 2014-08-25 08:57:36 +02:00
Daniel Cederman
e7a42a0cfb score: Add missing define to cache manager 2014-08-25 08:52:05 +02:00
Pavel Pisa
d13ce7553b bsp/tms570: implemented and tested initialization of Cortex-R performance counters. 
The code is written as BSP specific now but it should work for all
Cortex-A and R based CPUs and can be moved to ARM generic place in future.

StackOverflow suggested sequences of writes to the registers required
to start counters is used.

http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
 2014-08-22 10:24:53 -05:00
Daniel Cederman
9a9ab85b45 smptests/smpcache01: Test the SMP cache manager 
Invokes SMP cache management routines under different scenarios.
 2014-08-22 13:10:59 +02:00
Daniel Cederman
ddbc3f8d83 score: Add SMP support to the cache manager 
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
 2014-08-22 13:10:59 +02:00
Daniel Cederman
62f373fb57 bsp/sparc: Flush only instruction cache 
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
 2014-08-22 13:10:59 +02:00
Daniel Cederman
bba83e5191 score/sparc: Add comment on icache flush after trap table update 
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
 2014-08-22 13:10:59 +02:00
Daniel Cederman
54f3476e24 bsp/sparc: Flush icache before first time enabling interrupts 
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
 2014-08-22 13:10:59 +02:00
Daniel Cederman
aed38189be score: Rename SMP broadcast message function 
Change message type to unsigned long to match other SMP message functions.
 2014-08-22 13:10:59 +02:00