forked from Imagelibrary/rtems
bba83e5191
Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache just after entering the up state, but before enabling interrupts. Cache invalidation is required for both single and multiprocessor systems.
This is the Real-Time Executive for Multiprocessing Systems (RTEMS). The version number for this software is indicated in the VERSION file. See the documentation manuals in doc/ with daily builds available online at http://rtems.org/onlinedocs/doc-current/share/rtems/html/ and released builds at http://www.rtems.org/onlinedocs/releases/ for information on building, installing, and using RTEMS. The INSTALL file tells you to come back here. See the RTEMS Wiki at http://wiki.rtems.org/wiki/index.php/Main_Page for community knowledge and tutorials. RTEMS Doxygen available at http://www.rtems.org/onlinedocs/doxygen/cpukit/html Get help on the mailing lists: * For general-purpose questions related to using RTEMS, use the rtems-users ml: http://www.rtems.org/mailman/listinfo/rtems-users * For questions and discussion related to development of RTEMS, use the rtems-devel ml: http://www.rtems.org/mailman/listinfo/rtems-devel See http://www.rtems.org/bugzilla/ to report a bug.