Add or1ksim (sim.cfg) configuration file and edit README.

OpenRISC/or1ksim BSP: The new sim.cfg file configures or1ksim emulator with HW
capabilities that the current RTEMS/or1ksim BSP supports.

README: HOWTO run the or1ksim simulator.

c/src/lib/libbsp/or1k/or1ksim/README

@@ -14,4 +14,22 @@ Configuration file "sim.cfg" should be provided for complex board
 configurations at the current directory (which you run or1ksim from) or at
 ~/.or1k/
 
-sim -f sim.cfg hello.exe
+The current sim.cfg file that configures or1ksim emulator to RTEMS/or1ksim BSP
+is at the same directory as this README. You can also use or1ksim script from
+rtems-tools/sim-scripts.
+
+From command line type:
+
+sim -f sim.cfg $PATH_TO_RTEMS_EXE
+
+or (if you use a stable or1ksim release)
+
+or32-elf-sim -f sim.cfg $PATH_TO_RTEMS_EXE
+
+from sim-scripts:
+
+or1ksim $PATH_TO_RTEMS_EXE
+
+and then attach GDB to or1ksim from another terminal by running
+
+or1ksim-gdb $PATH_TO_RTEMS_EXE

c/src/lib/libbsp/or1k/or1ksim/sim.cfg

@@ -0,0 +1,104 @@
+section memory
+  name     =      "RAM"
+  random_seed = 12345
+  type        = random
+  ce       =          0
+  mc       =          0
+  baseaddr = 0x00000000
+  size     = 0x08000000
+  delayr   =          1
+  delayw   =          2
+end
+
+section immu
+  enabled = 0
+  nsets = 64
+  nways = 1
+  pagesize = 8192
+  hitdelay = 0
+  missdelay = 0
+end
+
+section dmmu
+  enabled = 0
+  nsets = 64
+  nways = 1
+  pagesize = 8192
+  hitdelay = 0
+  missdelay = 0
+end
+section mc
+  enabled = 0
+  baseaddr = 0x90000000
+  POC = 0x0000000a                 /* 32 bit SSRAM */
+  index = 0
+end
+
+section ic
+  enabled   =   0
+  nsets     = 256
+  nways     =   1
+  blocksize =  16
+  hitdelay  =  20
+  missdelay =  20
+end
+
+section dc
+  enabled = 0
+  nsets = 256
+  nways = 1
+  blocksize = 16
+  load_hitdelay = 0
+  load_missdelay = 0
+  store_hitdelay = 0
+  store_missdelay = 0
+end
+
+section pic
+  enabled = 1
+  edge_trigger = 1
+end
+
+section sim
+  verbose  =  1
+  debug    =  0
+  profile  =  0
+  history  =  0
+  clkcycle = 10ns		/* 100MHz clock */
+end
+
+section VAPI
+  enabled = 1
+  server_port = 50000
+  log_enabled = 1
+  vapi_log_file = "vapi.log"
+end
+
+section cpu
+  ver = 0x12
+  cfg = 0x00
+  rev = 0x0001
+  superscalar = 0
+  hazards = 0
+  dependstats = 0
+  sbuf_len = 100
+end
+
+section debug
+ enabled = 1
+ rsp_enabled = 1
+ rsp_port = 50001
+end
+
+section uart
+  enabled  = 1
+  baseaddr = 0x90000000
+ #channel = "xterm"
+  channel = "file:uart0.rx,uart0.tx"
+  irq = 2
+  16550    = 1
+end
+
+section pm
+  enabled = 1
+end