Daniel Cederman 54f3476e24 bsp/sparc: Flush icache before first time enabling interrupts
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
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This is the Real-Time Executive for Multiprocessing Systems (RTEMS).
The version number for this software is indicated in the VERSION file.

See the documentation manuals in doc/ with daily builds available online at
http://rtems.org/onlinedocs/doc-current/share/rtems/html/ and released builds
at http://www.rtems.org/onlinedocs/releases/ for information on building,
installing, and using RTEMS. The INSTALL file tells you to come back here.

See the RTEMS Wiki at http://wiki.rtems.org/wiki/index.php/Main_Page
for community knowledge and tutorials.

RTEMS Doxygen available at http://www.rtems.org/onlinedocs/doxygen/cpukit/html

Get help on the mailing lists:
* For general-purpose questions related to using RTEMS, use the
  rtems-users ml: http://www.rtems.org/mailman/listinfo/rtems-users
* For questions and discussion related to development of RTEMS, use the
  rtems-devel ml: http://www.rtems.org/mailman/listinfo/rtems-devel

See http://www.rtems.org/bugzilla/ to report a bug.

Description
RTEMS is a ​real-time executive in use by embedded systems applications around the world and beyond
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