Commit Graph

37944 Commits

Author SHA1 Message Date
Sebastian Huber
f76b04e133 build: Move FatFS build support
Use a separate build objects item for the FatFS to localize the use of command
line defines.
2026-03-24 02:54:23 +01:00
Matteo Concas
40818d91c5 riscv/sbi: Correct path 2026-03-20 10:31:46 +01:00
Yash
6c28b540fa libfs/dosfs: Add Doxygen headers and fix typo in msdos_init.c
Add missing Doxygen file headers to msdos.h and msdos_init.c to
comply with documentation standards. Correct a typo ('apropriately'
to 'appropriately') in msdos_init.c.
2026-03-19 19:18:21 -05:00
Mohamed Ayman
1097e00b5f arm/stm32f4: extend USART DR field to 9 bits
The STM32F4 USART data register supports up to 9-bit data
when CR1.M is set. The current DR macros mask only bits [7:0],
which truncates the MSB in 9-bit mode.
Extend the field width to [8:0] to match the hardware
definition while remaining compatible with 8-bit mode.
2026-03-19 19:13:44 -05:00
Vhmed-Mvnsour
0e86a5de8e doxygen: Update logo to current RTEMS logo
The old Doxygen logo is outdated and has been replaced with the

current RTEMS logo.

Closes #5495
2026-03-19 18:31:52 -05:00
Prakhar Kumar
b3a0dc0966 CRC check: Added CRC check in flashdisk
- added CRC check for rtems_fdisk_recover_block_mappings function
- Computes CRC of page data and compares with page descriptor
- Marks pages as bad if CRC mismatch occurs
2026-03-19 18:10:59 -05:00
Mohamed Ayman
6e83c38851 bsps/arm/stm32f4: fix HPRE bitfield Possible Bug in STM32F4 RCC header
Fix HPRE macro in cfgr register: original spanned bits 4–15,
accidentally overwriting APB1/APB2 prescaler bits (10–15).
Corrected range to 4–7, matching hardware specification.
2026-03-19 16:10:33 -05:00
Gedare Bloom
eeee01453d riscv: init FPU in s-mode
Fixes omission of initializing the FPU during shared boot
in s-mode.
2026-03-19 11:34:13 -05:00
Mohamed Ayman
485efbd418 docs: correct spelling and grammar in stm32f4 headers
Fixed various typos and grammatical errors throughout the documentation
in the stm32f4 include folder to improve readability.
2026-03-19 11:06:27 -05:00
Sebastian Huber
caead7cefc build: Add comment to command line options
Add a comment to explain the preference of using build options.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2026-03-19 10:46:15 -05:00
Mohamed Ayman
beea2a5683 stm32f4/usart: fix BRR calculation logical issues
Fix two issues in the BRR calculation logic.
First the fractional part was computed using an incorrect formula, which
can produce invalid values and does not match the USARTDIV equation. This
also risks a division-by-zero in some cases. The calculation is updated to
follow the correct relation between pclk, baud, and USARTDIV.
Second the computation of the higher approximation of USARTDIV was not
consistent with the intended logic. The update ensures the next valid
step is computed properly when refining the divisor.
These changes make the baud rate calculation more accurate and reliable.
2026-03-18 14:54:00 -05:00
Mohamed Ayman
050fc00c5a bsps/arm/stm32f4: Fix FLASH register macro definitions
Fix incorrect definition of STM32F4_FLASH_CR_SNB which was missing
its macro parameter.
Also correct the register prefix of OPTSTRT and OPTLOCK which belong
to the FLASH_OPTCR register instead of FLASH_CR.
2026-03-18 19:49:25 +00:00
Mohamed Ayman
3b052ba8bf bsps/arm/stm32f4: Fix incorrect bit definition for EXTI line 22
EXTI_LINE22 was incorrectly defined as BSP_BIT32(21), which conflicts
with EXTI_LINE21. Correct it to BSP_BIT32(22).
2026-03-18 19:48:44 +00:00
Mohamed Ayman
a1a1e16b11 BUG: Fix AFIO bit clearing in set_remap_config
Previously, the AFIO register bits were not cleared correctly before
setting the remap value, which could overwrite unrelated bits and
cause GPIO remapping to behave incorrectly.

This change ensures that only the intended bits are cleared and updated,
so GPIO remapping works as expected on STM32F10xxx devices.
2026-03-18 19:48:02 +00:00
Mohamed Ayman
dc11184541 arm/stm32f4: Fix I2C mutex initialization and potential mutex leak
Fix two issues in the STM32F4 I2C driver related to mutex handling.
The mutex protecting the I2C bus was created with an initial count of
0. For a binary semaphore used as a mutex this causes the first
rtems_semaphore_obtain() call to block indefinitely since the semaphore
starts in the locked state. Initialize the semaphore with a count of 1
so it starts unlocked.
Additionally, stm32f4_i2c_process_message() could return early if the
STOP bit was set in CR1 without releasing the mutex. This would leave
the mutex locked and cause subsequent calls to deadlock. Release the
mutex before returning in this case.
Also cast dummy SR2 reads to (void) to make the intent explicit and
avoid potential compiler warnings about statements with no effect.

arm/stm32f4: Fix I2C mutex initialization and potential mutex leak

fix the indentation on these lines.
2026-03-18 19:46:21 +00:00
Mohamed Ayman
14605b6d2b arm/stm32f4: fix SYSCFG register layout
The SYSCFG register block misses two reserved registers between
EXTICR4 and CMPCR. This causes CMPCR to be mapped at the wrong
offset (0x18 instead of 0x20).
Add the missing reserved fields to preserve the correct hardware
register layout according to the STM32F4 reference manual.
2026-03-18 19:43:25 +00:00
Mohamed Ayman
657cd11729 bsps/arm/stm32f4: Correct PLS macro Potential Bug in STM32F4 PWR header
STM32F4_PWR_CR_PLS now correctly takes a 'val' argument
to avoid compilation errors when selecting PVD level.
Verified other CR/CSR bit definitions and comments; no spelling issues.
2026-03-18 14:10:01 -05:00
Gedare Bloom
df28cf6e31 riscv/riscv: fix incorrect uses of SIP_STIP for SIP_SSIP
Fixes #5522
2026-03-18 12:44:46 -06:00
Gedare Bloom
e3ec0ab811 riscv/riscv: refactor FDT helper functions
Adds bsp/riscv-fdt.h with new functions for pulling information from
the FDT.
2026-03-18 12:44:46 -06:00
Gedare Bloom
6952bcf1ef riscv/riscv: remove RISCV_FATAL_CLOCK_SMP_INIT
Fixes #5486
2026-03-18 12:44:46 -06:00
Gedare Bloom
2c16558469 riscv/riscv: s-mode booting with SMP
Closes #3337
2026-03-18 12:44:46 -06:00
Gedare Bloom
fd4b66ff12 riscv/riscv: use shutdown SBI in s-mode
Updates #3337
2026-03-18 12:44:46 -06:00
Gedare Bloom
32de7146e2 riscv/riscv: support using SBI timer in s-mode
Uses the sbi_set_timer() SBI call if the Sstc extension is not found in
the FDT.

Also fixes rv32 support for s-mode timers.

Updates #3337
2026-03-18 12:44:46 -06:00
Yash
f8f6311b99 bsps/powerpc: Add Doxygen and formatting to Motorola BSPs
Add Doxygen-style file headers and fix specific typos in comments
to improve documentation and compliance with coding standards.
2026-03-18 08:34:57 +00:00
Sebastian Huber
28588dcc59 build: Check the GCC build key
Query the GCC build key and check it against the required value.

There are dependencies between the RTEMS sources and external interfaces
provided by Newlib and GCC.  For example, POSIX API interfaces may
change due to POSIX standard updates.  The GCC build key is used to
provide an indication that the present tools meet the requirements of
the RTEMS sources.

Add the GCC_BUILD_KEY_POLICY build option to define the checking policy.
The GCC build key policy defines how the build key of the present
compiler is checked against the required build key.  While the policy is
"ERROR", if the GCC build key has not the expected value, then the build
configuration process produces a fatal error.  While the policy is
"WARNING", if the GCC build key has not the expected value, then the
build configuration process produces a warning message.  While the
policy is "IGNORE", the GCC build key is not checked at all.  The
default policy is "WARNING".

Close #5521.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2026-03-18 02:24:45 +01:00
Chris Johns
5a16f9dd50 cpukit/rtems: Set the timer's chain node to off chain before appending
The timer's node is shared with the RB tree and before placing it on the
timer server's chain the node needs to set to off chain or
RTEMS_DEBUG may assert.
2026-03-16 17:03:56 -05:00
Cibi P
87cf29708f bsps/arm/realview-pbx-a9: Fix PL111 MMU mapping
The PL111 registers at 0x10020000 were not included in the
initial MMU device section. This caused a fatal source
exception during the framebuffer initialization.

Update the mapping to include the PL111 region
2026-03-16 18:48:10 +05:30
Mohamed Ayman
70adad45f7 docs: Fix spelling mistakes in stm32f4 bspstart documentation
Correct several spelling mistakes in the STM32F4 BSP
bspstart documentation to improve readability and documentation quality.
2026-03-15 14:54:12 -05:00
Vhmed-Mvnsour
30811dcf82 bsps/grlib: Fix IRQAMP MPSTAT register mask
The MPSTAT status field is 16 bits according to the GRLIB IP Core Manual.

Closes #5506
2026-03-12 04:44:09 +02:00
Mohammed Anees
a1551f1737 bsps/i386: Remove Redundant imps_lapic_addr extern declaration
The variable is already defined in smp-imps.c and declared in the
header. The additional extern declaration in the source file is
unnecessary and can be removed.
2026-03-11 22:42:10 +00:00
Sebastian Huber
e876fa1d27 score: Fix _Thread_Dispatch_unnest()
Commit ddd6f3d962 accidentally changed a
decrement into an increment.

Update #5505.
Fix #5517.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2026-03-11 10:12:24 +01:00
Shivam Deolankar
f2a3dd2b62 build: Separate SECTION_FLAGS from OPTIMIZATION_FLAGS
Move -ffunction-sections and -fdata-sections into new SECTION_FLAGS
option to prevent breakage when users override OPTIMIZATION_FLAGS.
Also added documentation for user's to override the flags.

Fixes stack checker undefined reference when OPTIMIZATION_FLAGS=-g.

Also added a copyright field for valid license.

Fixes #5497
2026-03-09 14:49:02 +00:00
Gedare Bloom
e8d948eba1 riscv/riscv: support s-mode IRQ handling
Separate the IRQ handling for M- and S-mode. S-Mode IRQ handling is
not available for external interrupts.

Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
dda1d34e59 riscv: avoid accessing per_cpu mtime variable in s-mode
updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
95a9e7aed6 riscv: use software irq in tm27 with s-mode
updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
7209cd44d1 riscv: support CPU counter in s-mode
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
7f46d3ca7a riscv/riscv: add clock driver using stimecmp
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
8ed01d70cc riscv/riscv: refactor clock driver
Separate the parts of the clock that rely on the CLINT to prepare
for an S-Mode clock driver.

Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
348e855f31 cpukit/riscv: remove s/m prefix on frame context regs
Use status, epc, and cause instead of providing m/s variants of each.

Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
598332c765 riscv: enable s-mode in CPU port
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
cdb253bac3 bsps/riscv: support s-mode irq handling
Updates #3337.
2026-03-06 11:35:16 -06:00
Gedare Bloom
aed3681616 bsps/riscv: support s-mode timer in clock driver
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
d7ff9f4da5 bsps/riscv: support SMP secondary processors
Fixes boot and per-cpu information for SMP

Updates #3337.
2026-03-06 11:35:16 -06:00
Gedare Bloom
b5264e4662 riscv: support s-mode during boot
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
ea31fe6cd8 spec/build: add RISCV_USE_S_MODE option
Updates #3337
2026-03-06 11:35:16 -06:00
Gedare Bloom
ea1d5dcd67 contrib/riscv/sbi: make 32-bit clean
Updates #3337
2026-03-06 11:31:08 -06:00
Gedare Bloom
10cb664875 spec/build/riscv: add SBI
Enable the imported SBI in the build for riscv/riscv.

Other riscv BSPs would need to add the entry for optincludes
in addition to adding objsbi to their grp.

Updates #3337
2026-03-06 11:31:08 -06:00
Gedare Bloom
da3313a562 contrib/riscv: adapt imported SBI to rtems
Updates #3337
2026-03-06 11:31:08 -06:00
Gedare Bloom
cee307c60f contrib: import sbi from freebsd 15.0.0
Upstream version: 15.0.0
Upstream source: https://cgit.freebsd.org/src/

https://cgit.freebsd.org/src/tag/?h=release/15.0.0

Files from sys/riscv/riscv/ and sys/riscv/include
2026-03-06 11:31:08 -06:00
Sebastian Huber
ddd6f3d962 score: Do not use deprecated volatile operation
C++20 deprecated some volatile operations including increments.

Fix #5505.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
2026-03-06 11:30:16 -06:00