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bsps/arm/stm32f4: fix HPRE bitfield Possible Bug in STM32F4 RCC header

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Fix HPRE macro in cfgr register: original spanned bits 4–15,
accidentally overwriting APB1/APB2 prescaler bits (10–15).
Corrected range to 4–7, matching hardware specification.
This commit is contained in:
Mohamed Ayman
2026-03-15 22:38:33 +02:00
committed by Kinsey Moore
parent eeee01453d
commit 6e83c38851
1 changed files with 1 additions and 1 deletions
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2
bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h
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@@ -128,7 +128,7 @@ typedef struct {
#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5)
#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6)
#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7)
#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar
#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 7) // AHB prescalar
#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7)
#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0)