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cpukit/riscv: remove s/m prefix on frame context regs

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Use status, epc, and cause instead of providing m/s variants of each.

Updates #3337
This commit is contained in:
Gedare Bloom
2026-02-20 11:12:22 -07:00
committed by Kinsey Moore
parent 598332c765
commit 348e855f31
5 changed files with 25 additions and 19 deletions
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6
cpukit/score/cpu/riscv/cpu.c
View File

@@ -83,8 +83,8 @@ RISCV_ASSERT_CONTEXT_OFFSET( fs11, FS11 );
riscv_interrupt_frame_offset_ ## field \
)
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( status, STATUS );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( epc, EPC );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 );
RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 );
@@ -136,7 +136,7 @@ RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( fa7, FA7 );
riscv_context_offset_ ## field \
)
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( mcause, MCAUSE );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( cause, CAUSE );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( sp, SP );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( gp, GP );
RISCV_ASSERT_EXCEPTION_FRAME_OFFSET( tp, TP );

6
cpukit/score/cpu/riscv/include/rtems/score/cpu.h
View File

@@ -295,8 +295,8 @@ typedef enum {
} RISCV_Exception_code;
typedef struct {
uintptr_t mstatus;
uintptr_t mepc;
uintptr_t status;
uintptr_t epc;
uintptr_t a2;
uintptr_t s0;
uintptr_t s1;
@@ -342,7 +342,7 @@ typedef struct {
typedef struct {
CPU_Interrupt_frame Interrupt_frame;
uintptr_t mcause;
uintptr_t cause;
uintptr_t sp;
uintptr_t gp;
uintptr_t tp;

10
cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h
View File

@@ -80,8 +80,8 @@
#define RISCV_CONTEXT_S10 60
#define RISCV_CONTEXT_S11 64
#define RISCV_INTERRUPT_FRAME_MSTATUS 0
#define RISCV_INTERRUPT_FRAME_MEPC 4
#define RISCV_INTERRUPT_FRAME_STATUS 0
#define RISCV_INTERRUPT_FRAME_EPC 4
#define RISCV_INTERRUPT_FRAME_A2 8
#define RISCV_INTERRUPT_FRAME_S0 12
#define RISCV_INTERRUPT_FRAME_S1 16
@@ -158,8 +158,8 @@
#define RISCV_CONTEXT_S10 112
#define RISCV_CONTEXT_S11 120
#define RISCV_INTERRUPT_FRAME_MSTATUS 0
#define RISCV_INTERRUPT_FRAME_MEPC 8
#define RISCV_INTERRUPT_FRAME_STATUS 0
#define RISCV_INTERRUPT_FRAME_EPC 8
#define RISCV_INTERRUPT_FRAME_A2 16
#define RISCV_INTERRUPT_FRAME_S0 24
#define RISCV_INTERRUPT_FRAME_S1 32
@@ -220,7 +220,7 @@
#endif /* __riscv_xlen */
#define RISCV_EXCEPTION_FRAME_MCAUSE RISCV_EXCEPTION_FRAME_X( 0 )
#define RISCV_EXCEPTION_FRAME_CAUSE RISCV_EXCEPTION_FRAME_X( 0 )
#define RISCV_EXCEPTION_FRAME_SP RISCV_EXCEPTION_FRAME_X( 1 )
#define RISCV_EXCEPTION_FRAME_GP RISCV_EXCEPTION_FRAME_X( 2 )
#define RISCV_EXCEPTION_FRAME_TP RISCV_EXCEPTION_FRAME_X( 3 )

12
cpukit/score/cpu/riscv/riscv-exception-frame-print.c
View File

@@ -40,9 +40,15 @@
void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
{
printk("mstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.mstatus);
printk("mcause " PRINT_REG "\n", frame->mcause);
printk("mepc " PRINT_REG "\n", frame->Interrupt_frame.mepc);
#ifdef RISCV_USE_S_MODE
printk( "sstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.status );
printk( "scause " PRINT_REG "\n", frame->cause );
printk( "sepc " PRINT_REG "\n", frame->Interrupt_frame.epc );
#else
printk( "mstatus 0x%08" PRIxPTR "\n", frame->Interrupt_frame.status );
printk( "mcause " PRINT_REG "\n", frame->cause );
printk( "mepc " PRINT_REG "\n", frame->Interrupt_frame.epc );
#endif
printk("ra " PRINT_REG "\n", frame->Interrupt_frame.ra);
printk("sp " PRINT_REG "\n", frame->sp);
printk("gp " PRINT_REG "\n", frame->gp);

10
cpukit/score/cpu/riscv/riscv-exception-handler.S
View File

@@ -85,8 +85,8 @@ SYM(_RISCV_Exception_handler):
SREG t4, RISCV_INTERRUPT_FRAME_T4(sp)
SREG t5, RISCV_INTERRUPT_FRAME_T5(sp)
SREG t6, RISCV_INTERRUPT_FRAME_T6(sp)
SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp)
SREG a1, RISCV_INTERRUPT_FRAME_STATUS(sp)
SREG a2, RISCV_INTERRUPT_FRAME_EPC(sp)
#if __riscv_flen > 0
sw s1, RISCV_INTERRUPT_FRAME_FCSR(sp)
FSREG ft0, RISCV_INTERRUPT_FRAME_FT0(sp)
@@ -218,8 +218,8 @@ SYM(_RISCV_Exception_handler):
.Lthread_dispatch_done:
/* Restore */
LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp)
LREG a0, RISCV_INTERRUPT_FRAME_STATUS(sp)
LREG a1, RISCV_INTERRUPT_FRAME_EPC(sp)
LREG s0, RISCV_INTERRUPT_FRAME_S0(sp)
LREG s1, RISCV_INTERRUPT_FRAME_S1(sp)
LREG ra, RISCV_INTERRUPT_FRAME_RA(sp)
@@ -298,7 +298,7 @@ SYM(_RISCV_Exception_handler):
.Lsynchronous_exception:
SREG a0, RISCV_EXCEPTION_FRAME_MCAUSE(sp)
SREG a0, RISCV_EXCEPTION_FRAME_CAUSE(sp)
addi a0, sp, CPU_INTERRUPT_FRAME_SIZE
SREG a0, RISCV_EXCEPTION_FRAME_SP(sp)
SREG gp, RISCV_EXCEPTION_FRAME_GP(sp)