Now that the SDM (finally) at least mentions it (without giving it a
proper instruction page, though), let's (again: finally) also support it
in assembler and disassembler.
In CLANG_PLUGIN_FILE it is possible for plugin_file to be non-NULL
when LLVMgold.so does not exist.
configure output is messy, with results not printed against their
"checking.." line, eg.
checking for clang... (cached) yes
checking for clang plugin file... checking for x86_64-pc-linux-gnu-ar... (cached) ar --plugin /usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so
/usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so
This patch fixes those problems, and a similar interposition of other
configure output between AC_MSG_CHECKING and AC_MSG_RESULT in
gcc-plugin.m4. It also tidies some of the message text, and makes
similar code in gcc-plugin.m4 and clang-plugin.m4 a little more
consistent.
config/
* clang-plugin.m4 (CLANG_PLUGIN_FILE): Don't place checks for
tools (llvm-config, ar) inside AC_MSG_CHECKING..AC_MSG_RESULT
for clang plugin file. Clear plugin_file before loop exit.
(CLANG_PLUGIN_FILE_FOR_TARGET): Similarly.
* gcc-plugin.m4 (GCC_PLUGIN_OPTION): Similarly.
(GCC_PLUGIN_OPTION_FOR_TARGET): Correct AC_MSG_CHECKING. Tidy
return code.
binutils/
* testsuite/lib/binutils-common.exp <llvm_plug_opt>: Set for
non-native.
* configure: Regenerate.
/
* configure: Regenerate.
bfd/
* configure: Regenerate.
gas/
* configure: Regenerate.
gdb/
* configure: Regenerate.
gprof/
* configure: Regenerate.
gprofng/
* configure: Regenerate.
* libcollector/configure: Regenerate.
ld/
* configure: Regenerate.
libbacktrace/
* configure: Regenerate.
libctf/
* configure: Regenerate.
libiberty/
* configure: Regenerate.
libsframe/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
sim/
* configure: Regenerate.
zlib/
* configure: Regenerate.
The s390 opcode table s390-opc.tbl is generated from s390-opc.txt
using the s390-mkopc utility using output redirection. If s390-mkopc
fails with a non-zero return code, e.g. due to a warning or error, an
incomplete opcode table may be generated in the build directory. A
subsequent invocation of make then assumes that incomplete opcode
table to be up to date. Depending on the s390-mkopc issue the build
may then proceed without any follow-on warnings or errors, causing
the preceding error or warning to go unnoticed.
Generate the s390 opcode table into an intermediate temporary file
s390-opc.tbl.tmp in the build directory and only move it to the final
target s390-opc.tbl if the generation was successful.
Tested by appending an unsupported inline comment "# TEST" to one of
the instructions defined in s390-opc.txt.
opcodes/
* Makefile.am (s390-opc.tab): Use an intermediate temporary file
to prevent updating of the target on error/warning.
* Makefile.in: Regenerated.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
In Binutils, we choose to keep the AMX-TRANSPOSE support for
now in case there are vendors want to utilize the instructions
although the feature itself is de-published. AMX-TRANSPOSE will
not show up on any Intel/AMD hardware. Also in foreseeable future,
no hardware will support AMX-TRANSPOSE, we will disable it by
default.
gas/ChangeLog:
* testsuite/gas/i386/x86-64-amx-movrs-intel.d:
Move AMX-TRANSPOSE part to AMX-TRANSPOSE test.
* testsuite/gas/i386/x86-64-amx-movrs.d: Ditto.
* testsuite/gas/i386/x86-64-amx-movrs.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-bad.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
* testsuite/gas/i386/x86-64-amx-movrs-inval.l: Move
AMX-TRANSPOSE part to AMX-TRANSPOSE file. Remove
noamx_transpose test.
* testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-bad.d:
Add AMX-MOVRS and AMX-TF32 related test.
* testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Remove AMX-MOVRS invalid test.
* testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d:
New test originally comes from APX_F test.
* testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-apx.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-apx.s: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Disable AMX-TRANSPOSE by default.
* i386-init.h: Regenerated.
This reverts commit bafcf0823c.
The patch (the removal) was done on the wrong assumption that
it was only the APX-promoted forms which would be dropped
because the APX spec was updated ahead of ISE and there was no
info that AMX-TRANSPOSE would be de-published at that time.
Given the current situation, since we will choose to disable
AMX-TRANSPOSE but not to remove the support in Binutils, we will
also not remove the APX support.
For one, all PadLock insns depend on CR4.FXSR to be enabled, which means
they ought to be taking FXSR as a prereq.
Furthermore none of them permits a REPNE prefix; such forms are documented
to cause #UD. (This is mainly relevant for XSTORE, which doesn't include a
REP prefix in its base encoding. For the others this merely is a change in
what diagnostic is issued.)
Finally it is documented that an operand size prefix also causes #UD.
A check in print_insn_aarch64_word asserted that part of the encoding
space couldn't contain any valid encodings, and then returned ERR_NYI
("Not Yet Implemented", perhaps?) for these values. However, some of
the new FEAT_MOP4 instructions will trigger the assert. The check seems
to be outdated, and is clearly no longer valid, so it can just be
deleted.
Additionally, there are no other assignments of ERR_NYI, so delete all
remaining references to this error type.
Update aarch64_{ins|ext}_simple_index to use constant fields, and swap
the order of the index and regno fields, so that the regno occupies the
last five bits. (Splitting/combining a variable length value and a
fixed length value is easiest if the fixed length value occupies the
least significant bits.)
Many instructions have constraints on the range of registers they can
use. This means that some bits in the register number are fixed, and
therefore aren't mapped to a field in the instruction encoding.
Currently we use various adhoc rules to handle these fixed bits, but
this doesn't handle all cases and we often have to write new code to
support new combinations of permitted registers.
This patch allows these constant bits to instead be specified in the
same structure used to represent instruction fields. Uses of the new
constant fields will be introduced in subsequent patches.
This patch adds support for hypervisor control registers on AArch64,
available via the Generic Interrupt Controller v5 feature, and enabled
via the +gcie flag.
- ich_apr_el2
- ich_contextr_el2
- ich_hfgitr_el2
- ich_hfgrtr_el2
- ich_hfgwtr_el2
- ich_hppir_el2 (RO)
- ich_ppi_activer[0,1]_el2
- ich_ppi_dvir[0,1]_el2
- ich_ppi_enabler[0,1]_el2
- ich_ppi_pendr[0,1]_el2
- ich_ppi_priorityr[0,15]_el2
- ich_vctlr_el2
- ich_vmcr_el2
This patch adds support for PPI registers on AArch64, available via the
Generic Interrupt Controller v5 feature, and enabled via the +gcie flag.
- icc_ppi_cactiver[0,1]_el1
- icc_ppi_cpendr[0,1]_el1
- icc_ppi_enabler[0,1]_el1
- icc_ppi_hmr[0,1]_el1 (RO)
- icc_ppi_priorityr[0,15]_el1
- icc_ppi_sactiver[0,1]_el1
- icc_ppi_spendr[0,1]_el1
Also, the new system register 'icc_ppi_priorityr8_el1' clashed with the
encoding of 's3_0_c12_c15_0' used in a test for the generic syntax of
system registers using mrs and msr.
This patch replaces 's3_0_c12_c15_0' in the test by an unused encoding:
s3_7_c0_c15_0.
This patch adds support for 13 new AArch64 system registers for the CPU
interface, which are enabled on using Generic Interrupt Controller v5
(+gcie flag) feature:
- 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3
ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3.
- 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1,
ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1.
Note: the already-existing ID_AA64PFR2_EL1 register is required by the
GICv5 feature.
Add new instructions from the Generic Interrupt Controller, GICv5,
extension. These instructions are aliases to system instructions and are
the following:
* gic <operation>, <reg>
* gicr <reg>, <operation>
* gsb <operation>
Generic Interrupt Controller v5, GICv5, adds new system registers
and system instructions. These are enabled with the +gcie flag, where
gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt
Extension.
This avoids a gcc-14.2 bug reporting an "error: null destination
pointer" on an sprintf buffer that is not NULL. Don't ask me why this
happens to work.
* msp430-dis.c (msp430_singleoperand): Don't overprint op or
comm for extended_dst.
This is the binutils fix for PR 33384. Here we are assuming that no
const char* comma-separated option strings are passed in to
disassemble_info.disassembler_options. That is true for current usage
in gdb and binutils. In fact, there is only one place that passes a
string in read-only memory, gdb/tdep-i386.c:disassembly_flavor, and
that one is a single option.
include/
* dis-asm.h (struct disassemble_info): Comment.
(disassembler_options_cmp, next_disassembler_option),
(FOR_EACH_DISASSEMBLER_OPTION): Delete.
(for_each_disassembler_option): Declare.
opcodes/
* disassemble.c (disassembler_options_cmp): Delete.
(for_each_disassembler_option): New function.
* arc-dis.c (parse_option): Replace disassembler_options_cmp
with strcmp.
(parse_cpu_option): Likewise.
(parse_disassembler_options): Replace FOR_EACH_DISASSEMBLER_OPTION
with for_each_disassembler_option, and extract loop body to..
(arc_parse_option): ..this new function.
* arm-dis.c (parse_arm_disassembler_options): Delete, extracting
loop body to..
(arm_parse_option): ..this new function.
(print_insn): Use for_each_disassembler_option.
* csky-dis.c (parse_csky_dis_options): Delete, extracting loop
body to..
(parse_csky_option): ..this new function.
(print_insn_csky): Use for_each_disassembler_option.
* nfp-dis.c (parse_disassembler_options): Replace
FOR_EACH_DISASSEMBLER_OPTION with for_each_disassembler_option,
and extract loop body to..
(nfp_parse_option): ..this new function. Use opcodes_error_handler
here rather than info->fprintf_func to print error.
* ppc-dis.c (ppc_parse_cpu): Replace disassembler_options_cmp
with strcmp.
(struct ppc_parse_data): New.
(powerpc_init_dialect): Adjust to use new struct. Replace
FOR_EACH_DISASSEMBLER_OPTION with for_each_disassembler_option,
and extract loop body to..
(ppc_parse_option): ..this new function.
Historically we have been inconsistent and overly restrictive in our
choice of features to gate system register accesses. (Originally this
gating was always applied, but now it is disabled unless the
--menable-sysreg-checking option is specified).
This patch updates these constraints, following the principle that we
should only reject a system register access if it requires some
architecture feature or version whose corresponding command line
extension has not been enabled.
The most common change in this patch concerns system registers that
were:
- part of a feature FEAT_X with no corresponding command line extension;
- introduced in a newer architecture version ArmvX.Z;
- permitted to be implemented from an earlier version ArmvX.Y.
Previously these system registers tended to be gated on ArmvX.Z or left
ungated, but following the above principle they are now gated on ArmvX.Y
instead.
Most support for CSRE was removed from Binutils in 2021 after it was
removed from the architecture. This patch removes the remaining system
registers and test files.
Remove all test cases that expect spmzr_el0 to be readable, and remove
some redundant default macro values from armv9_5-a-sysregs.s while we're
there.
Add a read of spmzr_el0 to sysreg-diagnostics.s. This turns out to be
the first test for the "reading from a write-only register" note.
Also remove the recently added -menable-sysreg-checking option from this
test, both to simplify the addition of spmzr_el0 to the test, and to
verify that read/write diagnostics don't depend on that option.
The flag is unnecessary, because we can just unconditionally check the
features field every time. Having the information duplicated in two
separate fields makes it harder to maintain, particularly in the context
of the upcoming regating patch.
The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now
unused, so remove that as well.
The opcode D6 has been officially reserved as a single-byte permanent
undefined (#UD) opcode in 64-bit mode with the mnemonic UDB. This is
already the behavior of all known 64-bit implementations; this is thus
merely an official statement of forward compatibility and the
assignment of a mnemonic.
This will be documented in the next version of the Intel Software
Developer's Manual; in the meantime I DO speak officially for Intel on
this issue.
The x86 Advisory Council has ratified this decision, and so it is
expected to be honored across vendors, but I obviously cannot make any
official statement on any other vendor's behalf.
I am covered by the Intel-FSF copyright assignment for binutils.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
I made a stupid mistake in the commit 28520d7, allow to assemble slli/srli/srai
with 0 immediate to hint c.slli/c.srli/c.srai. These hints will be regared as
illegal instruction for gdb and qemu, so at least I got following gcc testcases
failed,
=== g++: Unexpected fails for rv64gc lp64d medlow ===
FAIL: c-c++-common/torture/builtin-arith-overflow-17.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-6.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-p-17.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-p-6.c -O0 execution test
=== gfortran: Unexpected fails for rv64gc lp64d medlow ===
FAIL: gfortran.dg/leadz_trailz_2.f90 -O0 execution test
=== gcc: Unexpected fails for rv64gc lp64d medlow ===
FAIL: c-c++-common/torture/builtin-arith-overflow-17.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-6.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-p-17.c -O0 execution test
FAIL: c-c++-common/torture/builtin-arith-overflow-p-6.c -O0 execution test
So we should just allow c.slli/c.srli/c.srai with zero immediate as hints, but
don't allow slli/srli/srai with zero immediate.
gas/
PR 33216
* testsuite/gas/riscv/c-zero-imm.d: Only allow c.slli/c.srli/c.srai
with zero immediate as hints, but don't allow slli/srli/srai with
zero immediate.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
opcodes/
PR 33216
* riscv-opc.c (match_slli_as_c_slli): Added back.
(match_srxi_as_c_srxi): Likewise.
(riscv_opcodes): Only allow c.slli/c.srli/c.srai with zero immediate
as hints, but don't allow slli/srli/srai with zero immediate.
The original patch,
e6f372ba66
Since recently c.slli64, c.srai64, and c.srli64 have been removed from the
riscv-isa-manual, c.slli, c.srli, and c.srai with 0 immediate are now listed
as hints,
https://github.com/riscv/riscv-isa-manual/pull/1942 and https://github.com/riscv/riscv-isa-manual/pull/2093
So allow c.slli, c.srli, and c.srai with 0 immediate as a hint. Also allow to
assemble slli, srli and srai with 0 immediate to hint c.slli, c.srli and c.srai
when rvc is enabled. The c.slli64, c.srai64, and c.srli64 should be kept as
aliases, so dis-assembler should disassemble to c.slli, c.srli, and c.srai with
0 immediate.
Passed rv32/64-elf/linux binutils testcases.
gas/
PR 33216
* testsuite/gas/riscv/c-zero-imm.d: Updated since allow c.slli64,
c.srai64, and c.srli64 with 0 immediate as a hint.
* testsuite/gas/riscv/c-zero-imm.s: Likewise.
* testsuite/gas/riscv/zca.d: Likewise.
opcodes/
PR 33216
* riscv-opc.c (riscv_opcodes): Updated since allow c.slli64, c.srai64,
and c.srli64 with 0 immediate as a hint.
With the tables no longer being part of libopcodes (but rather being
compiled directly into gas), this table doesn't need exposing anymore.
The declaration cannot be avoided, though, as the first use of the
array sits ahead of its definition (in i386-tbl.h).
There's no reason to allow the array to be modifiable. In fact the
compiler is able to infer this, placing the array in .data.rel.ro, but
let's make it explicit.
Merge them into a single array of struct type. There's further no reason
to have the compiler materialize such objects on the stack. And there's
also no reason to allow the array(s) to be modifiable. Finally, given
how short the strings are, there's little point using more space to
store pointers to them (on 64-bit hosts; the situation is a little
better on 32-bit ones).
While there also correct indentation in adjacent code, and avoid open-
coding ARRAY_SIZE().
