mirror of
https://github.com/bminor/binutils-gdb.git
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x86: Disable AMX-TRANSPOSE by default
In Binutils, we choose to keep the AMX-TRANSPOSE support for now in case there are vendors want to utilize the instructions although the feature itself is de-published. AMX-TRANSPOSE will not show up on any Intel/AMD hardware. Also in foreseeable future, no hardware will support AMX-TRANSPOSE, we will disable it by default. gas/ChangeLog: * testsuite/gas/i386/x86-64-amx-movrs-intel.d: Move AMX-TRANSPOSE part to AMX-TRANSPOSE test. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Move AMX-TRANSPOSE part to AMX-TRANSPOSE file. Remove noamx_transpose test. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: Add AMX-MOVRS and AMX-TF32 related test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. * testsuite/gas/i386/x86-64.exp: Remove AMX-MOVRS invalid test. * testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d: New test originally comes from APX_F test. * testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-apx.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-apx.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Disable AMX-TRANSPOSE by default. * i386-init.h: Regenerated.
This commit is contained in:
Haochen Jiang
@@ -8,14 +8,6 @@ Disassembly of section \.text:
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#...
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[a-f0-9]+ <_intel>:
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\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs tmm6,\[rbp\+r14\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs tmm2,\[r9\+riz\*1\]
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\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 tmm2,\[r9\+riz\*1\]
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\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs tmm6,\[rbp\+r14\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs tmm2,\[r9\+riz\*1\]
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\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 tmm2,\[r9\+riz\*1\]
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\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs tmm6,\[rbp\+r14\*8\+0x10000000\]
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\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs tmm3,\[r9\+riz\*1\]
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\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
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@@ -1,13 +0,0 @@
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.* Assembler messages:
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.*:5: Error: `\(%rip\)' cannot be used here
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.*:6: Error: `\(%rip\)' cannot be used here
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.*:7: Error: `\(%rip\)' cannot be used here
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.*:8: Error: `\(%rip\)' cannot be used here
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.*:9: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
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.*:10: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
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.*:11: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
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.*:12: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
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.*:16: Error: `t2rpntlvwz0rs' is not supported on `x86_64.noamx_transpose'
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.*:17: Error: `t2rpntlvwz0rst1' is not supported on `x86_64.noamx_transpose'
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.*:18: Error: `t2rpntlvwz1rs' is not supported on `x86_64.noamx_transpose'
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.*:19: Error: `t2rpntlvwz1rst1' is not supported on `x86_64.noamx_transpose'
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@@ -1,19 +0,0 @@
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# Check Invalid 64bit AMX-MOVRS instructions
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.text
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_start:
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t2rpntlvwz0rs (%rip), %tmm2
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t2rpntlvwz0rst1 (%rip), %tmm2
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t2rpntlvwz1rs (%rip), %tmm2
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t2rpntlvwz1rst1 (%rip), %tmm2
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t2rpntlvwz0rs (%r9), %tmm1
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t2rpntlvwz0rst1 (%r9), %tmm3
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t2rpntlvwz1rs (%r9), %tmm5
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t2rpntlvwz1rst1 (%r9), %tmm7
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.arch .noamx_transpose
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_transpose:
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t2rpntlvwz0rs (%r9), %tmm2
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t2rpntlvwz0rst1 (%r9), %tmm2
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t2rpntlvwz1rs (%r9), %tmm2
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t2rpntlvwz1rst1 (%r9), %tmm2
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@@ -6,14 +6,6 @@
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs 0x10000000\(%rbp,%r14,8\),%tmm6
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\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs \(%r9,%riz,1\),%tmm2
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\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 0x10000000\(%rbp,%r14,8\),%tmm6
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\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 \(%r9,%riz,1\),%tmm2
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\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs 0x10000000\(%rbp,%r14,8\),%tmm6
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\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs \(%r9,%riz,1\),%tmm2
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\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 0x10000000\(%rbp,%r14,8\),%tmm6
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\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 \(%r9,%riz,1\),%tmm2
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\s*[a-f0-9]+:\s*c4 a2 7b 4a b4 f5 00 00 00 10\s+tileloaddrs 0x10000000\(%rbp,%r14,8\),%tmm6
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\s*[a-f0-9]+:\s*c4 c2 7b 4a 1c 21\s+tileloaddrs \(%r9,%riz,1\),%tmm3
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\s*[a-f0-9]+:\s*c4 a2 79 4a b4 f5 00 00 00 10\s+tileloaddrst1 0x10000000\(%rbp,%r14,8\),%tmm6
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@@ -2,14 +2,6 @@
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.text
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_start:
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t2rpntlvwz0rs 0x10000000(%rbp, %r14, 8), %tmm6
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t2rpntlvwz0rs (%r9), %tmm2
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t2rpntlvwz0rst1 0x10000000(%rbp, %r14, 8), %tmm6
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t2rpntlvwz0rst1 (%r9), %tmm2
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t2rpntlvwz1rs 0x10000000(%rbp, %r14, 8), %tmm6
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t2rpntlvwz1rs (%r9), %tmm2
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t2rpntlvwz1rst1 0x10000000(%rbp, %r14, 8), %tmm6
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t2rpntlvwz1rst1 (%r9), %tmm2
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tileloaddrs 0x10000000(%rbp, %r14, 8), %tmm6
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tileloaddrs (%r9), %tmm3
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tileloaddrst1 0x10000000(%rbp, %r14, 8), %tmm6
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@@ -17,14 +9,6 @@ _start:
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_intel:
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.intel_syntax noprefix
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t2rpntlvwz0rs tmm6, [rbp+r14*8+0x10000000]
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t2rpntlvwz0rs tmm2, [r9]
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t2rpntlvwz0rst1 tmm6, [rbp+r14*8+0x10000000]
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t2rpntlvwz0rst1 tmm2, [r9]
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t2rpntlvwz1rs tmm6, [rbp+r14*8+0x10000000]
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t2rpntlvwz1rs tmm2, [r9]
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t2rpntlvwz1rst1 tmm6, [rbp+r14*8+0x10000000]
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t2rpntlvwz1rst1 tmm2, [r9]
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tileloaddrs tmm6, [rbp+r14*8+0x10000000]
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tileloaddrs tmm3, [r9]
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tileloaddrst1 tmm6, [rbp+r14*8+0x10000000]
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@@ -10,7 +10,4 @@ Disassembly of section \.text:
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\s*[a-f0-9]+:\s*c4 e2 71 48 d1\s+tmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
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\s*[a-f0-9]+:\s*c4 e2 69 48 c9\s+tmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
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\s*[a-f0-9]+:\s*c4 e2 71 48 ca\s+tmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1\/\(bad\)
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\s*[a-f0-9]+:\s*c4 e2 70 48 d1\s+ttmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
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\s*[a-f0-9]+:\s*c4 e2 68 48 c9\s+ttmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
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\s*[a-f0-9]+:\s*c4 e2 70 48 ca\s+ttmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
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#pass
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@@ -7,12 +7,3 @@
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# tmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
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.insn VEX.128.66.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
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# ttmmultf32ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
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.insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm1, %tmm2
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# ttmmultf32ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
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.insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm2, %tmm1
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# ttmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
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.insn VEX.128.NP.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
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@@ -10,6 +10,4 @@ Disassembly of section \.text:
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[a-f0-9]+ <_intel>:
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\s*[a-f0-9]+:\s*c4 e2 59 48 f5\s+tmmultf32ps tmm6,tmm5,tmm4
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\s*[a-f0-9]+:\s*c4 e2 71 48 da\s+tmmultf32ps tmm3,tmm2,tmm1
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\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps tmm6,tmm5,tmm4
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\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps tmm3,tmm2,tmm1
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#pass
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@@ -2,6 +2,3 @@
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.*:5: Error: all tmm registers must be distinct for `tmmultf32ps'
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.*:6: Error: all tmm registers must be distinct for `tmmultf32ps'
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.*:7: Error: all tmm registers must be distinct for `tmmultf32ps'
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.*:8: Error: all tmm registers must be distinct for `ttmmultf32ps'
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.*:9: Error: all tmm registers must be distinct for `ttmmultf32ps'
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.*:10: Error: all tmm registers must be distinct for `ttmmultf32ps'
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@@ -5,6 +5,3 @@ _start:
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tmmultf32ps %tmm1, %tmm1, %tmm2
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tmmultf32ps %tmm1, %tmm2, %tmm1
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tmmultf32ps %tmm2, %tmm1, %tmm1
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ttmmultf32ps %tmm1, %tmm1, %tmm2
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ttmmultf32ps %tmm1, %tmm2, %tmm1
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ttmmultf32ps %tmm2, %tmm1, %tmm1
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@@ -8,6 +8,4 @@ Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 e2 59 48 f5\s+tmmultf32ps %tmm4,%tmm5,%tmm6
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\s*[a-f0-9]+:\s*c4 e2 71 48 da\s+tmmultf32ps %tmm1,%tmm2,%tmm3
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\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps %tmm4,%tmm5,%tmm6
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\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps %tmm1,%tmm2,%tmm3
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#pass
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@@ -4,12 +4,8 @@
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_start:
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tmmultf32ps %tmm4, %tmm5, %tmm6
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tmmultf32ps %tmm1, %tmm2, %tmm3
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ttmmultf32ps %tmm4, %tmm5, %tmm6
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ttmmultf32ps %tmm1, %tmm2, %tmm3
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_intel:
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.intel_syntax noprefix
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tmmultf32ps tmm6, tmm5, tmm4
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tmmultf32ps tmm3, tmm2, tmm1
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ttmmultf32ps tmm6, tmm5, tmm4
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ttmmultf32ps tmm3, tmm2, tmm1
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19
gas/testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d
Normal file
19
gas/testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d
Normal file
@@ -0,0 +1,19 @@
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#objdump: -dw -Mintel
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#name: x86_64 AMX_TRANSPOSE APX_F EVEX-Promoted insns (Intel disassembly)
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#source: x86-64-amx-transpose-apx.s
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.*: +file format .*
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Disassembly of section \.text:
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#...
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[a-f0-9]+ <_intel>:
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
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#pass
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19
gas/testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d
Normal file
19
gas/testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d
Normal file
@@ -0,0 +1,19 @@
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#as: -mevexwig=1
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#objdump: -dw
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#name: x86_64 AMX_TRANSPOSE APX_F EVEX-Promoted insns w/ -mevexwig=1
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#source: x86-64-amx-transpose-apx.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
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[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
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#pass
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17
gas/testsuite/gas/i386/x86-64-amx-transpose-apx.d
Normal file
17
gas/testsuite/gas/i386/x86-64-amx-transpose-apx.d
Normal file
@@ -0,0 +1,17 @@
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#objdump: -dw
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#name: x86_64 APX_F EVEX-Promoted insns
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.*: +file format .*
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||||
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Disassembly of section \.text:
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||||
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||||
0+ <_start>:
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[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
#pass
|
||||
23
gas/testsuite/gas/i386/x86-64-amx-transpose-apx.s
Normal file
23
gas/testsuite/gas/i386/x86-64-amx-transpose-apx.s
Normal file
@@ -0,0 +1,23 @@
|
||||
# Check 64bit AMX-TRANSPOSE APX_F EVEX-Promoted instructions.
|
||||
|
||||
.arch .amx_transpose
|
||||
.text
|
||||
_start:
|
||||
t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6
|
||||
|
||||
_intel:
|
||||
t2rpntlvwz0 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0rs tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1rs tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123]
|
||||
@@ -13,5 +13,8 @@ Disassembly of section \.text:
|
||||
\s*[a-f0-9]+:\s*c4 e2 73 6c d1\s+ttdpfp16ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 e2 6b 6c c9\s+ttdpfp16ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
|
||||
\s*[a-f0-9]+:\s*c4 e2 73 6c ca\s+ttdpfp16ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 48 d1\s+ttmmultf32ps %tmm1/\(bad\),%tmm1/\(bad\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 e2 68 48 c9\s+ttmmultf32ps %tmm2,%tmm1/\(bad\),%tmm1/\(bad\)
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 48 ca\s+ttmmultf32ps %tmm1/\(bad\),%tmm2,%tmm1/\(bad\)
|
||||
#pass
|
||||
|
||||
|
||||
@@ -16,3 +16,12 @@
|
||||
|
||||
# ttdpfp16ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
|
||||
.insn VEX.128.f2.0F38.W0 0x6c, %tmm2, %tmm1, %tmm1
|
||||
|
||||
# ttmmultf32ps %tmm1, %tmm1, %tmm2 all tmm registers should be distinct
|
||||
.insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm1, %tmm2
|
||||
|
||||
# ttmmultf32ps %tmm1, %tmm2, %tmm1 all tmm registers should be distinct
|
||||
.insn VEX.128.NP.0F38.W0 0x48, %tmm1, %tmm2, %tmm1
|
||||
|
||||
# ttmmultf32ps %tmm2, %tmm1, %tmm1 all tmm registers should be distinct
|
||||
.insn VEX.128.NP.0F38.W0 0x48, %tmm2, %tmm1, %tmm1
|
||||
|
||||
@@ -22,6 +22,14 @@ Disassembly of section \.text:
|
||||
\s*[a-f0-9]+:\s*c4 c2 79 6e 14 21\s+t2rpntlvwz1 tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 a2 79 6f b4 f5 00 00 00 10\s+t2rpntlvwz1t1 tmm6,\[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c2 79 6f 14 21\s+t2rpntlvwz1t1 tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs tmm6,\[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs tmm6,\[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 tmm6,\[rbp\+r14\*8\+0x10000000\]
|
||||
\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 tmm2,\[r9\+riz\*1\]
|
||||
\s*[a-f0-9]+:\s*c4 e2 58 6b f5\s+tconjtcmmimfp16ps tmm6,tmm5,tmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 6b da\s+tconjtcmmimfp16ps tmm3,tmm2,tmm1
|
||||
\s*[a-f0-9]+:\s*c4 e2 79 6b f5\s+tconjtfp16 tmm6,tmm5
|
||||
@@ -30,4 +38,6 @@ Disassembly of section \.text:
|
||||
\s*[a-f0-9]+:\s*c4 e2 73 6b da\s+ttcmmimfp16ps tmm3,tmm2,tmm1
|
||||
\s*[a-f0-9]+:\s*c4 e2 5a 6b f5\s+ttcmmrlfp16ps tmm6,tmm5,tmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 72 6b da\s+ttcmmrlfp16ps tmm3,tmm2,tmm1
|
||||
\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps tmm6,tmm5,tmm4
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps tmm3,tmm2,tmm1
|
||||
#pass
|
||||
|
||||
@@ -1,15 +1,31 @@
|
||||
.* Assembler messages:
|
||||
.*:5: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:6: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:7: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:8: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:9: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:10: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:11: Error: `\(%rip\)' cannot be used here
|
||||
.*:12: Error: `\(%rip\)' cannot be used here
|
||||
.*:13: Error: `\(%rip\)' cannot be used here
|
||||
.*:14: Error: `\(%rip\)' cannot be used here
|
||||
.*:15: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
|
||||
.*:16: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
|
||||
.*:17: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
|
||||
.*:18: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
|
||||
.*:5: Error: `t2rpntlvwz0rs' is not supported on `x86_64'
|
||||
.*:6: Error: `t2rpntlvwz0rst1' is not supported on `x86_64'
|
||||
.*:7: Error: `t2rpntlvwz1rs' is not supported on `x86_64'
|
||||
.*:8: Error: `t2rpntlvwz1rst1' is not supported on `x86_64'
|
||||
.*:9: Error: `ttmmultf32ps' is not supported on `x86_64'
|
||||
.*:13: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:14: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:15: Error: all tmm registers must be distinct for `ttdpbf16ps'
|
||||
.*:16: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:17: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:18: Error: all tmm registers must be distinct for `ttdpfp16ps'
|
||||
.*:19: Error: all tmm registers must be distinct for `ttmmultf32ps'
|
||||
.*:20: Error: all tmm registers must be distinct for `ttmmultf32ps'
|
||||
.*:21: Error: all tmm registers must be distinct for `ttmmultf32ps'
|
||||
.*:22: Error: `\(%rip\)' cannot be used here
|
||||
.*:23: Error: `\(%rip\)' cannot be used here
|
||||
.*:24: Error: `\(%rip\)' cannot be used here
|
||||
.*:25: Error: `\(%rip\)' cannot be used here
|
||||
.*:26: Error: `\(%rip\)' cannot be used here
|
||||
.*:27: Error: `\(%rip\)' cannot be used here
|
||||
.*:28: Error: `\(%rip\)' cannot be used here
|
||||
.*:29: Error: `\(%rip\)' cannot be used here
|
||||
.*:30: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
|
||||
.*:31: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
|
||||
.*:32: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
|
||||
.*:33: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
|
||||
.*:34: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
|
||||
.*:35: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
|
||||
.*:36: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
|
||||
.*:37: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
|
||||
|
||||
@@ -2,17 +2,36 @@
|
||||
|
||||
.text
|
||||
_start:
|
||||
t2rpntlvwz0rs (%r9), %tmm2
|
||||
t2rpntlvwz0rst1 (%r9), %tmm2
|
||||
t2rpntlvwz1rs (%r9), %tmm2
|
||||
t2rpntlvwz1rst1 (%r9), %tmm2
|
||||
ttmmultf32ps %tmm1, %tmm2, %tmm3
|
||||
|
||||
.arch .amx_transpose
|
||||
_transpose:
|
||||
ttdpbf16ps %tmm1, %tmm1, %tmm2
|
||||
ttdpbf16ps %tmm1, %tmm2, %tmm1
|
||||
ttdpbf16ps %tmm2, %tmm1, %tmm1
|
||||
ttdpfp16ps %tmm1, %tmm1, %tmm2
|
||||
ttdpfp16ps %tmm1, %tmm2, %tmm1
|
||||
ttdpfp16ps %tmm2, %tmm1, %tmm1
|
||||
ttmmultf32ps %tmm1, %tmm1, %tmm2
|
||||
ttmmultf32ps %tmm1, %tmm2, %tmm1
|
||||
ttmmultf32ps %tmm2, %tmm1, %tmm1
|
||||
t2rpntlvwz0 (%rip), %tmm2
|
||||
t2rpntlvwz0t1 (%rip), %tmm2
|
||||
t2rpntlvwz1 (%rip), %tmm2
|
||||
t2rpntlvwz1t1 (%rip), %tmm2
|
||||
t2rpntlvwz0rs (%rip), %tmm2
|
||||
t2rpntlvwz0rst1 (%rip), %tmm2
|
||||
t2rpntlvwz1rs (%rip), %tmm2
|
||||
t2rpntlvwz1rst1 (%rip), %tmm2
|
||||
t2rpntlvwz0 (%r9), %tmm1
|
||||
t2rpntlvwz0t1 (%r9), %tmm3
|
||||
t2rpntlvwz1 (%r9), %tmm5
|
||||
t2rpntlvwz1t1 (%r9), %tmm7
|
||||
t2rpntlvwz0rs (%r9), %tmm1
|
||||
t2rpntlvwz0rst1 (%r9), %tmm3
|
||||
t2rpntlvwz1rs (%r9), %tmm5
|
||||
t2rpntlvwz1rst1 (%r9), %tmm7
|
||||
|
||||
@@ -20,6 +20,14 @@ Disassembly of section \.text:
|
||||
\s*[a-f0-9]+:\s*c4 c2 79 6e 14 21\s+t2rpntlvwz1 \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 a2 79 6f b4 f5 00 00 00 10\s+t2rpntlvwz1t1 0x10000000\(%rbp,%r14,8\),%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 c2 79 6f 14 21\s+t2rpntlvwz1t1 \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 a5 78 f8 b4 f5 00 00 00 10\s+t2rpntlvwz0rs 0x10000000\(%rbp,%r14,8\),%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 c5 78 f8 14 21\s+t2rpntlvwz0rs \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 a5 78 f9 b4 f5 00 00 00 10\s+t2rpntlvwz0rst1 0x10000000\(%rbp,%r14,8\),%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 c5 78 f9 14 21\s+t2rpntlvwz0rst1 \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 a5 79 f8 b4 f5 00 00 00 10\s+t2rpntlvwz1rs 0x10000000\(%rbp,%r14,8\),%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 c5 79 f8 14 21\s+t2rpntlvwz1rs \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 a5 79 f9 b4 f5 00 00 00 10\s+t2rpntlvwz1rst1 0x10000000\(%rbp,%r14,8\),%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 c5 79 f9 14 21\s+t2rpntlvwz1rst1 \(%r9,%riz,1\),%tmm2
|
||||
\s*[a-f0-9]+:\s*c4 e2 58 6b f5\s+tconjtcmmimfp16ps %tmm4,%tmm5,%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 6b da\s+tconjtcmmimfp16ps %tmm1,%tmm2,%tmm3
|
||||
\s*[a-f0-9]+:\s*c4 e2 79 6b f5\s+tconjtfp16 %tmm5,%tmm6
|
||||
@@ -28,4 +36,6 @@ Disassembly of section \.text:
|
||||
\s*[a-f0-9]+:\s*c4 e2 73 6b da\s+ttcmmimfp16ps %tmm1,%tmm2,%tmm3
|
||||
\s*[a-f0-9]+:\s*c4 e2 5a 6b f5\s+ttcmmrlfp16ps %tmm4,%tmm5,%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 72 6b da\s+ttcmmrlfp16ps %tmm1,%tmm2,%tmm3
|
||||
\s*[a-f0-9]+:\s*c4 e2 58 48 f5\s+ttmmultf32ps %tmm4,%tmm5,%tmm6
|
||||
\s*[a-f0-9]+:\s*c4 e2 70 48 da\s+ttmmultf32ps %tmm1,%tmm2,%tmm3
|
||||
#pass
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
# Check 64bit AMX-TRANSPOSE instructions
|
||||
|
||||
.arch .amx_transpose
|
||||
.text
|
||||
_start:
|
||||
ttdpbf16ps %tmm4, %tmm5, %tmm6
|
||||
@@ -16,6 +17,14 @@ _start:
|
||||
t2rpntlvwz1 (%r9), %tmm2
|
||||
t2rpntlvwz1t1 0x10000000(%rbp, %r14, 8), %tmm6
|
||||
t2rpntlvwz1t1 (%r9), %tmm2
|
||||
t2rpntlvwz0rs 0x10000000(%rbp, %r14, 8), %tmm6
|
||||
t2rpntlvwz0rs (%r9), %tmm2
|
||||
t2rpntlvwz0rst1 0x10000000(%rbp, %r14, 8), %tmm6
|
||||
t2rpntlvwz0rst1 (%r9), %tmm2
|
||||
t2rpntlvwz1rs 0x10000000(%rbp, %r14, 8), %tmm6
|
||||
t2rpntlvwz1rs (%r9), %tmm2
|
||||
t2rpntlvwz1rst1 0x10000000(%rbp, %r14, 8), %tmm6
|
||||
t2rpntlvwz1rst1 (%r9), %tmm2
|
||||
tconjtcmmimfp16ps %tmm4, %tmm5, %tmm6
|
||||
tconjtcmmimfp16ps %tmm1, %tmm2, %tmm3
|
||||
tconjtfp16 %tmm5, %tmm6
|
||||
@@ -24,6 +33,8 @@ _start:
|
||||
ttcmmimfp16ps %tmm1, %tmm2, %tmm3
|
||||
ttcmmrlfp16ps %tmm4, %tmm5, %tmm6
|
||||
ttcmmrlfp16ps %tmm1, %tmm2, %tmm3
|
||||
ttmmultf32ps %tmm4, %tmm5, %tmm6
|
||||
ttmmultf32ps %tmm1, %tmm2, %tmm3
|
||||
|
||||
_intel:
|
||||
.intel_syntax noprefix
|
||||
@@ -41,6 +52,14 @@ _intel:
|
||||
t2rpntlvwz1 tmm2, [r9]
|
||||
t2rpntlvwz1t1 tmm6, [rbp+r14*8+0x10000000]
|
||||
t2rpntlvwz1t1 tmm2, [r9]
|
||||
t2rpntlvwz0rs tmm6, [rbp+r14*8+0x10000000]
|
||||
t2rpntlvwz0rs tmm2, [r9]
|
||||
t2rpntlvwz0rst1 tmm6, [rbp+r14*8+0x10000000]
|
||||
t2rpntlvwz0rst1 tmm2, [r9]
|
||||
t2rpntlvwz1rs tmm6, [rbp+r14*8+0x10000000]
|
||||
t2rpntlvwz1rs tmm2, [r9]
|
||||
t2rpntlvwz1rst1 tmm6, [rbp+r14*8+0x10000000]
|
||||
t2rpntlvwz1rst1 tmm2, [r9]
|
||||
tconjtcmmimfp16ps tmm6, tmm5, tmm4
|
||||
tconjtcmmimfp16ps tmm3, tmm2, tmm1
|
||||
tconjtfp16 tmm6, tmm5
|
||||
@@ -49,3 +68,5 @@ _intel:
|
||||
ttcmmimfp16ps tmm3, tmm2, tmm1
|
||||
ttcmmrlfp16ps tmm6, tmm5, tmm4
|
||||
ttcmmrlfp16ps tmm3, tmm2, tmm1
|
||||
ttmmultf32ps tmm6, tmm5, tmm4
|
||||
ttmmultf32ps tmm3, tmm2, tmm1
|
||||
|
||||
@@ -139,14 +139,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
|
||||
@@ -286,14 +278,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+r11,r15,r31
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+r15,QWORD PTR \[r31\+rax\*4\+0x123\],r31
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+\[r31\+rax\*4\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1 tmm6,\[r31\+rax\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd tmm6,\[r31\+rax\*4\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+tmm6,\[rbp\+r31\*8\+0x10000000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+tmm3,\[r16\+riz\*1\]
|
||||
|
||||
@@ -139,14 +139,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
|
||||
@@ -286,14 +278,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
|
||||
|
||||
@@ -139,14 +139,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
|
||||
@@ -286,14 +278,6 @@ Disassembly of section \.text:
|
||||
[ ]*[a-f0-9]+:[ ]*62 52 87 00 f7 df[ ]+shrx[ ]+%r31,%r15,%r11
|
||||
[ ]*[a-f0-9]+:[ ]*62 5a 87 00 f7 bc 87 23 01 00 00[ ]+shrx[ ]+%r31,0x123\(%r31,%rax,4\),%r15
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 49 84 87 23 01 00 00[ ]+sttilecfg[ ]+0x123\(%r31,%rax,4\)
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz0[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7c 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz0rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7c 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz0t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6e b4 c7 23 01 00 00[ ]+t2rpntlvwz1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f8 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rs[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 dd 7d 08 f9 b4 c7 23 01 00 00[ ]+t2rpntlvwz1rst1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7d 08 6f b4 c7 23 01 00 00[ ]+t2rpntlvwz1t1[ ]+0x123\(%r31,%rax,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 da 7f 08 4b b4 87 23 01 00 00[ ]+tileloadd[ ]+0x123\(%r31,%rax,4\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 b2 7b 08 4a b4 fd 00 00 00 10[ ]+tileloaddrs[ ]+0x10000000\(%rbp,%r31,8\),%tmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 fa 7f 08 4a 1c 20[ ]+tileloaddrs[ ]+\(%r16,%riz,1\),%tmm3
|
||||
|
||||
@@ -133,14 +133,6 @@ _start:
|
||||
shrx %r31,%r15,%r11
|
||||
shrx %r31,0x123(%r31,%rax,4),%r15
|
||||
sttilecfg 0x123(%r31,%rax,4)
|
||||
t2rpntlvwz0 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0rs 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0rst1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz0t1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1rs 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1rst1 0x123(%r31,%rax,8),%tmm6
|
||||
t2rpntlvwz1t1 0x123(%r31,%rax,8),%tmm6
|
||||
tileloadd 0x123(%r31,%rax,4),%tmm6
|
||||
tileloaddrs 0x10000000(%rbp, %r31, 8), %tmm6
|
||||
tileloaddrs (%r16), %tmm3
|
||||
@@ -282,14 +274,6 @@ _start:
|
||||
shrx r11,r15,r31
|
||||
shrx r15,QWORD PTR [r31+rax*4+0x123],r31
|
||||
sttilecfg [r31+rax*4+0x123]
|
||||
t2rpntlvwz0 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0rs tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0rst1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz0t1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1rs tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1rst1 tmm6,[r31+rax*8+0x123]
|
||||
t2rpntlvwz1t1 tmm6,[r31+rax*8+0x123]
|
||||
tileloadd tmm6,[r31+rax*4+0x123]
|
||||
tileloaddrs tmm6, [rbp+r31*8+0x10000000]
|
||||
tileloaddrs tmm3, [r16]
|
||||
|
||||
@@ -534,7 +534,6 @@ run_list_test "x86-64-amx-fp8-inval"
|
||||
run_dump_test "x86-64-amx-fp8-bad"
|
||||
run_dump_test "x86-64-amx-movrs"
|
||||
run_dump_test "x86-64-amx-movrs-intel"
|
||||
run_list_test "x86-64-amx-movrs-inval"
|
||||
run_dump_test "x86-64-amx-avx512"
|
||||
run_dump_test "x86-64-amx-avx512-intel"
|
||||
run_dump_test "x86-64-movrs"
|
||||
|
||||
@@ -47,7 +47,7 @@ typedef struct dependency
|
||||
static const dependency isa_dependencies[] =
|
||||
{
|
||||
{ "UNKNOWN",
|
||||
"~(IAMCU|MPX)" },
|
||||
"~(IAMCU|MPX|AMX_TRANSPOSE)" },
|
||||
{ "GENERIC32",
|
||||
"386" },
|
||||
{ "GENERIC64",
|
||||
|
||||
@@ -1596,7 +1596,7 @@
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
|
||||
Reference in New Issue
Block a user