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aarch64: gas: Allow movprfx with fmmla and bfscale [PR gas/33562]

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These instructions were previously incorrectly marked as not accepting
movprfx.  Fix this and add tests.

	PR gas/33562

opcodes:
	* aarch64-tbl.h: Update widening fmmmla and bfscale instructions.
gas:
	* testsuite/gas/aarch64/f8f16mm_sve2-bad.l: Update test with movprfx.
	* testsuite/gas/aarch64/f8f16mm_sve2.d: Ditto.
	* testsuite/gas/aarch64/f8f16mm_sve2.s: Ditto.
	* testsuite/gas/aarch64/f8f32mm_sve2-bad.l: Ditto.
	* testsuite/gas/aarch64/f8f32mm_sve2.d: Ditto.
	* testsuite/gas/aarch64/f8f32mm_sve2.s: Ditto.
	* testsuite/gas/aarch64/sve-f16f32mm-bad.l: Ditto.
	* testsuite/gas/aarch64/sve-f16f32mm.d: Ditto.
	* testsuite/gas/aarch64/sve-f16f32mm.s: Ditto.
	* testsuite/gas/aarch64/sve-bfscale-sve2.s: Ditto.
	* testsuite/gas/aarch64/sve-bfscale-sve2.d: Ditto.

Approved-By: Alice Carlotti <alice.carlotti@arm.com>
This commit is contained in:
Alfie Richards
2025-10-23 09:45:22 +00:00
committed by Alice Carlotti
parent 2006dea18d
commit facb933805
12 changed files with 235 additions and 13 deletions
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26
opcodes/aarch64-tbl.h
View File

@@ -3260,16 +3260,16 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SME2p1, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL }
#define SVE_F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE_F16F32MM, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL }
#define F8F32MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F32MM, OPS, QUALS, FLAGS, 0, 0, NULL }
#define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL }
#define F8F32MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F32MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL }
#define F8F16MM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F16MM, OPS, QUALS, FLAGS, 0, 0, NULL }
#define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL }
#define F8F16MM_SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS) \
{ NAME, OPCODE, MASK, CLASS, OP, F8F16MM_SVE2, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, 0, NULL }
#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
FLAGS | F_STRICT | F_INVALID_IMM_SYMS_2, CONSTRAINTS, TIED, NULL }
@@ -3336,11 +3336,11 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE_BFSCALE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE, OPS, QUALS, FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
#define SVE_BFSCALE_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SVE_BFSCALE_SME2, OPS, QUALS, FLAGS | F_STRICT, 0, TIED, NULL }
#define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
#define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \
CONSTRAINTS, TIED, NULL }
#define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -6768,7 +6768,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0),
/* SVE_BFSCALE instructions. */
SVE_BFSCALE_INSN ("bfscale", 0x65098000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, 2),
SVE_BFSCALE_INSN ("bfscale", 0x65098000, 0xffffe000, sve_misc, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_HMHH, 0, C_SCAN_MOVPRFX, 2),
SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120a180, 0xfff0ffe1, sme_misc, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_H, 0, 1),
SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120a980, 0xfff0ffe3, sme_misc, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_H, 0, 1),
SVE_BFSCALE_SME2_INSN ("bfscale", 0xc120b180, 0xffe1ffe1, sme_misc, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_H, 0, 1),
@@ -6979,13 +6979,13 @@ const struct aarch64_opcode aarch64_opcode_table[] =
BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0),
/* SVE_F16F32 Matrix Multiply-Accumulate. */
SVE_F16F32MM_INSN ("fmmla", 0x6420e400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0),
SVE_F16F32MM_INSN ("fmmla", 0x6420e400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX),
/* F8F32 Matrix Multiply-Accumulate. */
F8F32MM_INSN ("fmmla", 0x6e80ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FMLL4S, 0),
F8F32MM_SVE2_INSN ("fmmla", 0x6420e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0),
F8F32MM_SVE2_INSN ("fmmla", 0x6420e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX),
/* F8F16 Matrix Multiply-Accumulate. */
F8F16MM_INSN ("fmmla", 0x6e00ec00, 0xffe0fc00, asimdmisc, 0, OP3 (Vd, Vn, Vm), QL_V3FML8H, 0),
F8F16MM_SVE2_INSN ("fmmla", 0x6460e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0),
F8F16MM_SVE2_INSN ("fmmla", 0x6460e000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX),
/* cpyfp cpyfprn cpyfpwn cpyfpn
cpyfm cpyfmrn cpyfmwn cpyfmn