Before altering how build_modrm_byte() works, arrange for this part of
the testcase to actually use distinguishable source and destination
register numbers, such that incorrect propagation of, in particular, the
high bit encodings (from REX to VEX) can be noticed (in turn
specifically assertions [not] triggering in the respective code).
In the course of using the upcoming .insn directive to eliminate various
.byte uses in testcases I've come across these, which needlessly use
more .byte than necessary even without the availability of .insn.
As 1fafeaac85, "line.s" and "Line.s" are
identical in case insensitive file systems. Thus, gas doesn't trigger
an input file switch.
gas/ChangeLog:
* testsuite/gas/elf/dwarf-5-macro.s: Change Line.s to Line2.s.
Several insns have a (typically shorter) non-ModR/M and a (typically
longer) ModR/M encoding. In most cases the former is used by default.
This isn't too dissimilar from register-only insns sometimes having two
encoding forms. In those cases {load} or {store} can be used to control
the encoding used. Extend this to ModR/M-less encodings which have a
ModR/M counterpart (note that BSWAP hasn't). For insn reading and
writing their (explicit) memory operand, both prefixes are honored;
otherwise only the applicable one is.
Note that for some forms of XCHG, {store} has already been performing
this function, apparently as an unnoticed side effect of adding D to
the template.
The feature isn't universally available on 64-bit CPUs.
Note that in i386-gen.c:isa_dependencies[] I'm only adding it to models
where I'm certain the functionality exists. For Nocona and Core I'm
uncertain in particular.
While MOV to/from segment register as well as selector storing insns
already permit 32- and 64-bit GPR operands, selector loading insns and
ARPL do not. Split templates accordingly.
For shifts (but not ordinary rotates) and other cases where an immediate
describes e.g. a bit count or position, allowing negative operands is at
best confusing. An extreme example would be the two rotate-through-carry
insns, where a negative value would _not_ mean rotating the
corresponding number of bits in the other direction. To refuse such,
give meaning to the combination of Imm8 and Imm8S in templates (so far
these weren't used together anywhere). The issue was with
smallest_imm_type() blindly setting .imm8 for signed numbers determined
to fit in a byte.
VPROT{B,W,D,Q} is a little special: The rotate count there is a signed
quantity, so Imm8 is replaced by Imm8S. Adjust affected testcases
accordingly as well.
Another small adjustment to the testsuite is necessary: AAM and AAD were
never sensible to use with 0xffffff90 operands. This should have been an
error.
Just like we suppress emitting REX.W for e.g. MOV from/to segment
register, there's also no need for it for LAR and LSL - these can only
ever return 32-bit values and hence always zero-extend their results
anyway.
While there also drop the redundant Word from the first operand of
the second template each - this is already implied by Reg16.
In 64-bit mode BT can have REX.W or a data size prefix dropped in
certain cases. Outside of 64-bit mode all 4 insns can have the data
size prefix dropped in certain cases.
When dealing with case insensitive file systems, ".file line.s" and
".file Line.s" are identical and thus gas won't change the current
input file.
However, in line.l test, it's expecting to trigger an input file switch.
As the second filename doesn't matter in it, change it to fit for those
file systems.
gas/ChangeLog:
* testsuite/gas/elf/line.l: Change Line.s to Line2.s.
* testsuite/gas/elf/line.s: Adjust output.
In 162c6aef1f ("gas: fold symbol table entries generated for
.startof.() / .sizeof.()") I screwed up quite badly, inverting the case
sensitive and case insensitive comparison functions.
There is some inconsistency between the behaviour of objdump -D and
objdump -s, both supposedly operating on all sections by default.
objdump -s ignores bss sections, while objdump -D dissassembles the
zeros. Fix this by making objdump -D ignore bss sections too.
Furthermore, "objdump -s -j .bss" doesn't dump .bss as it should,
since the user is specifically asking to look at all those zeros.
This change does find some tests that used objdump -D with expected
output in bss-style sections. I've updated all the msp430 tests that
just wanted to find a non-empty section to look at section headers
instead, making the tests slightly more stringent. The ppc xcoff and
spu tests are fixed by adding -j options to objdump, which makes the
tests somewhat more lenient.
binutils/
* objdump.c (disassemble_section): Ignore sections without
contents, unless overridden by -j.
(dump_section): Allow -j to override the default of not
displaying sections without contents.
* doc/binutils.texi (objdump options): Update -D, -s and -j
description.
gas/
* testsuite/gas/ppc/xcoff-tls-32.d: Select wanted objdump
sections with -j.
* testsuite/gas/ppc/xcoff-tls-64.d: Likewise.
ld/
* testsuite/ld-msp430-elf/main-bss-lower.d,
* testsuite/ld-msp430-elf/main-bss-upper.d,
* testsuite/ld-msp430-elf/main-const-lower.d,
* testsuite/ld-msp430-elf/main-const-upper.d,
* testsuite/ld-msp430-elf/main-text-lower.d,
* testsuite/ld-msp430-elf/main-text-upper.d,
* testsuite/ld-msp430-elf/main-var-lower.d,
* testsuite/ld-msp430-elf/main-var-upper.d: Expect -wh output.
* testsuite/ld-msp430-elf/msp430-elf.exp: Use objdump -wh
rather than objdump -D or objdump -d with tests checking for
non-empty given sections.
* testsuite/ld-spu/ear.d,
* testsuite/ld-spu/icache1.d,
* testsuite/ld-spu/ovl.d,
* testsuite/ld-spu/ovl2.d: Select wanted objdump sections.
Swapping operands for commutative insns occurs outside of
optimize_encoding() and hence needs explicit checking for a request to
avoid any optimizations.
Dropping a meaningless segment prefix occurs outside of
optimize_encoding() and hence needs explicit checking for a request to
avoid any optimizations.
Insn width granularity being 16 bits, producing byte granular output
isn't very useful. With there being a way to specific otherwise
unknown insns to the assembler, use that same representation (to be
precise: its <length>,<encoding> flavor) for disassembly.
Currently, when using -gdwarf-2, gas emits a v3 .debug_line contribution.
Fix this by emitting a v2 .debug_line contribution instead.
gas/ChangeLog:
2023-01-31 Tom de Vries <tdevries@suse.de>
PR 23941
* dwarf2dbg.c (DWARF2_LINE_VERSION): Set to 2 for -gdwarf-2.
(DWARF2_LINE_OPCODE_BASE): Handle DWARF2_LINE_VERSION == 2.
(dwarf2_directive_loc): Bump dwarf_level when encountering
v3 .loc options.
(out_debug_line): Don't output v3 standard opcodes for v2.
* testsuite/gas/i386/debug1.d: Update.
* testsuite/gas/i386/dwarf2-line-1.d: Update.
* testsuite/gas/i386/dwarf2-line-4.d: Update.
I noticed that some of the Power6 DFP instructions were not covered by
the assembler tests. I've added a new test file which I believe
covers all the DFP Power6 instructions.
The existing gas/testsuite/gas/ppc/power6.d test is called:
POWER6 tests (includes DFP and Altivec)
And does cover some of the DFP instructions. But, given the number of
additional instructions I'm adding I opted to add a whole new test
file. I've left the original power6.d unchanged, so there is now some
overlap, but I don't think that should hurt much.
Along with the normal JAL alias, the C-extension one should have been
moved as well by 839189bc93 ("RISC-V: re-arrange opcode table for
consistent alias handling"), for the assembler to actually be able to
use it where/when possible.
Since neither this nor any other compressed branch insn was being tested
so far, take the opportunity and introduce a new testcase covering those.
We noticed that a warning message about the use of scalar fp16
instructions being UNPREDICTABLE when conditionalized in an IT
block referenced the specific A-class architecture revision
ARMv8.2-A.
Many of these instructions are now also part of ARMv8.1-M, so
the warning message had become misleading. Here we just change
the message to not specify an architecture revision at all and
update all testing accordingly. This was done with a simple
find-n-replace within the binutils sources. No tests have
regressed for the arm target.
gas/ChangeLog:
* config/tc-arm.c (do_scalar_fp16_v82_encode): Remove
ARMv8.2-A from the warning message.
(do_neon_movhf): Likewise
* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Likewise
* testsuite/gas/arm/mve-vaddsub-it-bad.l: Likewise
* testsuite/gas/arm/mve-vcvtne-it-bad.l: Likewise
* testsuite/gas/arm/mve-vcvtne-it.d: Likewise
Previously we had experienced issues with assembling a "VCVTNE" instruction
in the presence of the MVE architecture extension, because it could be
interpreted both as:
* The base instruction VCVT + NE for IT predication when inside an IT block.
* The MVE instruction VCVTN + E in the Else of a VPT block.
Given a C reproducer of:
```
int test_function(float value)
{
int ret_val = 10;
if (value != 0.0)
{
ret_val = (int) value;
}
return ret_val;
}
```
GCC generates a VCVTNE instruction based on the `truncsisf2_vfp`
pattern, which will look like:
`vcvtne.s32.f32 s-reg, s-reg`
This still triggers an error due to being misidentified as "vcvtn+e"
Similar errors were found with other type combinations and instruction
patterns (these have all been added to the testing of this patch).
This class of errors was previously worked around by:
https://sourceware.org/pipermail/binutils/2020-August/112728.html
which addressed this by looking at the operand types, however,
that isn't adequate to cover all the extra cases that have been
found. Instead, we add some special-casing logic earlier when
the instructions are parsed that is conditional on whether we are
in a VPT block or not, when the instruction is parsed.
gas/ChangeLog:
* config/tc-arm.c (opcode_lookup): Add special vcvtn handling.
* testsuite/gas/arm/mve-vcvtne-it-bad.l: Add further testing.
* testsuite/gas/arm/mve-vcvtne-it-bad.s: Likewise.
* testsuite/gas/arm/mve-vcvtne-it.d: Likewise.
* testsuite/gas/arm/mve-vcvtne-it.s: Likewise.
This adds a mingw target for aarch64, including windres and dlltool.
Note that the old value of jmp_aarch64_bytes was wrong, and this does
the same thing as MSVC does.
This adds the remaining pe-aarch64 relocations, and gets them working.
It also brings in the constant directives from ELF, as otherwise .word
would be 2 rather than 4 bytes, and .xword and .dword wouldn't be
defined.
Delete a few files only used for obsolete targets, and tidy config,
xfails and other pieces of support specific to those targets. And
since I was editing target triplets in test files, fix the nm
alpha-linuxecoff fails.
The newer update-copyright.py fixes file encoding too, removing cr/lf
on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and
embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
This fixes a couple of places in display_debug_lines_decoded that were
off by one in checking DWARF5 .debug_line directory indices. It also
displays the DWARF5 entry 0 for the program current directory rather
than "." as is done for pre-DWARF5. I decided against displaying
DW_AT_comp_dir for pre-DWARF5 since I figure it is better for readelf
to minimally interpret debug info.
binutils/
PR 29948
* dwarf.c (display_debug_lines_decoded): Display the given
directory entry 0 for DWARF5. Properly check directory index
against number of entries in the table. Revert to using
unsigned int for n_directories and associated variables.
Correct warning messages.
gas/
* testsuite/gas/elf/dwarf-5-loc0.d: Update.
* riscv-toolchain-conventions,
PR, https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14
Issue, https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11
* Refer to the commit afc41ffb,
RISC-V: Reorder the prefixed extensions which are out of order.
In the past we only allow to reorder the prefixed extensions. But according
to the PR 14 in the riscv-toolchain-convention, we can also relax the order
checking to allow the whole extensions be written out of orders, including
the single standard extensions and the prefixed multi-letter extensions.
Just that we still need to follow the following rules as usual,
1. prefixed extensions need to be seperated with `_'.
2. prefixed extensions need complete <major>.<minor> version if set.
Please see the details in the march-ok-reorder gas testcase.
Passed the riscv-gnu-toolchain regressions.
bfd/
* elfxx-riscv.c (enum riscv_prefix_ext_class): Changed RV_ISA_CLASS_UNKNOWN
to RV_ISA_CLASS_SINGLE, since everything that does not belong to the
multi-keyword will possible be a single extension for the current parser.
(parse_config): Likewise.
(riscv_get_prefix_class): Likewise.
(riscv_compare_subsets): Likewise.
(riscv_parse_std_ext): Removed, and merged with riscv_parse_prefixed_ext
into riscv_parse_extensions.
(riscv_parse_prefixed_ext): Likewise.
(riscv_parse_subset): Only need to call riscv_parse_extensions to parse
both single standard and prefixed extensions.
gas/
* testsuite/gas/riscv/march-fail-order-std.d: Removed since the relaxed
order checking.
* testsuite/gas/riscv/march-fail-order-std.l: Likewise.
* testsuite/gas/riscv/march-fail-order-x-std.d: Likewise.
* testsuite/gas/riscv/march-fail-order-z-std.d: Likewise.
* testsuite/gas/riscv/march-fail-order-zx-std.l: Likewise.
* testsuite/gas/riscv/march-fail-unknown-std.l: Updated.
* testsuite/gas/riscv/march-ok-reorder.d: New testcase.
This is actually a composite test that checks SFrame unwind information
generation for both the .cfi_negate_ra_state and .cfi_b_key_frame
directives on aarch64.
ChangeLog:
* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.d:
New test.
* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-pac-ab-key-1.s:
Likewise.
* testsuite/gas/cfi-sframe/cfi-sframe.exp: Run new test.
It is kind of odd to have the expansions of such constructs ahead of
their definition in listings with macro expansion enabled. Adjust this
by pulling ahead the output of the definition lines, taking care to
avoid producing a listing line for (non-existing) line 0 when the source
is stdin.
Note that with the code movement the conditional operator isn't
necessary anymore - list->line now match up.
Like AVX512-FP16, several other extensions require wider than 16-bit
mask registers. As a result they take AVX512BW as a prereq, not (just)
AVX512F. Which in turn points out wrong expectations in the noavx512-1
testcase.
So far the set of ".noavx512*" has been accumulating, which isn't ideal.
In particular this hides issues with dependencies between features.
Switch back to the default ISA before disabling a particular subset.
Furthermore limit redundancy by wrapping the repeated block of insns in
an .irp.
Add a new test to check that .cfi_negate_ra_state on aarch64 is handled
well (a non-empty SFrame section with valid SFrame FREs is generated).
ChangeLog:
* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.d: New test.
* testsuite/gas/cfi-sframe/cfi-sframe-aarch64-2.s: Likewise.
* testsuite/gas/cfi-sframe/cfi-sframe.exp: Adjust the list
accordingly.
DW_CFA_AARCH64_negate_ra_state in aarch64 is multiplexed with
DW_CFA_GNU_window_save in the DWARF format.
Remove the common-empty-4 testcase because the generated SFrame section
will not be be empty anymore. A relevant test will be added in a later
commit.
ChangeLog:
* gas/gen-sframe.c (sframe_v1_set_fre_info): Add new argument
for mangled_ra_p.
(sframe_set_fre_info): Likewise.
(output_sframe_row_entry): Handle mangled_ra_p.
(sframe_row_entry_new): Reset mangled_ra_p.
(sframe_row_entry_initialize): Initialize mangled_ra_p.
(sframe_xlate_do_gnu_window_save): New definition.
(sframe_do_cfi_insn): Handle DW_CFA_GNU_window_save.
* gas/gen-sframe.h (struct sframe_row_entry): New member.
(struct sframe_version_ops): Add a new argument for
mangled_ra_p.
* gas/testsuite/gas/cfi-sframe/cfi-sframe.exp: Remove test.
* gas/testsuite/gas/cfi-sframe/common-empty-4.d: Removed.
* gas/testsuite/gas/cfi-sframe/common-empty-4.s: Removed.
While 6fdb723799 ("gas: re-work line number tracking for macros and
their expansions") was meant to leave generated Dwarf as is, it really
didn't (and the testcase intended to catch that wasn't covering the case
which broke). Its adjustment to buffer_and_nest() didn't go far enough,
leading to the "linefile" directive inserted at the top to also be
processed later in the PR gas/16908 workaround (which clearly isn't
intended - it's being put there for processing during macro expansion
only). That unnoticed flaw in turn led me to work around it by a
(suspicious to me already at the time) conditional in as_where().
The current AS accepts invalid operands due to miss of operands length check.
For example, "e6" is an invalid operand in (vsetvli a0, a1, e6, mf8, tu, ma),
but it's still accepted by assembler. In detail, the condition check "strncmp
(array[i], *s, len) == 0" in arg_lookup function passes with "strncmp ("e64",
"e6", 2)" in the case above. So the generated encoding is same as that of
(vsetvli a0, a1, e64, mf8, tu, ma).
This patch fixes issue above by prompting an error in such case and also adds
a new testcase.
gas/ChangeLog:
* config/tc-riscv.c (arg_lookup): Add string length check for operands.
* testsuite/gas/riscv/vector-insns-fail-vsew.d: New testcase for an illegal vsew.
* testsuite/gas/riscv/vector-insns-fail-vsew.l: Likewise.
* testsuite/gas/riscv/vector-insns-fail-vsew.s: Likewise.
The PR gas/16908 workaround aimed at uniformly reporting line numbers
to reference macro invocation sites. As mentioned in a comment this may
be desirable for small macros, but often isn't for larger ones. As a
first step improve diagnostics to report both locations, while aiming at
leaving generated debug info unaltered.
Note that macro invocation context is lost for any diagnostics issued
only after all input was processed (or more generally for any use of
as_*_where(), as the functions can't know whether the passed in location
is related to [part of] the present stack of locations). To maintain the
intended workaround behavior for PR gas/16908, a new as_where() is
introduced to "look through" macro invocations, while the existing
as_where() is renamed (and used in only very few places for now). Down
the road as_where() will likely want to return a list of (file,line)
pairs.
Macros with just a single use site are a little pointless to have, and
even in further cases .irp is more suitable for the purpose. Expand such
inline, avoiding the need to touch the testcases when diagnostics are
changed for code resulting from macro expansion.
While there also make what was "iter_mla" in sp-usage-thumb2-relax cover
smlatt as well, rather than testing smlabt twice.
PR gas/29524
Having templates with a suffix explicitly present has always been
quirky. After prior adjustment all that's left to also eliminate the
anomaly from move-with-sign-extend is to consolidate the insn templates
and to make may_need_pass2() cope (plus extend testsuite coverage).
In commit 1212781b35 ("ix86: allow HLE store of accumulator to
absolute address") I was wrong to exclude 64-bit code. Dropping the
check also leads to better diagnostics in 64-bit code ("MOV", after
all, isn't invalid with "XRELEASE").
While there also limit the amount of further checks done: The operand
type checks that were there were effectively redundant with other ones
anyway, plus it's quite fine to also have "xrelease mov <disp>, %eax"
look for the next MOV template (in fact again also improving
diagnostics).
Have its use, except where actually legitimate, result in the same "only
supported in 64-bit mode" diagnostic as emitted for other 64-bit only
insns. Also suppress deriving of the suffix in Intel mode except in the
legitimate cases. This in exchange allows dropping the respective code
from match_template().
To maintain reasonable diagnostics (in particular to avoid "`mov' is
only supported in 64-bit mode" on the SIMD forms of MOVQ) we need to
defer parse_insn()'s emitting of errors unrelated to prefix parsing.
Utilize i.error just like match_template() does.
Oddly enough despite gcc's preference towards FILDQ and FIST{,T}Q we
had no testcase whatsoever for these. Therefore such tests are being
added. Note that the removed line in the x86-64-lfence-load testcase
was redundant with the exact same one a few lines up.
Having templates with a suffix explicitly present has always been
quirky. Introduce a 2nd matching pass in case the 1st one couldn't find
a suitable template _and_ didn't itself already need to trim off a
suffix to find a match at all. This requires error reporting adjustments
(albeit luckily fewer than I was afraid might be necessary), as errors
previously reported during matching now need deferring until after the
2nd pass (because, obviously, we must not emit any error if the 2nd pass
succeeds). While also related to PR gas/29524, it was requested that
move-with-sign-extend be left as broken as it always was.
PR gas/29525
Note that with the dropped CMPSD and MOVSD Intel Syntax string insn
templates taking operands, mixed IsString/non-IsString template groups
(with memory operands) cannot occur anymore. With that
maybe_adjust_templates() becomes unnecessary (and is hence being
removed).
PR gas/29526
Note further that while the additions to the intel16 testcase aren't
really proper Intel syntax, we've been permitting all of those except
for the MOVD variant. The test therefore is to avoid re-introducing such
an inconsistency.
