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[Aarch64] Add Binutils support for MEC

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This change supports MEC which is part of RME (Realm Management Extension).
This commit is contained in:
Richard Ball
2023-02-28 10:55:25 +00:00
committed by Nick Clifton
parent 26c294bd1b
commit 31f2faf5cf
8 changed files with 74 additions and 0 deletions
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8
gas/ChangeLog
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@@ -1,3 +1,11 @@
2023-02-28 Richard Ball <richard.ball@arm.com>
* testsuite/gas/aarch64/mec-invalid.d: New test.
* testsuite/gas/aarch64/mec-invalid.l: New test.
* testsuite/gas/aarch64/mec-invalid.s: New test.
* testsuite/gas/aarch64/mec.d: New test.
* testsuite/gas/aarch64/mec.s: New test.
2023-02-27 Benson Muite <benson_muite@emailplus.org>
PR 28909

3
gas/testsuite/gas/aarch64/mec-invalid.d Normal file
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#name: Invalid MEC System registers usage
#source: mec-invalid.s
#warning_output: mec-invalid.l

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gas/testsuite/gas/aarch64/mec-invalid.l Normal file
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.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1.*

4
gas/testsuite/gas/aarch64/mec-invalid.s Normal file
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// Memory Encryption Contexts, an extension of RME.
// Illegal write to MEC system registers.
msr mecidr_el2, x0

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gas/testsuite/gas/aarch64/mec.d Normal file
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#name: MEC System registers
#objdump: -dr
.*: file format .*
Disassembly of section .text:
0+ <.*>:
[^:]*: d53ca8e0 mrs x0, mecidr_el2
[^:]*: d53ca800 mrs x0, mecid_p0_el2
[^:]*: d53ca820 mrs x0, mecid_a0_el2
[^:]*: d53ca840 mrs x0, mecid_p1_el2
[^:]*: d53ca860 mrs x0, mecid_a1_el2
[^:]*: d53ca900 mrs x0, vmecid_p_el2
[^:]*: d53ca920 mrs x0, vmecid_a_el2
[^:]*: d53eaa20 mrs x0, mecid_rl_a_el3
[^:]*: d51ca800 msr mecid_p0_el2, x0
[^:]*: d51ca820 msr mecid_a0_el2, x0
[^:]*: d51ca840 msr mecid_p1_el2, x0
[^:]*: d51ca860 msr mecid_a1_el2, x0
[^:]*: d51ca900 msr vmecid_p_el2, x0
[^:]*: d51ca920 msr vmecid_a_el2, x0
[^:]*: d51eaa20 msr mecid_rl_a_el3, x0

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gas/testsuite/gas/aarch64/mec.s Normal file
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// Memory Encryption Contexts, an extension of RME.
// Read from MEC system registers.
mrs x0, mecidr_el2
mrs x0, mecid_p0_el2
mrs x0, mecid_a0_el2
mrs x0, mecid_p1_el2
mrs x0, mecid_a1_el2
mrs x0, vmecid_p_el2
mrs x0, vmecid_a_el2
mrs x0, mecid_rl_a_el3
// Write to MEC system registers.
msr mecid_p0_el2, x0
msr mecid_a0_el2, x0
msr mecid_p1_el2, x0
msr mecid_a1_el2, x0
msr vmecid_p_el2, x0
msr vmecid_a_el2, x0
msr mecid_rl_a_el3, x0

4
opcodes/ChangeLog
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@@ -1,3 +1,7 @@
2023-02-28 Richard Ball <richard.ball@arm.com>
* aarch64-opc.c: Add MEC system registers.
2023-01-03 Nick Clifton <nickc@redhat.com>
* po/de.po: Updated German translation.

9
opcodes/aarch64-opc.c
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@@ -5010,6 +5010,15 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),
SR_CORE ("mecidr_el2", CPENC (3,4,C10,C8,7), F_REG_READ),
SR_CORE ("mecid_p0_el2", CPENC (3,4,C10,C8,0), 0),
SR_CORE ("mecid_a0_el2", CPENC (3,4,C10,C8,1), 0),
SR_CORE ("mecid_p1_el2", CPENC (3,4,C10,C8,2), 0),
SR_CORE ("mecid_a1_el2", CPENC (3,4,C10,C8,3), 0),
SR_CORE ("vmecid_p_el2", CPENC (3,4,C10,C9,0), 0),
SR_CORE ("vmecid_a_el2", CPENC (3,4,C10,C9,1), 0),
SR_CORE ("mecid_rl_a_el3",CPENC (3,6,C10,C10,1), 0),
SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0),
SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5), F_REG_READ),
SR_SME ("smcr_el1", CPENC (3,0,C1,C2,6), 0),