It is necessary to enable the DWT using a special initialization
sequence before the CYCCNT can be enabled. See for example the
RESET_CYCLE_COUNTER in libbsp/arm/atsam/utils/utility.h.
Note that this problem only occurs if no debugger is connected. A
debugger most likely already enables the necessary module.
Since the FP area pointer is passed by reference in
_CPU_Context_Initialize_fp() the optional FP area adjustment via
_CPU_Context_Fp_start() is superfluous. It is also wrong with respect
to memory management, e.g. pointer passed to _Workspace_Free() may be
not the one returned by _Workspace_Allocate().
Close#1400.
On SMP configurations, it is a fatal error to call blocking operating
system with interrupts disabled, since this prevents delivery of
inter-processor interrupts. This could lead to executing threads which
are not allowed to execute resulting in undefined behaviour.
The ARM Cortex-M port has a similar problem, since the interrupt state
is not a part of the thread context.
Update #2811.
We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM
mode for the Thumb-1 targets during interrupt low-level processing.
Update #2751.
Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution. During this period we must not use
a thread stack for interrupt processing.
Update #2809.
Use the previously unused TPIDRPRW register to get the per-CPU control
of the current processor. This avoids instructions in
GET_SELF_CPU_CONTROL which are not available in Thumb mode.
The aim of this file is to encapsulate CPU port implementation details.
This helps to hide implementation details from <rtems.h> which
indirectly includes <rtems/score/cpu.h>.
The use of actual cache line max bytes and minimum required alignment
in architecture but not-BSP dependent code could be problematic
because there exists even ARM instruction set implementations
with 128 byte line length and real maximum can be quite problematic
to say. But actually supported ARM BSPs should be OK with these values.
Only use CPU_Per_CPU_control if it contains at least one filed. In GNU
C empty structures have a size of zero. In C++ structures have a
non-zero size. In case CPU_PER_CPU_CONTROL_SIZE is defined to zero,
then this structure is not used anymore.
The main reason for inclusion of minimum hypervisor related defines
is that current ARM boards firmware and loaders (U-boot for example)
start loaded operating system kernel in HYP mode to allow it take
control of virtualization (Linux/KVM for example).
The priority bit map can deal with a maximum of 256 priority values
ranging from 0 to 255. Consistently use an unsigned int for
computation, due to the usual integer promotion rules.
Make Priority_bit_map_Word definition architecture-independent and
define it to uint16_t. This was already the case for all architectures
except PowerPC. Adjust the PowerPC bitmap support accordingly.
Rename __log2table into _Bitfield_Leading_zeros since it acually returns
the count of leading zeros of an 8-bit integer. The value for zero is a
bit odd. Provide it unconditionally.
Rename _ISR_Disable() into _ISR_Local_disable(). Rename _ISR_Enable()
into _ISR_Local_enable(). Remove _Debug_Is_owner_of_giant().
This is a preparation to remove the Giant lock.
Update #2555.
According to the C11 and C++11 memory models only a read-modify-write
operation guarantees that we read the last value written in modification
order. Avoid the sequential consistent thread fence and instead use the
inter-processor interrupt to set the thread dispatch necessary
indicator.
This patch adds a brief description of how context state is saved into the
SP on exception entry, and makes a few changes to _ARMV7M_Exception_default
in order to make it a bit more efficient. I also removed the unused 'v7mfsz'
input parameter.
This should apply over Sudarshan's patch.
