forked from Imagelibrary/rtems
arm: Fix Thumb-1 targets
We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM mode for the Thumb-1 targets during interrupt low-level processing. Update #2751.
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@@ -102,8 +102,8 @@ _ARMV4_Exception_interrupt:
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cmp r2, #0
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moveq sp, r1
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/* Switch to THUMB instructions if necessary */
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SWITCH_FROM_ARM_TO_THUMB r1
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/* Switch to Thumb-2 instructions if necessary */
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SWITCH_FROM_ARM_TO_THUMB_2 r1
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/* Increment interrupt nest and thread dispatch disable level */
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ldr r3, [SELF_CPU_CONTROL, #PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
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@@ -116,18 +116,18 @@ _ARMV4_Exception_interrupt:
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#ifdef RTEMS_PROFILING
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cmp r2, #1
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bne .Lskip_profiling
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bl _CPU_Counter_read
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BLX_TO_THUMB_1 _CPU_Counter_read
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mov SELF_CPU_CONTROL, r0
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bl bsp_interrupt_dispatch
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bl _CPU_Counter_read
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BLX_TO_THUMB_1 bsp_interrupt_dispatch
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BLX_TO_THUMB_1 _CPU_Counter_read
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mov r2, r0
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mov r1, SELF_CPU_CONTROL
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GET_SELF_CPU_CONTROL r0
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mov SELF_CPU_CONTROL, r0
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bl _Profiling_Outer_most_interrupt_entry_and_exit
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BLX_TO_THUMB_1 _Profiling_Outer_most_interrupt_entry_and_exit
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.Lprofiling_done:
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#else
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bl bsp_interrupt_dispatch
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BLX_TO_THUMB_1 bsp_interrupt_dispatch
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#endif
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/* Load some per-CPU variables */
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@@ -175,7 +175,7 @@ _ARMV4_Exception_interrupt:
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mov r1, NON_VOLATILE_SCRATCH
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mov r2, #0x80
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bic r1, r2
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bl _Thread_Do_dispatch
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BLX_TO_THUMB_1 _Thread_Do_dispatch
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/* Disable interrupts */
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msr CPSR, NON_VOLATILE_SCRATCH
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@@ -196,7 +196,7 @@ _ARMV4_Exception_interrupt:
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.Lthread_dispatch_done:
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/* Switch to ARM instructions if necessary */
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SWITCH_FROM_THUMB_TO_ARM
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SWITCH_FROM_THUMB_2_TO_ARM
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#ifdef ARM_MULTILIB_VFP
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/* Restore VFP context */
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@@ -274,7 +274,7 @@ _ARMV4_Exception_interrupt:
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.thumb
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#endif
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.Lskip_profiling:
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bl bsp_interrupt_dispatch
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BLX_TO_THUMB_1 bsp_interrupt_dispatch
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b .Lprofiling_done
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#endif
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@@ -187,6 +187,36 @@
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#endif /* __thumb__ */
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.endm
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.macro SWITCH_FROM_THUMB_2_TO_ARM
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#ifdef __thumb2__
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.align 2
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bx pc
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.arm
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#endif /* __thumb__ */
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.endm
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.macro SWITCH_FROM_ARM_TO_THUMB_2 REG
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#ifdef __thumb2__
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add \REG, pc, #1
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bx \REG
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.thumb
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#endif /* __thumb__ */
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.endm
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.macro BLX_TO_THUMB_1 TARGET
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#if defined(__thumb__) && !defined(__thumb2__)
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add lr, pc, #1
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bx lr
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.thumb
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bl \TARGET
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.align 2
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bx pc
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.arm
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#else
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bl \TARGET
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#endif
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.endm
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.macro GET_SELF_CPU_CONTROL REG
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#ifdef RTEMS_SMP
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/* Use PL1 only Thread ID Register (TPIDRPRW) */
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