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score: Move CPU_PER_CPU_CONTROL_SIZE

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Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
This commit is contained in:
Sebastian Huber
2016-11-11 10:16:33 +01:00
parent d78d5294cd
commit 82d30a310c
34 changed files with 125 additions and 94 deletions
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2
cpukit/score/cpu/arm/rtems/score/cpu.h
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@@ -197,8 +197,6 @@
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/** @} */

4
cpukit/score/cpu/arm/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/bfin/rtems/score/cpu.h
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@@ -329,8 +329,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/bfin/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

1
cpukit/score/cpu/epiphany/rtems/score/cpu.h
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@@ -671,7 +671,6 @@ void _CPU_Context_Initialize(
*/
#define CPU_SIZEOF_POINTER 4
#define CPU_EXCEPTION_FRAME_SIZE 260
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32

4
cpukit/score/cpu/epiphany/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/i386/rtems/score/cpu.h
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@@ -120,8 +120,6 @@ extern "C" {
#define CPU_BIG_ENDIAN FALSE
#define CPU_LITTLE_ENDIAN TRUE
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
#define I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0

4
cpukit/score/cpu/i386/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/lm32/rtems/score/cpu.h
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@@ -323,8 +323,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/lm32/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/m32c/rtems/score/cpu.h
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@@ -346,8 +346,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/m32c/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/m68k/rtems/score/cpu.h
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@@ -111,8 +111,6 @@ extern "C" {
#define CPU_BIG_ENDIAN TRUE
#define CPU_LITTLE_ENDIAN FALSE
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )

4
cpukit/score/cpu/m68k/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/mips/rtems/score/cpu.h
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@@ -292,8 +292,6 @@ extern "C" {
#define CPU_SIZEOF_POINTER 4
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/mips/rtems/score/cpuimpl.h
View File

@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/moxie/rtems/score/cpu.h
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@@ -261,8 +261,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/moxie/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/nios2/rtems/score/cpu.h
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@@ -102,8 +102,6 @@ extern "C" {
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
#ifndef ASM

4
cpukit/score/cpu/nios2/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

22
cpukit/score/cpu/no_cpu/rtems/score/cpu.h
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@@ -360,14 +360,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
/**
* @brief The size of the CPU specific per-CPU control.
*
* This define must be visible to assember files since it is used to derive
* structure offsets.
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
/**
* @brief Maximum number of processors of all systems supported by this CPU
* port.
@@ -384,20 +376,6 @@ extern "C" {
/* may need to put some structures here. */
/**
* @brief The CPU specific per-CPU control.
*
* The CPU port can place here all state information that must be available and
* maintained for each processor in the system. This structure must contain at
* least one field for C/C++ compatibility. In GNU C empty structures have a
* size of zero. In C++ structures have a non-zero size. In case
* CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not
* used.
*/
typedef struct {
/* CPU specific per-CPU state */
} CPU_Per_CPU_control;
/**
* @defgroup CPUContext Processor Dependent Context Management
*

24
cpukit/score/cpu/no_cpu/rtems/score/cpuimpl.h
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@@ -5,7 +5,7 @@
*/
/*
* Copyright (c) 2015, 2016 embedded brains GmbH
* Copyright (c) 2013, 2016 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -17,12 +17,34 @@
#include <rtems/score/cpu.h>
/**
* @brief The size of the CPU specific per-CPU control.
*
* This define must be visible to assember files since it is used to derive
* structure offsets.
*/
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief The CPU specific per-CPU control.
*
* The CPU port can place here all state information that must be available and
* maintained for each processor in the system. This structure must contain at
* least one field for C/C++ compatibility. In GNU C empty structures have a
* size of zero. In C++ structures have a non-zero size. In case
* CPU_PER_CPU_CONTROL_SIZE is defined to zero, then this structure is not
* used.
*/
typedef struct {
/* CPU specific per-CPU state */
} CPU_Per_CPU_control;
/**
* @brief Special register pointing to the per-CPU control of the current
* processor.

1
cpukit/score/cpu/or1k/rtems/score/cpu.h
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@@ -658,7 +658,6 @@ void _CPU_Context_Initialize(
#endif /* ASM */
#define CPU_SIZEOF_POINTER 4
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32

4
cpukit/score/cpu/or1k/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/powerpc/rtems/score/cpu.h
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@@ -152,8 +152,6 @@ extern "C" {
#define CPU_IDLE_TASK_IS_FP FALSE
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h
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@@ -5,7 +5,7 @@
*/
/*
* Copyright (c) 2016 embedded brains GmbH
* Copyright (c) 2013, 2016 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -17,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifdef RTEMS_SMP
/* Use SPRG0 for the per-CPU control of the current processor */

2
cpukit/score/cpu/sh/rtems/score/cpu.h
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@@ -239,8 +239,6 @@ extern "C" {
#define CPU_MODES_INTERRUPT_MASK 0x0000000f
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/sh/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

41
cpukit/score/cpu/sparc/rtems/score/cpu.h
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@@ -347,28 +347,8 @@ typedef struct {
/** This defines the size of the minimum stack frame. */
#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
#if ( SPARC_HAS_FPU == 1 )
#define CPU_PER_CPU_CONTROL_SIZE 8
#else
#define CPU_PER_CPU_CONTROL_SIZE 4
#endif
#define CPU_MAXIMUM_PROCESSORS 32
/**
* @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
* relative to the Per_CPU_Control begin.
*/
#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
* Per_CPU_Control begin.
*/
#define SPARC_PER_CPU_FSR_OFFSET 4
#endif
/**
* @defgroup Contexts SPARC Context Structures
*
@@ -392,27 +372,6 @@ typedef struct {
#ifndef ASM
typedef struct {
/**
* This flag is context switched with each thread. It indicates
* that THIS thread has an _ISR_Dispatch stack frame on its stack.
* By using this flag, we can avoid nesting more interrupt dispatching
* attempts on a previously interrupted thread's stack.
*/
uint32_t isr_dispatch_disable;
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Memory location to store the FSR register during interrupt
* processing.
*
* This is a write-only field. The FSR is written to force a completion of
* floating point operations in progress.
*/
uint32_t fsr;
#endif
} CPU_Per_CPU_control;
/**
* @brief SPARC basic context.
*

44
cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
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@@ -5,7 +5,8 @@
*/
/*
* Copyright (c) 2015, 2016 embedded brains GmbH
* Copyright (c) 2007 On-Line Applications Research Corporation (OAR)
* Copyright (c) 2013, 2016 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
@@ -17,12 +18,53 @@
#include <rtems/score/cpu.h>
#if ( SPARC_HAS_FPU == 1 )
#define CPU_PER_CPU_CONTROL_SIZE 8
#else
#define CPU_PER_CPU_CONTROL_SIZE 4
#endif
/**
* @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
* relative to the Per_CPU_Control begin.
*/
#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
* Per_CPU_Control begin.
*/
#define SPARC_PER_CPU_FSR_OFFSET 4
#endif
#ifndef ASM
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
/**
* This flag is context switched with each thread. It indicates
* that THIS thread has an _ISR_Dispatch stack frame on its stack.
* By using this flag, we can avoid nesting more interrupt dispatching
* attempts on a previously interrupted thread's stack.
*/
uint32_t isr_dispatch_disable;
#if ( SPARC_HAS_FPU == 1 )
/**
* @brief Memory location to store the FSR register during interrupt
* processing.
*
* This is a write-only field. The FSR is written to force a completion of
* floating point operations in progress.
*/
uint32_t fsr;
#endif
} CPU_Per_CPU_control;
/**
* @brief The pointer to the current per-CPU control is available via register
* g6.

2
cpukit/score/cpu/sparc64/rtems/score/cpu.h
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@@ -198,8 +198,6 @@ extern "C" {
#define CPU_MODES_INTERRUPT_MASK 0x0000000F
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/*

4
cpukit/score/cpu/sparc64/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus

2
cpukit/score/cpu/v850/rtems/score/cpu.h
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@@ -322,8 +322,6 @@ extern "C" {
*/
#define CPU_MODES_INTERRUPT_MASK 0x00000001
#define CPU_PER_CPU_CONTROL_SIZE 0
#define CPU_MAXIMUM_PROCESSORS 32
/**

4
cpukit/score/cpu/v850/rtems/score/cpuimpl.h
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@@ -5,6 +5,8 @@
*/
/*
* Copyright (c) 2013 embedded brains GmbH
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
@@ -15,6 +17,8 @@
#include <rtems/score/cpu.h>
#define CPU_PER_CPU_CONTROL_SIZE 0
#ifndef ASM
#ifdef __cplusplus