arm: Fix CPU context validation for Cortex-R4

Do not touch the FPSCR[QC] bit since this is DNM/RAZ on Cortex-R4.
This commit is contained in:
Sebastian Huber
2017-03-09 14:32:04 +01:00
parent dc95663e8b
commit b437a36064
2 changed files with 3 additions and 7 deletions

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -103,11 +103,7 @@ FUNCTION_ENTRY(_CPU_Context_validate)
#ifdef ARM_MULTILIB_VFP
/* R3 contains the FPSCR */
vmrs r3, FPSCR
#ifdef ARM_MULTILIB_ARCH_V7M
ldr r4, =0xf000001f
#else
ldr r4, =0xf800001f
#endif
bic r3, r3, r4
and r4, r4, r0
orr r3, r3, r4

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Dornierstr. 4
@@ -33,7 +33,7 @@ FUNCTION_ENTRY(_CPU_Context_volatile_clobber)
#ifdef ARM_MULTILIB_VFP
vmrs r1, FPSCR
ldr r2, =0xf800001f
ldr r2, =0xf000001f
bic r1, r1, r2
and r2, r2, r0
orr r1, r1, r2