Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
Skip the data cache initialization if we are a secondary processor.
The bug was introduced by e164df5e33 and
did not show up in tests using Qemu since the data cache behaviour is
not emulated.
Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector
numbers start with zero.
The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit
and building all BSPs.
Update #3269.
Set the Main Stack Pointer (MSP) to the ISR stack area end just in case
we run using the Process Stack Pointer (PSP). This helps if
applications are started by a boot loader.
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
Use the targets parameter to determine the targets of the SGI. Change
targets parameter type to 32-bit to ease the parameter passing. GICv3
supports up to 16 targets.
Update #4202.
This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.
Close#4068.
_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().
Closes#3961.
At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.
Place idle and MPCI stacks into extra linker sections. This can be
optionally used by applications to control the placement of the stacks.
Update #3835.
This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
