In combination with the PPC_EXC_CONFIG_USE_FIXED_HANDLER option this
removes all dependencies on valid read-write data. The exception
handling must be statically configured and all components reside in
read-only sections.
In case a BSP enables this option, then fixed high level exception
handler will be used. For normal asynchronous exceptions this is
bsp_interrupt_dispatch() and for other exceptions this is the handler
from the read-only ppc_exc_handler_table. The global handler is
C_exception_handler(). This avoids some dependencies on valid
read-write data.
The Machine Check and Exception Syndrome Registers on Book-E and Book-E-like
processors contain useful information for decoding the cause of an exception.
NB: This patch depends on the PR 2048 patch sent earlier having been applied.
This BSP now uses the MPC6xx clock driver instead of a modified PPC403 clock
driver. Support for the MMU has been added, but is not enabled by default.
This file was originally modified by me to support the PPC440 of the virtex5
BSP. I have since discovered that the clock driver built with the MVME3100
BSP works out of the box for the virtex5 and so have switched to using that.
This file is reverted to the way it was before I touched it, modulo whitespace,
making some functions static (to avoid compiler warnings) and changes by others.
Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().
The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().
Add rtems_exception_frame and rtems_exception_frame_print().
Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.
Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().
Add test sptests/spfatal26.
Add ppc_exc_print_frame_and_context() which prints an exception frame
and the context via printk().
The global exception handler will call now rtems_fatal() with source
RTEMS_FATAL_SOURCE_POWERPC_EXCEPTION. The fatal code will contain the
pointer value to the exception frame.
PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
These modifications were required by hand after running the script.
In some cases, the file names did not match patterns. In others,
the format of the file did not match any common patterns.
