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Code Pull Requests Activity
33,088 Commits 7 Branches 54 Tags
b51a1d07d007c665eda450ee48fc9b9d80e41251
Commit Graph

623 Commits

Author SHA1 Message Date
Sebastian Huber
3d11c1e2af bsp/riscv: Fix a synchronization issue for PLIC 
Update #3433.
 2018-08-02 09:28:23 +02:00
Sebastian Huber
dee2ebbaa6 bsp/riscv: Remove unused variable 
Update #3433.
 2018-08-01 11:15:55 +02:00
Sebastian Huber
56b0387d2f bsp/riscv: Add NS16750 support to console driver 
Update #3433.
 2018-08-01 11:15:14 +02:00
Sebastian Huber
a7cd4b737c serial/ns16550: Precision clock synthesizer 
Set the FIFO control register while DLAB == 1 in the line control
register.  At least on the QorIQ T4240 the driver still works with the
re-ordered FIFO control register access.
 2018-08-01 11:13:58 +02:00
Sebastian Huber
8a78b784c4 serial/ns16550: Use standard register names 
Use the standard register names for the divisor latches.  This makes it
easier to compare the code with other driver implementations.
 2018-08-01 10:08:59 +02:00
Sebastian Huber
529154bad2 bsp/riscv: Initialize FPU depending on ISA 
Initialize fcsr to zero for a defined rounding mode.

Update #3433.
 2018-08-01 10:08:59 +02:00
Sebastian Huber
48cbd63c84 bsp/riscv: Fix clock driver 
Do not assume that mtime is zero at boot time.

Update #3433.
 2018-08-01 10:07:18 +02:00
Sebastian Huber
71284ce893 bsps/sparc: Fix typo in start.S 
Fix typo in start.S introduced by
4678d1a8b0.
 2018-08-01 10:07:18 +02:00
Sebastian Huber
44c2d393bd bsp/riscv: Fix inter-processor interrupts 
The previous version worked only on a patched Qemu.  Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
cfc95736ff riscv: Rework CPU counter support 
Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
581a0f8866 bsp/riscv: Use interrupt driven NS16550 driver 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
adede135e7 bsp/riscv: Add PLIC support 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
bd5603868a bsp/riscv: Add simple SMP support to clock driver 
This is a hack.  The clock interrupt should be handled by each hart.

Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6552ba8c37 bsp/riscv: Use CPU counter btimer 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
447fd894ae bsp/riscv: Add basic SMP startup 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6b9ef097c3 riscv: Add CLINT and PLIC support 
The CLINT and PLIC need some per-processor state.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
f5fd8eb9e3 bsps/riscv: Update linker-symbols.h 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
dda6e06edb bsp/riscv: Add reset via for SiFive Test Finisher 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
3a263a9b02 bsp/riscv: Add and use riscv_fdt_get_address() 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
7fe48551a2 bsp/riscv: Fix HTIF warnings 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
8db3f0e878 riscv: Rework exception handling 
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions.  Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
406dd62c99 _SMP_Start_multitasking_on_secondary_processor() 
Pass current processor control as first parameter to make dependency
more explicit.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
4678d1a8b0 bsps: bsp_start_on_secondary_processor() 
Pass current processor control as first parameter in
bsp_start_on_secondary_processor() and qoriq_start_thread() to make
dependency more explicit.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
0d362ff397 score: _SMP_Inter_processor_interrupt_handler() 
Pass current processor control via parameter since it may be already
available at the caller side.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
caccc5bfc6 bsps: Fix function declaration warnings 2018-07-24 13:00:56 +02:00
Sebastian Huber
61c51dbb18 bsp/beagle: Fix warnings 2018-07-24 09:11:08 +02:00
Sebastian Huber
1b57b7527a bsp/realview-pbx-a9: Support unassigned processors 2018-07-18 07:16:26 +02:00
Amaan Cheval
cf811a4eb2 x86_64/console: Add NS16550 polled console driver 
This addition allows us to successfully run the sample hello.exe test.

Updates #2898.
 2018-07-11 15:23:43 -05:00
Amaan Cheval
76c03152e1 bsp/x86_64: Minimal bootable BSP 
Current state:

  - Basic context initialization and switching code.
  - Stubbed console (empty functions).
  - Mostly functional linker script (may need tweaks if we ever want to move
    away from the large code model (see: CPU_CFLAGS).
  - Fully functional boot, by using FreeBSD's bootloader to load RTEMS's ELF for
    UEFI-awareness.

In short, the current state with this commit lets us boot, go through the system
initialization functions, and then call user application's Init task too.

Updates #2898.
 2018-07-11 15:22:44 -05:00
Sebastian Huber
1a192398bf bsp/riscv: Add console support for NS16550 devices 
Update #3433.
 2018-07-06 14:27:39 +02:00
Sebastian Huber
31f90a2ff4 bsp/riscv: Simplify printk() support 
This is a prepartion to add NS16550 driver support to the console
driver.

Update #3433.
 2018-07-06 14:27:29 +02:00
Sebastian Huber
bca36d986b riscv: Add LADDR assembler define 
An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
dd32e2b2d0 riscv: Implement CPU counter 
Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
fc5cc9af10 bsps/arm: Include missing header file 2018-07-05 08:54:57 +02:00
Sebastian Huber
d3dff40e5e bsps: Update headers.am 2018-07-05 07:26:49 +02:00
Sebastian Huber
0fd8287b2b riscv: Add _CPU_Get_current_per_CPU_control() 
Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
3be4478f5a riscv: Avoid namespace pollution 
Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).

Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
ff7b10479b bsp/riscv: Remove bsp_interrupt_handler_default() 
It duplicated the default implementation.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
cdfed94f34 bsp/riscv: Rework clock driver 
Use device tree provided timebase frequency.  Do not write to read-only
mtime register.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
1232cd4690 bsp/riscv: Add device tree support for console 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
c558cc4b00 bsp/riscv: Fix vector table for lp64 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
5f5c450aa4 bsp/riscv: Add SMP startup synchronization 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
fe2cd01ba7 bsp/riscv: Add device tree support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
2086948a7b riscv: Add dummy SMP support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
9b2ef07f4b bsp/riscv: Load global pointer 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
b0ee7894d7 bsp/riscv: Use memset() to clear .bss 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
52f4fb65b3 riscv: Format assembler files 
Use tabs to match the GCC generated assembler output.

Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
fef0a414cf bsp/riscv: Do not clear integer registers at start 
There is no need to do this.

Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
380243627b bsp/riscv: Fix some warnings 
Update #3444.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
16d905f289 bsp/riscv: Add BSP options to define RAM region 
Update #3433.
 2018-06-27 08:58:17 +02:00