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riscv: Format assembler files

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Use tabs to match the GCC generated assembler output.

Update #3433.
This commit is contained in:
Sebastian Huber
2018-06-26 07:48:06 +02:00
parent fef0a414cf
commit 52f4fb65b3
5 changed files with 424 additions and 419 deletions
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69
bsps/riscv/riscv/start/start.S
View File

@@ -26,6 +26,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <bsp/linker-symbols.h>
#include <rtems/score/riscv-utility.h>
#include <rtems/score/cpu.h>
@@ -40,48 +41,50 @@ PUBLIC(bsp_start_vector_table_begin)
PUBLIC(bsp_start_vector_table_end)
PUBLIC(_start)
.section .bsp_start_text, "wax"
.section .bsp_start_text, "ax", @progbits
.align 2
TYPE_FUNC(_start)
SYM(_start):
la t0, ISR_Handler
csrw mtvec, t0
la t0, ISR_Handler
csrw mtvec, t0
/* load stack and frame pointers */
la sp, _Configuration_Interrupt_stack_area_end
/* load stack and frame pointers */
la sp, _Configuration_Interrupt_stack_area_end
/* Clearing .bss */
la t0, bsp_section_bss_begin
la t1, bsp_section_bss_end
/* Clearing .bss */
la t0, bsp_section_bss_begin
la t1, bsp_section_bss_end
_loop_clear_bss:
bge t0, t1, _end_clear_bss
SREG x0, 0(t0)
addi t0, t0, CPU_SIZEOF_POINTER
j _loop_clear_bss
bge t0, t1, _end_clear_bss
SREG x0, 0(t0)
addi t0, t0, CPU_SIZEOF_POINTER
j _loop_clear_bss
_end_clear_bss:
/* Init FPU unit if it's there */
li t0, MSTATUS_FS
csrs mstatus, t0
/* Init FPU unit if it's there */
li t0, MSTATUS_FS
csrs mstatus, t0
j boot_card
j boot_card
.align 4
.align 4
bsp_start_vector_table_begin:
.word _RISCV_Exception_default /* User int */
.word _RISCV_Exception_default /* Supervisor int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine int */
.word _RISCV_Exception_default /* User timer int */
.word _RISCV_Exception_default /* Supervisor Timer int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine Timer int */
.word _RISCV_Exception_default /* User external int */
.word _RISCV_Exception_default /* Supervisor external int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine external int */
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default /* User int */
.word _RISCV_Exception_default /* Supervisor int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine int */
.word _RISCV_Exception_default /* User timer int */
.word _RISCV_Exception_default /* Supervisor Timer int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine Timer int */
.word _RISCV_Exception_default /* User external int */
.word _RISCV_Exception_default /* Supervisor external int */
.word _RISCV_Exception_default /* Reserved */
.word _RISCV_Exception_default /* Machine external int */
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
.word _RISCV_Exception_default
bsp_start_vector_table_end:

164
cpukit/score/cpu/riscv/riscv-context-switch.S
View File

@@ -33,8 +33,8 @@
#include <rtems/asm.h>
#include <rtems/score/cpu.h>
.section .text, "ax"
.align 4
.section .text, "ax", @progbits
.align 2
PUBLIC(_CPU_Context_switch)
PUBLIC(_CPU_Context_restore)
@@ -43,94 +43,94 @@ PUBLIC(_CPU_Context_save_fp)
PUBLIC(restore)
SYM(_CPU_Context_switch):
/* Disable interrupts and store all registers */
csrr t0, mstatus
SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
/* Disable interrupts and store all registers */
csrr t0, mstatus
SREG t0, (32 * CPU_SIZEOF_POINTER)(a0)
csrci mstatus, MSTATUS_MIE
csrci mstatus, MSTATUS_MIE
SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
SREG x1, (1 * CPU_SIZEOF_POINTER)(a0)
SREG x2, (2 * CPU_SIZEOF_POINTER)(a0)
SREG x3, (3 * CPU_SIZEOF_POINTER)(a0)
SREG x4, (4 * CPU_SIZEOF_POINTER)(a0)
SREG x5, (5 * CPU_SIZEOF_POINTER)(a0)
SREG x6, (6 * CPU_SIZEOF_POINTER)(a0)
SREG x7, (7 * CPU_SIZEOF_POINTER)(a0)
SREG x8, (8 * CPU_SIZEOF_POINTER)(a0)
SREG x9, (9 * CPU_SIZEOF_POINTER)(a0)
SREG x10, (10 * CPU_SIZEOF_POINTER)(a0)
SREG x11, (11 * CPU_SIZEOF_POINTER)(a0)
SREG x12, (12 * CPU_SIZEOF_POINTER)(a0)
SREG x13, (13 * CPU_SIZEOF_POINTER)(a0)
SREG x14, (14 * CPU_SIZEOF_POINTER)(a0)
SREG x15, (15 * CPU_SIZEOF_POINTER)(a0)
SREG x16, (16 * CPU_SIZEOF_POINTER)(a0)
SREG x17, (17 * CPU_SIZEOF_POINTER)(a0)
SREG x18, (18 * CPU_SIZEOF_POINTER)(a0)
SREG x19, (19 * CPU_SIZEOF_POINTER)(a0)
SREG x20, (20 * CPU_SIZEOF_POINTER)(a0)
SREG x21, (21 * CPU_SIZEOF_POINTER)(a0)
SREG x22, (22 * CPU_SIZEOF_POINTER)(a0)
SREG x23, (23 * CPU_SIZEOF_POINTER)(a0)
SREG x24, (24 * CPU_SIZEOF_POINTER)(a0)
SREG x25, (25 * CPU_SIZEOF_POINTER)(a0)
SREG x26, (26 * CPU_SIZEOF_POINTER)(a0)
SREG x27, (27 * CPU_SIZEOF_POINTER)(a0)
SREG x28, (28 * CPU_SIZEOF_POINTER)(a0)
SREG x29, (28 * CPU_SIZEOF_POINTER)(a0)
SREG x30, (30 * CPU_SIZEOF_POINTER)(a0)
SREG x31, (31 * CPU_SIZEOF_POINTER)(a0)
SYM(restore):
SYM(restore):
LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
/* Skip a1/x11 */
LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
LREG x1, (1 * CPU_SIZEOF_POINTER)(a1)
LREG x2, (2 * CPU_SIZEOF_POINTER)(a1)
LREG x3, (3 * CPU_SIZEOF_POINTER)(a1)
LREG x4, (4 * CPU_SIZEOF_POINTER)(a1)
LREG x5, (5 * CPU_SIZEOF_POINTER)(a1)
LREG x6, (6 * CPU_SIZEOF_POINTER)(a1)
LREG x7, (7 * CPU_SIZEOF_POINTER)(a1)
LREG x8, (8 * CPU_SIZEOF_POINTER)(a1)
LREG x9, (9 * CPU_SIZEOF_POINTER)(a1)
LREG x10, (10 * CPU_SIZEOF_POINTER)(a1)
/* Skip a1/x11 */
LREG x12, (12 * CPU_SIZEOF_POINTER)(a1)
LREG x13, (13 * CPU_SIZEOF_POINTER)(a1)
LREG x14, (14 * CPU_SIZEOF_POINTER)(a1)
LREG x15, (15 * CPU_SIZEOF_POINTER)(a1)
LREG x16, (16 * CPU_SIZEOF_POINTER)(a1)
LREG x17, (17 * CPU_SIZEOF_POINTER)(a1)
LREG x18, (18 * CPU_SIZEOF_POINTER)(a1)
LREG x19, (19 * CPU_SIZEOF_POINTER)(a1)
LREG x20, (20 * CPU_SIZEOF_POINTER)(a1)
LREG x21, (21 * CPU_SIZEOF_POINTER)(a1)
LREG x22, (22 * CPU_SIZEOF_POINTER)(a1)
LREG x23, (23 * CPU_SIZEOF_POINTER)(a1)
LREG x24, (24 * CPU_SIZEOF_POINTER)(a1)
LREG x25, (25 * CPU_SIZEOF_POINTER)(a1)
LREG x26, (26 * CPU_SIZEOF_POINTER)(a1)
LREG x27, (27 * CPU_SIZEOF_POINTER)(a1)
LREG x28, (28 * CPU_SIZEOF_POINTER)(a1)
LREG x29, (29 * CPU_SIZEOF_POINTER)(a1)
LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
/* Load mstatus */
LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
csrw mstatus, x31
/* Load mstatus */
LREG x31, (32 * CPU_SIZEOF_POINTER)(a1)
csrw mstatus, x31
LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
LREG x30, (30 * CPU_SIZEOF_POINTER)(a1)
LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
LREG x11, (11 * CPU_SIZEOF_POINTER)(a1)
ret
ret
SYM(_CPU_Context_restore):
mv a1, a0
j restore
SYM(_CPU_Context_restore):
mv a1, a0
j restore
/* TODO no FP support for riscv32 yet */
SYM(_CPU_Context_restore_fp):
nop
/* TODO no FP support for riscv32 yet */
SYM(_CPU_Context_restore_fp):
nop
SYM(_CPU_Context_save_fp):
nop
SYM(_CPU_Context_save_fp):
nop

296
cpukit/score/cpu/riscv/riscv-context-validate.S
View File

@@ -30,171 +30,171 @@
#include <rtems/asm.h>
#include <rtems/score/cpu.h>
.section .text
.section .text, "ax", @progbits
.align 2
PUBLIC(_CPU_Context_validate)
SYM(_CPU_Context_validate):
/* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
/* RISC-V/RTEMS context has 36 registers of CPU_SIZEOF_POINTER size */
addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip x2/sp */
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip x2/sp */
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
/* Fill */
/* Fill */
/* t0 is used for temporary values */
mv t0, x0
/* t0 is used for temporary values */
mv t0, x0
/* x31 contains the stack pointer */
mv x31, sp
/* x31 contains the stack pointer */
mv x31, sp
.macro fill_register reg
addi t0, t0, 1
mv \reg, t0
.endm
.macro fill_register reg
addi t0, t0, 1
mv \reg, t0
.endm
fill_register x1
fill_register x2
fill_register x3
fill_register x4
fill_register x5
fill_register x6
fill_register x7
fill_register x8
fill_register x9
fill_register x10
fill_register x11
fill_register x12
fill_register x13
fill_register x14
fill_register x15
fill_register x16
fill_register x17
fill_register x18
fill_register x19
fill_register x20
fill_register x21
fill_register x22
fill_register x23
fill_register x24
fill_register x25
fill_register x26
fill_register x27
fill_register x28
fill_register x29
fill_register x30
fill_register x31
fill_register x1
fill_register x2
fill_register x3
fill_register x4
fill_register x5
fill_register x6
fill_register x7
fill_register x8
fill_register x9
fill_register x10
fill_register x11
fill_register x12
fill_register x13
fill_register x14
fill_register x15
fill_register x16
fill_register x17
fill_register x18
fill_register x19
fill_register x20
fill_register x21
fill_register x22
fill_register x23
fill_register x24
fill_register x25
fill_register x26
fill_register x27
fill_register x28
fill_register x29
fill_register x30
fill_register x31
/* Check */
/* Check */
check:
.macro check_register reg
addi t0, t0, 1
bne \reg, t0, restore
.endm
.macro check_register reg
addi t0, t0, 1
bne \reg, t0, restore
.endm
bne x31, sp, restore
bne x31, sp, restore
mv t0, x0
mv t0, x0
check_register x1
check_register x2
check_register x3
check_register x4
check_register x5
check_register x6
check_register x7
check_register x8
check_register x9
check_register x10
check_register x11
check_register x12
check_register x13
check_register x14
check_register x15
check_register x16
check_register x17
check_register x18
check_register x19
check_register x20
check_register x21
check_register x22
check_register x23
check_register x24
check_register x25
check_register x26
check_register x27
check_register x28
check_register x29
check_register x30
check_register x31
check_register x1
check_register x2
check_register x3
check_register x4
check_register x5
check_register x6
check_register x7
check_register x8
check_register x9
check_register x10
check_register x11
check_register x12
check_register x13
check_register x14
check_register x15
check_register x16
check_register x17
check_register x18
check_register x19
check_register x20
check_register x21
check_register x22
check_register x23
check_register x24
check_register x25
check_register x26
check_register x27
check_register x28
check_register x29
check_register x30
check_register x31
j check
j check
/* Restore */
/* Restore */
restore:
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip sp/x2 */
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip sp/x2 */
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
addi sp, sp, 36 * CPU_SIZEOF_POINTER
ret
addi sp, sp, 36 * CPU_SIZEOF_POINTER
ret

27
cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S
View File

@@ -29,22 +29,23 @@
#include <rtems/asm.h>
.section .text
.section .text, "ax", @progbits
.align 2
PUBLIC(_CPU_Context_volatile_clobber)
SYM(_CPU_Context_volatile_clobber):
.macro clobber_register reg
addi t0, t0, -1
mv \reg, t0
.endm
.macro clobber_register reg
addi t0, t0, -1
mv \reg, t0
.endm
clobber_register a0
clobber_register a1
clobber_register a2
clobber_register a3
clobber_register a4
clobber_register a5
clobber_register a6
clobber_register a0
clobber_register a1
clobber_register a2
clobber_register a3
clobber_register a4
clobber_register a5
clobber_register a6
ret
ret

287
cpukit/score/cpu/riscv/riscv-exception-handler.S
View File

@@ -45,177 +45,178 @@ EXTERN(bsp_start_vector_table_begin)
EXTERN(_Thread_Dispatch)
PUBLIC(ISR_Handler)
.section .text, "ax"
.align 4
.section .text, "ax", @progbits
.align 2
TYPE_FUNC(ISR_Handler)
SYM(ISR_Handler):
addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip x2/sp */
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
SREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip x2/sp */
SREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
SREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
SREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
SREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
SREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
SREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
SREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
SREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
SREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
SREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
SREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
SREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
SREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
SREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
SREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
SREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
SREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
SREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
SREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
SREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
SREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
SREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
SREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
SREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
SREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
SREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x29, (28 * CPU_SIZEOF_POINTER)(sp)
SREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
SREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
/* Exception level related registers */
csrr a0, mstatus
SREG a0, (32 * CPU_SIZEOF_POINTER)(sp)
csrr a0, mcause
SREG a0, (33 * CPU_SIZEOF_POINTER)(sp)
csrr a1, mepc
SREG a1, (34 * CPU_SIZEOF_POINTER)(sp)
/* Exception level related registers */
csrr a0, mstatus
SREG a0, (32 * CPU_SIZEOF_POINTER)(sp)
csrr a0, mcause
SREG a0, (33 * CPU_SIZEOF_POINTER)(sp)
csrr a1, mepc
SREG a1, (34 * CPU_SIZEOF_POINTER)(sp)
/* FIXME Only handle interrupts for now (MSB = 1) */
andi a0, a0, 0xf
/* FIXME Only handle interrupts for now (MSB = 1) */
andi a0, a0, 0xf
/* Increment nesting level */
la t0, ISR_NEST_LEVEL
/* Increment nesting level */
la t0, ISR_NEST_LEVEL
/* Disable multitasking */
la t1, THREAD_DISPATCH_DISABLE_LEVEL
/* Disable multitasking */
la t1, THREAD_DISPATCH_DISABLE_LEVEL
lw t2, (t0)
lw t3, (t1)
addi t2, t2, 1
addi t3, t3, 1
sw t2, (t0)
sw t3, (t1)
lw t2, (t0)
lw t3, (t1)
addi t2, t2, 1
addi t3, t3, 1
sw t2, (t0)
sw t3, (t1)
/* Save interrupted task stack pointer */
addi t4, sp, 36 * CPU_SIZEOF_POINTER
SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
/* Save interrupted task stack pointer */
addi t4, sp, 36 * CPU_SIZEOF_POINTER
SREG t4, (2 * CPU_SIZEOF_POINTER)(sp)
/* Keep sp (Exception frame address) in s1 */
mv s1, sp
/* Keep sp (Exception frame address) in s1 */
mv s1, sp
/* Call the exception handler from vector table */
/* Call the exception handler from vector table */
/* First function arg for C handler is vector number,
* and the second is a pointer to exception frame.
* a0/mcause/vector number is already loaded above */
mv a1, sp
/* First function arg for C handler is vector number,
* and the second is a pointer to exception frame.
* a0/mcause/vector number is already loaded above */
mv a1, sp
/* calculate the offset */
la t5, bsp_start_vector_table_begin
#if __riscv_xlen == 32
slli t6, a0, 2
#else /* xlen = 64 */
slli t6, a0, 3
/* calculate the offset */
la t5, bsp_start_vector_table_begin
#if __riscv_xlen == 32
slli t6, a0, 2
#else /* xlen = 64 */
slli t6, a0, 3
#endif
add t5, t5, t6
LREG t5, (t5)
add t5, t5, t6
LREG t5, (t5)
/* Do not switch stacks if we are in a nested interrupt. At
* this point t2 should be holding ISR_NEST_LEVEL value.
*/
li s0, 1
bgtu t2, s0, jump_to_c_handler
/* Do not switch stacks if we are in a nested interrupt. At
* this point t2 should be holding ISR_NEST_LEVEL value.
*/
li s0, 1
bgtu t2, s0, jump_to_c_handler
/* Switch to RTEMS dedicated interrupt stack */
la sp, INTERRUPT_STACK_HIGH
LREG sp, (sp)
/* Switch to RTEMS dedicated interrupt stack */
la sp, INTERRUPT_STACK_HIGH
LREG sp, (sp)
jump_to_c_handler:
jalr t5
jalr t5
/* Switch back to the interrupted task stack */
mv sp, s1
/* Switch back to the interrupted task stack */
mv sp, s1
/* Decrement nesting level */
la t0, ISR_NEST_LEVEL
/* Decrement nesting level */
la t0, ISR_NEST_LEVEL
/* Enable multitasking */
la t1, THREAD_DISPATCH_DISABLE_LEVEL
/* Enable multitasking */
la t1, THREAD_DISPATCH_DISABLE_LEVEL
Lw t2, (t0)
lw t3, (t1)
addi t2, t2, -1
addi t3, t3, -1
sw t2, (t0)
sw t3, (t1)
Lw t2, (t0)
lw t3, (t1)
addi t2, t2, -1
addi t3, t3, -1
sw t2, (t0)
sw t3, (t1)
/* Check if _ISR_Nest_level > 0 */
bgtz t2, exception_frame_restore
/* Check if _ISR_Nest_level > 0 */
bgtz t2, exception_frame_restore
/* Check if _Thread_Dispatch_disable_level > 0 */
bgtz t3, exception_frame_restore
/* Check if _Thread_Dispatch_disable_level > 0 */
bgtz t3, exception_frame_restore
/* Check if dispatch needed */
la x31, DISPATCH_NEEDED
lw x31, (x31)
beqz x31, exception_frame_restore
/* Check if dispatch needed */
la x31, DISPATCH_NEEDED
lw x31, (x31)
beqz x31, exception_frame_restore
la x31, _Thread_Dispatch
jalr x31
la x31, _Thread_Dispatch
jalr x31
SYM(exception_frame_restore):
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip sp/x2 */
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
SYM(exception_frame_restore):
LREG x1, (1 * CPU_SIZEOF_POINTER)(sp)
/* Skip sp/x2 */
LREG x3, (3 * CPU_SIZEOF_POINTER)(sp)
LREG x4, (4 * CPU_SIZEOF_POINTER)(sp)
LREG x5, (5 * CPU_SIZEOF_POINTER)(sp)
LREG x6, (6 * CPU_SIZEOF_POINTER)(sp)
LREG x7, (7 * CPU_SIZEOF_POINTER)(sp)
LREG x8, (8 * CPU_SIZEOF_POINTER)(sp)
LREG x9, (9 * CPU_SIZEOF_POINTER)(sp)
LREG x10, (10 * CPU_SIZEOF_POINTER)(sp)
LREG x11, (11 * CPU_SIZEOF_POINTER)(sp)
LREG x12, (12 * CPU_SIZEOF_POINTER)(sp)
LREG x13, (13 * CPU_SIZEOF_POINTER)(sp)
LREG x14, (14 * CPU_SIZEOF_POINTER)(sp)
LREG x15, (15 * CPU_SIZEOF_POINTER)(sp)
LREG x16, (16 * CPU_SIZEOF_POINTER)(sp)
LREG x17, (17 * CPU_SIZEOF_POINTER)(sp)
LREG x18, (18 * CPU_SIZEOF_POINTER)(sp)
LREG x19, (19 * CPU_SIZEOF_POINTER)(sp)
LREG x20, (20 * CPU_SIZEOF_POINTER)(sp)
LREG x21, (21 * CPU_SIZEOF_POINTER)(sp)
LREG x22, (22 * CPU_SIZEOF_POINTER)(sp)
LREG x23, (23 * CPU_SIZEOF_POINTER)(sp)
LREG x24, (24 * CPU_SIZEOF_POINTER)(sp)
LREG x25, (25 * CPU_SIZEOF_POINTER)(sp)
LREG x26, (26 * CPU_SIZEOF_POINTER)(sp)
LREG x27, (27 * CPU_SIZEOF_POINTER)(sp)
LREG x28, (28 * CPU_SIZEOF_POINTER)(sp)
LREG x29, (29 * CPU_SIZEOF_POINTER)(sp)
LREG x30, (30 * CPU_SIZEOF_POINTER)(sp)
/* Load mstatus */
LREG x31, (32 * CPU_SIZEOF_POINTER)(sp)
csrw mstatus, x31
/* Load mepc */
LREG x31, (34 * CPU_SIZEOF_POINTER)(sp)
csrw mepc, x31
/* Load mstatus */
LREG x31, (32 * CPU_SIZEOF_POINTER)(sp)
csrw mstatus, x31
/* Load mepc */
LREG x31, (34 * CPU_SIZEOF_POINTER)(sp)
csrw mepc, x31
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
LREG x31, (31 * CPU_SIZEOF_POINTER)(sp)
/* Unwind exception frame */
addi sp, sp, 36 * CPU_SIZEOF_POINTER
/* Unwind exception frame */
addi sp, sp, 36 * CPU_SIZEOF_POINTER
mret
mret