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bsp/riscv: Add reset via for SiFive Test Finisher

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Update #3433.
This commit is contained in:
Sebastian Huber
2018-07-19 14:45:47 +02:00
parent 3a263a9b02
commit dda6e06edb
1 changed files with 18 additions and 5 deletions
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23
bsps/riscv/riscv/start/bsp_fatal_halt.c
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@@ -1,8 +1,8 @@
/* @ingroup riscv_generic
* @brief riscv_generic BSP Fatal_halt handler.
/*
* Copyright (c) 2018 embedded brains GmbH
*
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -27,14 +27,27 @@
*/
#include <bsp/riscv.h>
#include <bsp/fdt.h>
#include <libfdt.h>
void _CPU_Fatal_halt(uint32_t source, uint32_t error)
{
const char *fdt;
int node;
volatile uintptr_t *sifive_test;
#if RISCV_ENABLE_HTIF_SUPPORT != 0
htif_poweroff();
#endif
fdt = bsp_fdt_get();
node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0");
sifive_test = riscv_fdt_get_address(fdt, node);
while (true) {
/* Do nothing */
if (sifive_test != NULL) {
*sifive_test = 0x5555;
}
}
}