Separate the Interrupt Manager implementation from the generic Arm GICv3
support. Move parts of the Arm GICv3 support into a new header file. This
helps to support systems with a clustered structure in which multiple GICv3
instances are present. For example, two clusters of two Cortex-R52 cores where
each cluster has a dedicated GICv3 instance.
Most BSPs which used the stubbed benachmark timer provide a CPU counter.
All BSPs provide at least a stub CPU counter. Simply use the benchmark
timer implementation using the CPU counter.
Always start the executive in Exception Level 1, Non-Secure mode.
If we boot in EL3 Secure with GICv3 then we have to initialize
the distributor and redistributor to set up G1NS interrupts
early in the boot sequence before stepping down from EL3S to EL1NS.
Now there is no need to distinguish between secure and non-secure
world execution after the primary core boots, so get rid of the
AARCH64_IS_NONSECURE configuration option.
ARM's GICv2 is configurable and its attributes vary between
implementations including omission of specific interrupts. This allows
BSPs to accomodate those varying implementations with customized
attribute sets.
Certain files related to the Zynq BSP's I2C driver are useable by the ZynqMP BSP as well.
Moved these files to shared directory in anticipation of I2C support for ZynqMP.
Do not return a status code in bsp_interrupt_facility_initialize() since this
leads to unreachable code in bsp_interrupt_initialize(). Use RTEMS_DEBUG
assertions in bsp_interrupt_facility_initialize() if necessary.
Add rtems_interrupt_raise_on() and rtems_interrupt_clear().
Add a default implementation which just returns RTEMS_UNSATISFIED for
valid parameters.
Update #3269.
The GICv3 support is shared between AArch32 and AArch64. For AArch32,
the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4
instead.
This issue was introduced by 76c6caad52.
There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52.
The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
Add a parameter to _TOD_Validate() to disable the validation of the
ticks member.
There are two reasons for this change. Firstly, in
rtems_task_wake_when() was a double check for time_buffer == NULL (one
in rtems_task_wake_when() and one in _TOD_Validate()). Secondly, the
ticks member is ignored by rtems_task_wake_when(). This was done with a
write of zero to the ticks member and thus a modification of the
user-provided structure. Now the structure is no longer modified.
Using a mask parameter is quite efficient. You just have to load an
immediate value and there are no additional branches in _TOD_Validate().
Close#4406.
This patch fixes bug #4403. Directives
* rtems_timer_fire_when()
* rtems_timer_server_fire_when()
* rtems_task_wake_when()
are documented to return RTEMS_INVALID_ADDRESS when their time-of-day
argument is NULL. But actually they return RTEMS_INVALID_CLOCK. To fix
the issue this patch changes _TOD_Validate() to return a
status code instead of just true/false.
Close#4403
Constantly reinitializing the Cadence UART on every character output
causes data corruption/loss on some ZynqMP hardware. Only initialize
the UART once for early output and give it a kick on startup.
Note: The changes have been done with portability in mind. The driver
should (in theory) be able to replace the original one in the MPC BSPs
too. For full compatibility an adaption layer and especially a test
would be necessary. Because both are missing, don't integrate it into
the MPC BSP now.
Update #4180
