forked from Imagelibrary/rtems
bsps: Add <dev/irq/arm-gicv3.h>
Separate the Interrupt Manager implementation from the generic Arm GICv3 support. Move parts of the Arm GICv3 support into a new header file. This helps to support systems with a clustered structure in which multiple GICv3 instances are present. For example, two clusters of two Cortex-R52 cores where each cluster has a dedicated GICv3 instance.
This commit is contained in:
Sebastian Huber
162
bsps/include/dev/irq/arm-gicv3.h
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162
bsps/include/dev/irq/arm-gicv3.h
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@@ -0,0 +1,162 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup arm_gic
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*
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* @brief This header file contains interfaces to access an Arm GICv3.
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*/
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/*
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* Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTEMS_DEV_IRQ_ARM_GICV3_H
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#define _RTEMS_DEV_IRQ_ARM_GICV3_H
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#include <dev/irq/arm-gic.h>
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#include <dev/irq/arm-gic-arch.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PRIORITY_DEFAULT 127
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#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
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#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
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#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
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#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
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#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
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#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
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#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
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#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
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#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
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#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
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#define ICC_SGIR_IRM BSP_BIT32(40)
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#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
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#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
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#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
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#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
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#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
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#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
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#ifdef ARM_MULTILIB_ARCH_V4
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/* cpuif->iccicr */
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#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
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/* cpuif->iccpmr */
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#define ICC_PMR "p15, 0, %0, c4, c6, 0"
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/* cpuif->iccbpr */
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#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
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#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
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/* cpuif->icciar */
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#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
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#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
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/* cpuif->icceoir */
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#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
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#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
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#define ICC_SRE "p15, 0, %0, c12, c12, 5"
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#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
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#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
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#define MPIDR "p15, 0, %0, c0, c0, 5"
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#define READ_SR(SR_NAME) \
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({ \
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uint32_t value; \
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__asm__ volatile("mrc " SR_NAME : "=r" (value) ); \
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value; \
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})
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#define WRITE_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) );
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#define ICC_SGI1 "p15, 0, %Q0, %R0, c12"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) );
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#else /* ARM_MULTILIB_ARCH_V4 */
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/* AArch64 GICv3 registers are not named in GCC */
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#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
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#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
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#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
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#define ICC_PMR "S3_0_C4_C6_0, %0"
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#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
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#define ICC_SRE "S3_0_C12_C12_5, %0"
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#define ICC_BPR0 "S3_0_C12_C8_3, %0"
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#define ICC_CTLR "S3_0_C12_C12_4, %0"
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#define ICC_IAR1 "%0, S3_0_C12_C12_0"
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#define MPIDR "%0, mpidr_el1"
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#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
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#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGI1 "S3_0_C12_C11_5, %0"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );
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#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
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#define READ_SR(SR_NAME) \
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({ \
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uint64_t value; \
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__asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \
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value; \
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})
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#endif /* ARM_MULTILIB_ARCH_V4 */
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static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
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{
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return (volatile gic_redist *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
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}
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static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
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{
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return (volatile gic_sgi_ppi *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTEMS_DEV_IRQ_ARM_GICV3_H */
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@@ -25,132 +25,12 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dev/irq/arm-gic.h>
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#include <dev/irq/arm-gic-arch.h>
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#include <dev/irq/arm-gicv3.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <bsp/start.h>
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#ifdef ARM_MULTILIB_ARCH_V4
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#include <rtems/score/armv4.h>
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#else
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#include <rtems/score/cpu_irq.h>
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#endif
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#define PRIORITY_DEFAULT 127
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#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
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#define MPIDR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define MPIDR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define MPIDR_AFFINITY1(val) BSP_FLD64(val, 8, 15)
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#define MPIDR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 8, 15)
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#define MPIDR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 8, 15)
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#define MPIDR_AFFINITY0(val) BSP_FLD64(val, 0, 7)
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#define MPIDR_AFFINITY0_GET(reg) BSP_FLD64GET(reg, 0, 7)
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#define MPIDR_AFFINITY0_SET(reg, val) BSP_FLD64SET(reg, val, 0, 7)
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#define ICC_SGIR_AFFINITY3(val) BSP_FLD64(val, 48, 55)
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#define ICC_SGIR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 48, 55)
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#define ICC_SGIR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 48, 55)
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#define ICC_SGIR_IRM BSP_BIT32(40)
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#define ICC_SGIR_AFFINITY2(val) BSP_FLD64(val, 32, 39)
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#define ICC_SGIR_AFFINITY2_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define ICC_SGIR_AFFINITY2_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGIR_INTID(val) BSP_FLD64(val, 24, 27)
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#define ICC_SGIR_INTID_GET(reg) BSP_FLD64GET(reg, 24, 27)
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#define ICC_SGIR_INTID_SET(reg, val) BSP_FLD64SET(reg, val, 24, 27)
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#define ICC_SGIR_AFFINITY1(val) BSP_FLD64(val, 16, 23)
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#define ICC_SGIR_AFFINITY1_GET(reg) BSP_FLD64GET(reg, 16, 23)
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#define ICC_SGIR_AFFINITY1_SET(reg, val) BSP_FLD64SET(reg, val, 16, 23)
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#define ICC_SGIR_CPU_TARGET_LIST(val) BSP_FLD64(val, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD64GET(reg, 0, 15)
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#define ICC_SGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD64SET(reg, val, 0, 15)
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#ifdef ARM_MULTILIB_ARCH_V4
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/* cpuif->iccicr */
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#define ICC_CTLR "p15, 0, %0, c12, c12, 4"
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/* cpuif->iccpmr */
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#define ICC_PMR "p15, 0, %0, c4, c6, 0"
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/* cpuif->iccbpr */
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#define ICC_BPR0 "p15, 0, %0, c12, c8, 3"
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#define ICC_BPR1 "p15, 0, %0, c12, c12, 3"
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/* cpuif->icciar */
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#define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
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#define ICC_IAR1 "p15, 0, %0, c12, c12, 0"
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/* cpuif->icceoir */
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#define ICC_EOIR0 "p15, 0, %0, c12, c8, 1"
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#define ICC_EOIR1 "p15, 0, %0, c12, c12, 1"
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#define ICC_SRE "p15, 0, %0, c12, c12, 5"
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#define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
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#define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
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#define MPIDR "p15, 0, %0, c0, c0, 5"
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#define READ_SR(SR_NAME) \
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({ \
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uint32_t value; \
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__asm__ volatile("mrc " SR_NAME : "=r" (value) ); \
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value; \
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})
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#define WRITE_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcr " SR_NAME " \n" : : "r" (VALUE) );
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#define ICC_SGI1 "p15, 0, %Q0, %R0, c12"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("mcrr " SR_NAME " \n" : : "r" (VALUE) );
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#else /* ARM_MULTILIB_ARCH_V4 */
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/* AArch64 GICv3 registers are not named in GCC */
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#define ICC_IGRPEN0 "S3_0_C12_C12_6, %0"
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#define ICC_IGRPEN1 "S3_0_C12_C12_7, %0"
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#define ICC_IGRPEN1_EL3 "S3_6_C12_C12_7, %0"
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#define ICC_PMR "S3_0_C4_C6_0, %0"
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#define ICC_EOIR1 "S3_0_C12_C12_1, %0"
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#define ICC_SRE "S3_0_C12_C12_5, %0"
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#define ICC_BPR0 "S3_0_C12_C8_3, %0"
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#define ICC_CTLR "S3_0_C12_C12_4, %0"
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#define ICC_IAR1 "%0, S3_0_C12_C12_0"
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#define MPIDR "%0, mpidr_el1"
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#define MPIDR_AFFINITY3(val) BSP_FLD64(val, 32, 39)
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#define MPIDR_AFFINITY3_GET(reg) BSP_FLD64GET(reg, 32, 39)
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#define MPIDR_AFFINITY3_SET(reg, val) BSP_FLD64SET(reg, val, 32, 39)
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#define ICC_SGI1 "S3_0_C12_C11_5, %0"
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#define WRITE64_SR(SR_NAME, VALUE) \
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__asm__ volatile("msr " SR_NAME " \n" : : "r" (VALUE) );
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#define WRITE_SR(SR_NAME, VALUE) WRITE64_SR(SR_NAME, VALUE)
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#define READ_SR(SR_NAME) \
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({ \
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uint64_t value; \
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__asm__ volatile("mrs " SR_NAME : "=&r" (value) ); \
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value; \
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})
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#endif /* ARM_MULTILIB_ARCH_V4 */
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static volatile gic_redist *gicv3_get_redist(uint32_t cpu_index)
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{
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return (volatile gic_redist *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000);
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}
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static volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index)
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{
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return (volatile gic_sgi_ppi *)
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((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000);
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}
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void bsp_interrupt_dispatch(void)
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{
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uint32_t icciar = READ_SR(ICC_IAR1);
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@@ -19,6 +19,7 @@ install:
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- bsps/include/dev/irq/arm-gic-regs.h
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- bsps/include/dev/irq/arm-gic-tm27.h
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- bsps/include/dev/irq/arm-gic.h
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- bsps/include/dev/irq/arm-gicv3.h
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- destination: ${BSP_LIBDIR}
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source:
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- bsps/aarch64/shared/start/linkcmds.base
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@@ -42,6 +42,7 @@ install:
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- bsps/include/dev/irq/arm-gic-regs.h
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- bsps/include/dev/irq/arm-gic-tm27.h
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- bsps/include/dev/irq/arm-gic.h
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- bsps/include/dev/irq/arm-gicv3.h
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- destination: ${BSP_INCLUDEDIR}/libcpu
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source:
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- bsps/arm/include/libcpu/am335x.h
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