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35,335 Commits 7 Branches 54 Tags
a52aa5b43feb8ebec1336025ffc59a7c8045b517
Commit Graph

28 Commits

Author SHA1 Message Date
Chris Johns
e70384d3f4 aarch64/gicv3: Remove accesses to secure registers 
RTEMS runs at EL1 and the removed register accesses are for
EL3 or the TF-A. This change aligns our driver with the Linux
and FreeBSD ones.
 2022-06-16 10:21:46 +10:00
Sebastian Huber
0725b200e7 bsps: Add gicv3_get_attributes() 2022-04-06 09:48:52 +02:00
Sebastian Huber
d8b23fa488 bsps: Add gicv3_sgi_ppi_get_priority() 2022-04-06 09:48:52 +02:00
Sebastian Huber
f828ddd1a9 bsps: Add gicv3_sgi_ppi_set_priority() 2022-04-06 09:48:52 +02:00
Sebastian Huber
3026859d41 bsps: Move gicv3_init_cpu_interface() 
Make the processor index a parameter.
 2022-04-06 09:48:52 +02:00
Sebastian Huber
b3519336fd bsps: Move gicv3_init_dist() 
Make the distributor register block a parameter.
 2022-04-06 09:48:52 +02:00
Sebastian Huber
ea353b4bfa bsps: Add gicv3_sgi_ppi_disable() 2022-04-06 09:48:52 +02:00
Sebastian Huber
f74b120c24 bsps: Add gicv3_sgi_ppi_enable() 2022-04-06 09:48:52 +02:00
Sebastian Huber
42c806fc84 bsps: Add gicv3_sgi_ppi_is_enabled() 2022-04-06 09:48:52 +02:00
Sebastian Huber
be25de5ff8 bsps: Add gicv3_ppi_clear_pending() 2022-04-06 09:48:52 +02:00
Sebastian Huber
2e5b1312c8 bsps: Add gicv3_ppi_set_pending() 2022-04-06 09:48:52 +02:00
Sebastian Huber
518330069d bsps: Add gicv3_trigger_sgi() 2022-04-06 09:48:52 +02:00
Sebastian Huber
f10c551f54 bsps: Add gicv3_sgi_ppi_is_pending() 2022-04-06 09:48:52 +02:00
Sebastian Huber
9abcaaebc3 bsps: Add <dev/irq/arm-gicv3.h> 
Separate the Interrupt Manager implementation from the generic Arm GICv3
support.  Move parts of the Arm GICv3 support into a new header file.  This
helps to support systems with a clustered structure in which multiple GICv3
instances are present.  For example, two clusters of two Cortex-R52 cores where
each cluster has a dedicated GICv3 instance.
 2022-04-06 09:48:51 +02:00
Joel Sherrill
fe6d96cc85 bsps/include/: Scripted embedded brains header file clean up 
Updates #4625.
 2022-03-10 08:43:50 +01:00
Sebastian Huber
fe6ce5ac9c bsps/irq: Implement new directives for GICv2/3 
Update #3269.
 2021-07-26 19:57:31 +02:00
Sebastian Huber
85a378510d bsps/irq: bsp_interrupt_set_affinity() 
Return a status code for bsp_interrupt_set_affinity().

Update #3269.
 2021-07-26 19:57:31 +02:00
Sebastian Huber
23ec04c48c bsps/irq: bsp_interrupt_get_affinity() 
Return a status code for bsp_interrupt_get_affinity().

Update #3269.
 2021-07-26 19:57:31 +02:00
Gedare Bloom
fedd279f80 bsps/dev/irq: make icspicfgr an indexable array 2021-06-24 09:37:31 -06:00
Kinsey Moore
2ee12f023d bsps: Allow override of ARM TM27 IRQs 
ZynqMP hardware appears to have an odd hard-wired SGI implementation in
which the SGIs are permanently set as enabled or disabled. Allow the
TM27 IRQs to be overridden as necessary.
 2021-03-05 08:43:15 -06:00
Sebastian Huber
9f3a08ef2d bsps: Use header file for GIC architecture support 
This avoids a function call overhead in the interrupt dispatching.

Update #4202.
 2020-12-23 09:24:49 +01:00
Sebastian Huber
b5aceef5d9 bsps: Remove gicvx_interrupt_dispatch() 
Avoid one level of indirection.

Update #4202.
 2020-12-16 11:00:03 +01:00
Sebastian Huber
747fb65c6e bsps: Add GICv3 arm_gic_irq_processor_count() 
Update #4202.
 2020-12-16 11:00:03 +01:00
Kinsey Moore
9e7b5ebd7d tm27: Use generic cpu index accessor 
The arm_cp15 function for accessing the current CPU index is specific
to ARMv7 while this header is used for ARMv8 as well. Instead, use a
generic accessor that is part of the standard CPU API.
 2020-12-11 15:32:15 -06:00
Sebastian Huber
105e52032e bsps: Remove ARM GIC SGI target filter 
Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.

Update #4202.
 2020-12-10 09:42:50 +01:00
Sebastian Huber
b6925e10c8 bsps: Fix GICv3 arm_gic_trigger_sgi() 
Use the targets parameter to determine the targets of the SGI.  Change
targets parameter type to 32-bit to ease the parameter passing.  GICv3
supports up to 16 targets.

Update #4202.
 2020-12-10 09:42:49 +01:00
Kinsey Moore
a151ee167e bsps: Move ARM GICv2 driver to bsps/shared 
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
 2020-12-02 18:51:40 -06:00
Kinsey Moore
f8ad5bb2a4 bsps: Break out AArch32 GICv3 support 
This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
 2020-10-05 16:11:39 -05:00