Commit Graph

14077 Commits

Author SHA1 Message Date
Sebastian Huber
81af80e586 Rename *.s to *.S
Consistently use *.S for assembler files.

Close #2701.
2016-12-20 10:31:06 +01:00
Sebastian Huber
71f29c1206 bsp/atsam: Use standard XDMA throughout 2016-12-20 08:49:32 +01:00
Sebastian Huber
4aba8d7986 bsp/atsam: Use standard XDMA for QSPI support 2016-12-16 13:05:57 +01:00
Sebastian Huber
08f1d2f79b bsp/atsam: Add SC16IS752 support 2016-12-16 11:26:54 +01:00
Sebastian Huber
a5c56afa35 bsp/atsam: Move interrupt setup to PIO_Configure() 2016-12-16 09:04:58 +01:00
Sebastian Huber
a4936b59cb bsp/atsam: System initialization for PIO IRQs 2016-12-16 09:04:57 +01:00
Sebastian Huber
8eb5fbb64c bsp/atsamv: Move XDMAD instance out of SPI driver
Use system initialization for XDMAD.  Remove support for polling.
2016-12-16 09:04:57 +01:00
Sebastian Huber
d1c771cc8b bsp/atsam: Move XDMA IRQ handler to XDMA module
The XDMA is shared by all DMA capable modules.  Placing the XDMA
interrupt handler into the SPI module is wrong.
2016-12-15 11:05:09 +01:00
Sebastian Huber
cb592763d3 bsp/atsam: Use _Assert() instead of assert() 2016-12-15 11:05:08 +01:00
Sebastian Huber
fd12159a11 bsp/atsam: Use inline functions for XDMA access 2016-12-15 11:05:05 +01:00
Sebastian Huber
8dd83d39b4 bsp/atsam: Optimize SPI interrupt 2016-12-14 13:09:30 +01:00
Sebastian Huber
9686c6140f bsp/atsam: Simplify SPI transfer status 2016-12-14 13:09:30 +01:00
Sebastian Huber
de7c17192a bsp/atsam: Reduce context switches for SPI transf 2016-12-14 13:09:30 +01:00
Sebastian Huber
b52513b3a4 bsp/atsam: Optimize SPI DMA transfer setup 2016-12-14 13:09:29 +01:00
Sebastian Huber
f104bd342f bsp/atsam: Simplify SPI DMA transfer setup 2016-12-14 13:09:29 +01:00
Sebastian Huber
49b6931842 bsp/atsam: Simplify SPI DMA initialization 2016-12-14 13:09:29 +01:00
Sebastian Huber
d0452eb965 bsp/atsam: Simplify SPI interrupt handler 2016-12-14 13:09:29 +01:00
Sebastian Huber
c78928fcac bsp/atsam: Remove superfluous irq field 2016-12-14 13:09:29 +01:00
Sebastian Huber
9035630f00 bsp/atsam: Remove duplicate SPI register field 2016-12-14 13:09:28 +01:00
Sebastian Huber
62e1e0ff03 bsp/atsam: Simplify SPI initialization 2016-12-14 13:09:28 +01:00
Sebastian Huber
3afa95bae0 bsp/atsam: Hide details of SPI driver 2016-12-14 13:09:28 +01:00
Sebastian Huber
1505eca59c bsp/atsam: Align SPI API with PIO_Configure() 2016-12-14 13:09:28 +01:00
Sebastian Huber
5dd02e9569 bsp/atsam: Avoid to power on/off the SPI module 2016-12-14 13:09:27 +01:00
Sebastian Huber
f74e2959de bsp/atsam: Speed up SPI DMA transfer start 2016-12-14 13:09:27 +01:00
Sebastian Huber
0396f60e59 bsp/atsam: Optimize transfer setup checks 2016-12-14 13:09:27 +01:00
Sebastian Huber
3417070dc9 bsp/atsam: No timeout for SPI DMA transfers 2016-12-14 13:09:27 +01:00
Chris Johns
c6eead1353 libdl: Add C++ exception support to loaded modules.
This has been tested on SPARC, i386, PowerPC and ARM.

Closes #2767.
2016-12-14 09:07:16 +11:00
Sebastian Huber
6a9282d9bb Rename is_internal to always_set_to_false
Update #2825.
2016-12-12 08:03:14 +01:00
Sebastian Huber
b6606e8d99 score: Remove fatal is internal indicator
The fatal is internal indicator is redundant since the fatal source and
error code uniquely identify a fatal error.  Keep the fatal user
extension is internal parameter for backward compatibility and set it to
false always.

Update #2825.
2016-12-09 08:47:51 +01:00
Chris Johns
28fda6279b testsuite: Add test states to the testsuit configuration files.
Change the testsuite configuration files to hold state information about
a test. The states are:

 exclude        - Do not build the test
 expected-fail  - The test is expected to fail
 indeterminate  - The test may pass or may fail

A message is printed just after the test's BEGIN message to indicate
there is a special state for the test. No state message means the test
is expected to pass.

This support requires tests are correctly written to the use standard
support to begin and end a test.
2016-12-07 17:22:41 +11:00
Sebastian Huber
f65dcc712a score: Fix ARM and PowerPC context initialization
Update #2751.
2016-12-02 13:11:13 +01:00
Chris Johns
e629076003 libdebugger: Build for ARM's without a CP15. 2016-12-02 15:39:56 +11:00
Joel Sherrill
de7b174e38 Remove sparc/sis BSP.
closes #2810.
2016-11-29 09:29:03 -06:00
Chris Johns
8fd465e67e arm/zynq: Wait for the UART TX FIFO to empty on reset. 2016-11-29 08:50:40 +11:00
Sebastian Huber
6a1b9e4152 sparc: Optimize _ISR_Handler()
Use _Thread_Do_dispatch() instead of _Thread_Dispatch().  Restore the
PSR[EF] state of the interrupted context via new system call
syscall_irqdis_fp in case floating-point support is enabled.
2016-11-28 16:08:43 +01:00
Martin Erik Werner
9bf9068bb8 or1k: Avoid multiple iterations over cache
Previously, if the cache range operations were called with a range that
was larger than the cache size, this would lead to multiple iterations
over the cache, which is unnecessary.

Limit this so that if the range is larger than the cache size, the
operations will only iterate over the whole cache once.
2016-11-28 07:30:44 +01:00
Martin Erik Werner
a59dd5cc6f or1k: Remove secondary functions in cache manager
Move the code of the _CPU_OR1K_Cache_{enable,disable}_* functions into the
equivalent exported _CPU_cache_{enable,disable}_* functions instead, and
then delete them, in order to reduce the code indirection and aid
readability.

This does not touch the currently unused prefetch, writeback, and lock
functions.
2016-11-28 07:30:44 +01:00
Martin Erik Werner
3b4ddafe99 or1k: Avoid excessive ISR toggle in cache manager
Previously _ISR_Local_{disable,enable}() was executed twice for each
cache line operation, and since operations over the entire cache were
implemented by calling the single-line operations in a loop, this made
those operations rather costly.

Fix the double-toggle by calling _OR1K_mtspr() directly, and removing
the now-unused corresponding _CPU_OR1K_Cache_* functions.

Fix the entire-operations by moving the ISR toggle outside of the
loop, and by calling _OR1K_mtspr() directly instead of the single-line
operations.

Also implement range functions, since otherwise the cache manager falls
back on looping over the single-line operations.
2016-11-28 07:30:44 +01:00
Martin Erik Werner
4dcaa48e4a or1k: Indent & comment fix in cache.c
* Fix indentation of variable declarations.

* Change commented-out asm -> __asm__ to meet c99 standard if
  uncommented.
2016-11-28 07:30:44 +01:00
Martin Erik Werner
e639c026b9 or1k: Add functions for entire cache operations
Add functions for flushing and invalidating whole cache.

Since we don't have system calls that can operate on anything more than
a single cache line, these simply retrieves the cache size and iterates
over the full size, invalidating each line.

The current implementation assumes that there's only one level of cache.

These changes were contributed by Antmicro under contract by ÅAC
Microtec AB.

Close #2602
2016-11-28 07:30:44 +01:00
Sebastian Huber
562b0a014a bsps/arm: Add Cortex-M DWT CPU counter 2016-11-24 11:54:28 +01:00
Sebastian Huber
4b5ff47d15 score: Fix interrupt profiling
Callers of _Thread_Do_dispatch() must have a valid
Per_CPU_Control::Stats::thread_dispatch_disabled_instant.

Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt
stack to not exceed Per_CPU_Control::Interrupt_frame.

Update #2751.
2016-11-24 08:46:20 +01:00
Sebastian Huber
01ac1db824 powerpc: Fix interrupt profiling for e6500 2016-11-24 08:46:20 +01:00
Sebastian Huber
3142727602 bsp/lpc23xx_tli800: Disable tar01 test
Close #2824.
2016-11-23 07:47:00 +01:00
Sebastian Huber
f730c25b70 powerpc/mpc5xx: Rename CPU_Interrupt_frame
The MPC5XX support uses a legacy interrupt/exception infrastructure.

Close #2819.
2016-11-21 11:19:37 +01:00
Sebastian Huber
7ce60b378d powerpc: Use Per_CPU_Control::isr_dispatch_disable
Update #2751.
2016-11-18 07:30:35 +01:00
Sebastian Huber
c11ac2d59d sparc: Use Per_CPU_Control::isr_dispatch_disable
Update #2751.
2016-11-18 07:30:34 +01:00
Sebastian Huber
d5e073cde7 score: Allow interrupts during thread dispatch
Use a processor-specific interrupt frame during context switches in case
the executing thread is longer executes on the processor and the heir
thread is about to start execution.  During this period we must not use
a thread stack for interrupt processing.

Update #2809.
2016-11-18 07:30:34 +01:00
Sebastian Huber
2599c8e63e powerpc: Add up to date CPU_Interrupt_frame
Rename ppc_exc_min_frame to CPU_Interrupt_frame.  Move it and the
corresponding defines to <rtems/score/cpuimpl.h>.

Update #2809.
2016-11-18 07:30:33 +01:00
Sebastian Huber
bf4fdb1f1d powerpc: Move legacy CPU_Interrupt_frame
The only remaining user of CPU_Interrupt_frame on PowerPC is the mpc5xx
support.  Move it to here.

Update #2809.
2016-11-18 07:30:33 +01:00