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or1k: Indent & comment fix in cache.c

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* Fix indentation of variable declarations.

* Change commented-out asm -> __asm__ to meet c99 standard if
  uncommented.
This commit is contained in:
Martin Erik Werner
2016-11-25 19:21:41 +01:00
committed by Sebastian Huber
parent e639c026b9
commit 4dcaa48e4a
1 changed files with 25 additions and 14 deletions
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39
c/src/lib/libcpu/or1k/shared/cache/cache.c vendored
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@@ -23,9 +23,10 @@
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
@@ -35,7 +36,7 @@ static inline void _CPU_OR1K_Cache_enable_data(void)
static inline void _CPU_OR1K_Cache_disable_data(void)
{
uint32_t sr;
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
@@ -48,7 +49,7 @@ static inline void _CPU_OR1K_Cache_disable_data(void)
static inline void _CPU_OR1K_Cache_enable_instruction(void)
{
uint32_t sr;
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
@@ -84,7 +85,8 @@ static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
@@ -94,7 +96,8 @@ static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
@@ -104,7 +107,8 @@ static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
@@ -114,7 +118,8 @@ static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
@@ -125,7 +130,8 @@ static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
static inline void _CPU_OR1K_Cache_instruction_block_prefetch
(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
@@ -136,7 +142,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_prefetch
static inline void _CPU_OR1K_Cache_instruction_block_invalidate
(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
@@ -147,7 +154,8 @@ static inline void _CPU_OR1K_Cache_instruction_block_invalidate
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
@@ -159,19 +167,21 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
void _CPU_cache_flush_1_data_line(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_flush(d_addr);
//asm volatile("l.csync");
//__asm__ volatile("l.csync");
_ISR_Local_enable(level);
}
void _CPU_cache_invalidate_1_data_line(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_CPU_OR1K_Cache_data_block_invalidate(d_addr);
@@ -191,7 +201,8 @@ void _CPU_cache_unfreeze_data(void)
void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
{
ISR_Level level;
ISR_Level level;
_ISR_Local_disable (level);
_CPU_OR1K_Cache_instruction_block_invalidate(d_addr);