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Code Pull Requests Activity
32,670 Commits 7 Branches 54 Tags
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Commit Graph

65 Commits

Author SHA1 Message Date
Sebastian Huber
828276b081 bsps: Adjust shared Doxygen groups 
Update #3706.
 2019-03-08 07:42:54 +01:00
Sebastian Huber
c991eeeccc bsps: Adjust bsp.h Doxygen groups 
Update #3706.
 2019-03-08 07:42:54 +01:00
Sebastian Huber
212663bede bsps: Adjust architecture Doxygen groups 
- Use CamelCase as it is not used in our C code.  Enables simple search and
   replace.

 - Prefix with "RTEMS" to aid deployment and integration.  It aids
   searching and sorting.

Update #3706.
 2019-03-04 07:51:38 +01:00
Jiri Gaisler
568490a054 griscv: add additional cpu configurations 
* Also switch default config to imafd as the C extension
	  is not supported for code coverage
 2019-02-08 13:07:27 +01:00
Jiri Gaisler
d3d4e77c42 riscv: add griscv bsp 
Update #3678.
 2019-01-22 12:50:09 +01:00
Sebastian Huber
9aee88aa54 bsp/riscv: Clear boot command line 2019-01-08 14:44:08 +01:00
Sebastian Huber
ff081aee72 score: Rename interrupt stack symbols 
Rename

  * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin,
  * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and
  * _Configuration_Interrupt_stack_size in _ISR_Stack_size.

Move definitions to <rtems/score/isr.h>.  The new names are considerable
shorter and in the right namespace.

Update #3459.
 2018-11-08 08:09:20 +01:00
Hesham Almatary
9cda6f29a7 riscv: Allow platforms with no PLIC to proceed 
Spike simulator and QEMU's spike_v1.10 don't have a PLIC
 2018-09-17 14:22:17 +02:00
Sebastian Huber
141d502b52 bsp/riscv: Add missing BSP variant 
Update #3433.
 2018-08-02 15:33:00 +02:00
Sebastian Huber
4c740de6e2 bsp/riscv: Fix build with RTEMS_SMP undefined 
Update #3433.
 2018-08-02 14:13:25 +02:00
Sebastian Huber
3d11c1e2af bsp/riscv: Fix a synchronization issue for PLIC 
Update #3433.
 2018-08-02 09:28:23 +02:00
Sebastian Huber
dee2ebbaa6 bsp/riscv: Remove unused variable 
Update #3433.
 2018-08-01 11:15:55 +02:00
Sebastian Huber
56b0387d2f bsp/riscv: Add NS16750 support to console driver 
Update #3433.
 2018-08-01 11:15:14 +02:00
Sebastian Huber
529154bad2 bsp/riscv: Initialize FPU depending on ISA 
Initialize fcsr to zero for a defined rounding mode.

Update #3433.
 2018-08-01 10:08:59 +02:00
Sebastian Huber
48cbd63c84 bsp/riscv: Fix clock driver 
Do not assume that mtime is zero at boot time.

Update #3433.
 2018-08-01 10:07:18 +02:00
Sebastian Huber
44c2d393bd bsp/riscv: Fix inter-processor interrupts 
The previous version worked only on a patched Qemu.  Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
cfc95736ff riscv: Rework CPU counter support 
Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
581a0f8866 bsp/riscv: Use interrupt driven NS16550 driver 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
adede135e7 bsp/riscv: Add PLIC support 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
bd5603868a bsp/riscv: Add simple SMP support to clock driver 
This is a hack.  The clock interrupt should be handled by each hart.

Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6552ba8c37 bsp/riscv: Use CPU counter btimer 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
447fd894ae bsp/riscv: Add basic SMP startup 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6b9ef097c3 riscv: Add CLINT and PLIC support 
The CLINT and PLIC need some per-processor state.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
f5fd8eb9e3 bsps/riscv: Update linker-symbols.h 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
dda6e06edb bsp/riscv: Add reset via for SiFive Test Finisher 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
3a263a9b02 bsp/riscv: Add and use riscv_fdt_get_address() 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
7fe48551a2 bsp/riscv: Fix HTIF warnings 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
8db3f0e878 riscv: Rework exception handling 
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions.  Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
1a192398bf bsp/riscv: Add console support for NS16550 devices 
Update #3433.
 2018-07-06 14:27:39 +02:00
Sebastian Huber
31f90a2ff4 bsp/riscv: Simplify printk() support 
This is a prepartion to add NS16550 driver support to the console
driver.

Update #3433.
 2018-07-06 14:27:29 +02:00
Sebastian Huber
bca36d986b riscv: Add LADDR assembler define 
An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
dd32e2b2d0 riscv: Implement CPU counter 
Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
d3dff40e5e bsps: Update headers.am 2018-07-05 07:26:49 +02:00
Sebastian Huber
0fd8287b2b riscv: Add _CPU_Get_current_per_CPU_control() 
Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
3be4478f5a riscv: Avoid namespace pollution 
Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).

Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
ff7b10479b bsp/riscv: Remove bsp_interrupt_handler_default() 
It duplicated the default implementation.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
cdfed94f34 bsp/riscv: Rework clock driver 
Use device tree provided timebase frequency.  Do not write to read-only
mtime register.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
1232cd4690 bsp/riscv: Add device tree support for console 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
c558cc4b00 bsp/riscv: Fix vector table for lp64 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
5f5c450aa4 bsp/riscv: Add SMP startup synchronization 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
fe2cd01ba7 bsp/riscv: Add device tree support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
2086948a7b riscv: Add dummy SMP support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
9b2ef07f4b bsp/riscv: Load global pointer 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
b0ee7894d7 bsp/riscv: Use memset() to clear .bss 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
52f4fb65b3 riscv: Format assembler files 
Use tabs to match the GCC generated assembler output.

Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
fef0a414cf bsp/riscv: Do not clear integer registers at start 
There is no need to do this.

Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
380243627b bsp/riscv: Fix some warnings 
Update #3444.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
16d905f289 bsp/riscv: Add BSP options to define RAM region 
Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
f3da074a12 bsp/riscv: Add new BSP variants 
The latest RISC-V tool chain introduced new multilib variants. Add
corresponding BSP variants.

Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
6f5d88a469 bsp/riscv_generic: Rename to "riscv" 
Update #3433.
 2018-06-27 08:58:17 +02:00