In combination with the PPC_EXC_CONFIG_USE_FIXED_HANDLER option this
removes all dependencies on valid read-write data. The exception
handling must be statically configured and all components reside in
read-only sections.
In case a BSP enables this option, then fixed high level exception
handler will be used. For normal asynchronous exceptions this is
bsp_interrupt_dispatch() and for other exceptions this is the handler
from the read-only ppc_exc_handler_table. The global handler is
C_exception_handler(). This avoids some dependencies on valid
read-write data.
The Machine Check and Exception Syndrome Registers on Book-E and Book-E-like
processors contain useful information for decoding the cause of an exception.
NB: This patch depends on the PR 2048 patch sent earlier having been applied.
Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().
The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().
Add rtems_exception_frame and rtems_exception_frame_print().
Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.
Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().
Add test sptests/spfatal26.
Add ppc_exc_print_frame_and_context() which prints an exception frame
and the context via printk().
The global exception handler will call now rtems_fatal() with source
RTEMS_FATAL_SOURCE_POWERPC_EXCEPTION. The fatal code will contain the
pointer value to the exception frame.
PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the __eabi() function).
The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.
The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.
These modifications were required by hand after running the script.
In some cases, the file names did not match patterns. In others,
the format of the file did not match any common patterns.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
This commit covers at least PR2020, 2022, and 2023. This
patch adds all of the code for both BSPs, modifications
to libcpu/powerpc for the ppc440, and some updates to the
BSPs from follow up review and testing.
These BSPs should be good baselines for future development.
The configurations used by Ric are custom and have a non-standard
NIC. They also do not have a UART. Thus the current console
driver just prints to a RAM buffer.
The NIC and UART support are left for future work. When the UART
support is added, moving the existing "to RAM" console driver to
a shared location is likely desirable because boards with no debug
UART port are commonly deployed. This would let printk() go to RAM.
* new-exceptions/bspsupport/ppc_exc_async_normal.S: Bugfix for
MPC5674F. Use it for all to be safe.
* mpc55xx/include/emios.h: Fixed eMIOS module count.
* mpc55xx/include/irq.h: Fixed CAN vector numbers.
BSP_INTERRUPT_HANDLER_TABLE_SIZE is now a BSP option.
* mpc6xx/clock/c_clock.c, mpc6xx/mmu/mmuAsm.S,
new-exceptions/bspsupport/ppc_exc_global_handler.c,
shared/include/cpuIdent.c, shared/src/stack.c: Update due to API
changes.
* new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc_naked.S,
new-exceptions/bspsupport/ppc_exc_prologue.c: Branch targets are now
global for all minimal prologues. Generate branch instruction in
minimal prologues.
* shared/include/cpuIdent.c, shared/include/cpuIdent.h: Added support
for e500v2. Removed IVPR/IVOR/HWIVOR features since they are included
in Book E.
* new-exceptions/bspsupport/vectors.h,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_address.c,
new-exceptions/bspsupport/ppc_exc_categories.c,
new-exceptions/bspsupport/ppc_exc_initialize.c,
new-exceptions/bspsupport/ppc_exc_prologue.c: Added support for
e500v2. Added exception vector defines for Book E types. Removed
e200 exception vector defines. Added e500 exception vector defines.
Unified IVOR calculation for e200 and e500 (e200z1 has hard wired
IVOR values).
PR 1599/cpukit
* new-exceptions/bspsupport/ppc_exc_hdl.c: Rename
_Context_Switch_necessary to _Thread_Dispatch_necessary to more
properly reflect the intent.
PR 1573/cpukit
* mpc5xx/irq/irq.c, mpc5xx/irq/irq_asm.S,
new-exceptions/bspsupport/ppc_exc.S,
new-exceptions/bspsupport/ppc_exc_asm_macros.h,
new-exceptions/bspsupport/ppc_exc_hdl.c: Add a per cpu data structure
which contains the information required by RTEMS for each CPU core.
This encapsulates information such as thread executing, heir, idle
and dispatch needed.
* new-exceptions/bspsupport/ppc_exc_categories.c:
PSIM *must*not* hook SYS vector which is used e.g.,
for firmware I/O.
Added entries for AltiVec on PSIM.
