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2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

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* mpc6xx/clock/c_clock.c, mpc6xx/mmu/mmuAsm.S,
	new-exceptions/bspsupport/ppc_exc_global_handler.c,
	shared/include/cpuIdent.c, shared/src/stack.c: Update due to API
	changes.
This commit is contained in:
Sebastian Huber
2011-08-24 09:45:20 +00:00
parent cf3d1948b0
commit 1d367a49df
6 changed files with 19 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
c/src/lib/libcpu/powerpc/ChangeLog
View File

@@ -1,3 +1,10 @@
2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de>
* mpc6xx/clock/c_clock.c, mpc6xx/mmu/mmuAsm.S,
new-exceptions/bspsupport/ppc_exc_global_handler.c,
shared/include/cpuIdent.c, shared/src/stack.c: Update due to API
changes.
2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de>
PR 1799/bsps

1
c/src/lib/libcpu/powerpc/mpc6xx/clock/c_clock.c
View File

@@ -35,7 +35,6 @@
SPR_RW(BOOKE_TCR)
SPR_RW(BOOKE_TSR)
SPR_RW(BOOKE_DECAR)
SPR_RW(DEC)
extern int BSP_connect_clock_handler (void);

12
c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
View File

@@ -64,7 +64,7 @@ L1_caches_enables:
/*
* Enable caches and 604-specific features if necessary.
*/
mfspr r9,PVR
mfspr r9,PPC_PVR
rlwinm r9,r9,16,16,31
cmpi 0,r9,PPC_601
beq 4f /* not needed for 601 */
@@ -128,7 +128,7 @@ get_L1CR:
.type get_L2CR, @function
get_L2CR:
/* Make sure this is a > 750 chip */
mfspr r3,PVR
mfspr r3,PPC_PVR
rlwinm r3,r3,16,16,31
cmplwi r3,PPC_750 /* it's a 750 */
beq 1f
@@ -179,7 +179,7 @@ set_L2CR:
*/
/* Make sure this is a > 750 chip */
mfspr r0,PVR
mfspr r0,PPC_PVR
rlwinm r0,r0,16,16,31
cmplwi r0,PPC_750
beq thisIs750
@@ -349,7 +349,7 @@ enableCache:
.type get_L3CR, @function
get_L3CR:
/* Make sure this is a 7455 chip */
mfspr r3,PVR
mfspr r3,PPC_PVR
rlwinm r3,r3,16,16,31
cmplwi r3,PPC_7455 /* it's a 7455 */
beq 1f
@@ -379,7 +379,7 @@ set_L3CR:
*/
/* Make sure this is a 7455 chip */
mfspr r0,PVR
mfspr r0,PPC_PVR
rlwinm r0,r0,16,16,31
cmplwi r0,PPC_7455
beq thisIs7455
@@ -482,7 +482,7 @@ enableL3Cache:
.type CPU_clear_bats_early,@function
CPU_clear_bats_early:
li r3,0
mfspr r4,PVR
mfspr r4,PPC_PVR
rlwinm r4,r4,16,16,31 /* r4 = 1 for 601, 4 for 604 */
cmpwi r4, 1
sync

2
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_global_handler.c
View File

@@ -42,7 +42,7 @@ typedef struct LRFrameRec_ {
static uint32_t ppc_exc_get_DAR_dflt(void)
{
if (ppc_cpu_is_60x())
return PPC_SPECIAL_PURPOSE_REGISTER(DAR);
return PPC_SPECIAL_PURPOSE_REGISTER(PPC_DAR);
else
switch (ppc_cpu_is_bookE()) {
default:

6
c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
View File

@@ -21,7 +21,7 @@
/*
* Generate inline code to read Processor Version Register
*/
SPR_RO(PVR)
SPR_RO(PPC_PVR)
ppc_cpu_id_t current_ppc_cpu = PPC_UNKNOWN;
ppc_cpu_revision_t current_ppc_revision = 0xff;
@@ -79,7 +79,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
if ( PPC_UNKNOWN != current_ppc_cpu )
return current_ppc_cpu;
pvr = (_read_PVR() >> 16);
pvr = (_read_PPC_PVR() >> 16);
/*
* apply tweaks to ignore version
*/
@@ -210,7 +210,7 @@ ppc_cpu_id_t get_ppc_cpu_type(void)
ppc_cpu_revision_t get_ppc_cpu_revision(void)
{
ppc_cpu_revision_t rev = (ppc_cpu_revision_t) (_read_PVR() & 0xffff);
ppc_cpu_revision_t rev = (ppc_cpu_revision_t) (_read_PPC_PVR() & 0xffff);
current_ppc_revision = rev;
return rev;
}

4
c/src/lib/libcpu/powerpc/shared/src/stack.c
View File

@@ -2,7 +2,7 @@
#include <rtems/bspIo.h>
#include <libcpu/spr.h>
SPR_RO(LR)
SPR_RO(PPC_LR)
typedef struct FrameRec_ {
struct FrameRec_ *up;
@@ -17,7 +17,7 @@ register Frame p = (Frame)lr;
register int i=0;
if (pc) stack[i++]=pc;
if (!p)
p = (Frame)_read_LR();
p = (Frame)_read_PPC_LR();
stack[i++]=p;
p = r1;
if (!p) /* no macro for reading user regs */