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31,775 Commits 7 Branches 54 Tags
31f90a2ff4cb40b830c2cbcc184315e424fc8e12
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Author SHA1 Message Date
Sebastian Huber
31f90a2ff4 bsp/riscv: Simplify printk() support 
This is a prepartion to add NS16550 driver support to the console
driver.

Update #3433.
 2018-07-06 14:27:29 +02:00
Sebastian Huber
bca36d986b riscv: Add LADDR assembler define 
An address must be loaded to a register according to the code model.
Add LADDR define for use in assembler code.

Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
dd32e2b2d0 riscv: Implement CPU counter 
Update #3433.
 2018-07-06 13:46:46 +02:00
Sebastian Huber
6418c91d5a Update config.guess and config.sub 
Update via:

wget -O config.guess 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.guess;hb=HEAD'
wget -O config.sub 'https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=HEAD'

Update #3433.
 2018-07-06 10:06:02 +02:00
Sebastian Huber
fc5cc9af10 bsps/arm: Include missing header file 2018-07-05 08:54:57 +02:00
Sebastian Huber
d3dff40e5e bsps: Update headers.am 2018-07-05 07:26:49 +02:00
Sebastian Huber
e755782bde riscv: Clear reservations 
See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store-Conditional Instructions".

Update #3433.
 2018-07-05 07:12:24 +02:00
Sebastian Huber
77fbbd620f posix: Check for new <pthread.h> prototypes 
Update #3342.
Update #3343.
 2018-07-05 07:10:04 +02:00
Sebastian Huber
e07b51a710 riscv: Fix fcsr initialization 
Update #3433.
 2018-07-02 15:21:36 +02:00
Sebastian Huber
b36bf5bda8 score: Increase PER_CPU_CONTROL_SIZE_APPROX 
Increase the PER_CPU_CONTROL_SIZE_APPROX on 64-bit targets.

Update #3433.
 2018-06-29 12:55:28 +02:00
Sebastian Huber
79d69aef54 riscv: Fix SMP context switch support 
Update #3433.
 2018-06-29 12:08:16 +02:00
Sebastian Huber
109bc1c74b riscv: Add SMP context switch support 
Update #3433.
 2018-06-29 10:04:38 +02:00
Sebastian Huber
52352387cc riscv: Add floating-point support 
Update #3433.
 2018-06-29 10:04:38 +02:00
Sebastian Huber
995e91e847 riscv: Fix global construction 
Update #3433.
 2018-06-29 10:04:38 +02:00
Sebastian Huber
694e79a0b7 riscv: Add TLS support 
Update #3433.
 2018-06-29 10:04:38 +02:00
Sebastian Huber
afb60eb183 riscv: Remove dead code 
Update #3433.
 2018-06-29 10:04:38 +02:00
Sebastian Huber
e43994dfbb riscv: Optimize context switch and interrupts 
Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
a8188730bf riscv: Fix _CPU_Context_Initialize() prototype 
Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
dffc08c0e9 riscv: Fix interrupt save/restore 
Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
40f81ce634 riscv: Implement _CPU_Context_validate() 
Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
71af1a4bb2 riscv: Make some CPU port defines visible to asm 
Move SREG and LREG assembler defines to <rtems/score/asm.h>.

Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
8f035cb85a riscv: Implement _CPU_Context_volatile_clobber() 
Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
b706b4a3c0 riscv: Remove mstatus from thread context 
The mstatus register contains no thread-specific state which must be
saved/restored during a context switch.  Machine interrupts (MIE) must
be enabled during a context switch.

Create separate CPU_Interrupt_frame structure.

Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
2987c4f27a riscv: Remove x8 initialization 
The RISC-V psABI

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

does not mention that this is a frame pointer.

Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
04698ebd49 riscv: Properly align the thread stack 
Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
a49a3c8eed riscv: Do not clear thread context 
Do not clear the complete thread context.  Initialize only the necessary
members.  The Context_Control::is_executing member must be preserved
across _CPU_Context_Initialize() calls.

Update #3433.
 2018-06-29 10:04:37 +02:00
Sebastian Huber
9510742e7f riscv: Fix CPU_STACK_ALIGNMENT 
According to the RISC-V psABI

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

the stack alignment is 128 bits (16 bytes).

Update #3433.
 2018-06-29 10:04:36 +02:00
Sebastian Huber
98f051efed riscv: Remove RISCV_GCC_RED_ZONE_SIZE 
The current ABI says that there is no stack red zone:

https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

"Procedures must not rely upon the persistence of stack-allocated data
whose addresses lie below the stack pointer."

Update #3433.
 2018-06-29 10:04:36 +02:00
Sebastian Huber
9704d86f86 riscv: Enable interrupts during dispatch after ISR 
The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.
 2018-06-29 10:04:32 +02:00
Sebastian Huber
0fd8287b2b riscv: Add _CPU_Get_current_per_CPU_control() 
Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
3be4478f5a riscv: Avoid namespace pollution 
Remove <rtems/score/riscv-utility.h> include from <rtems/score/cpu.h>
(which is visible via <rtems.h> for example).

Update #3433.
 2018-06-28 15:03:23 +02:00
Sebastian Huber
bc3bdf2438 riscv: Optimize and fix interrupt disable/enable 
Use the atomic read and clear operation to disable interrupts.

Do not write the complete mstatus.  Instead, set only the MIE bit
depending on the level parameter.

Update #3433.
 2018-06-28 15:03:20 +02:00
Sebastian Huber
ff7b10479b bsp/riscv: Remove bsp_interrupt_handler_default() 
It duplicated the default implementation.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
cdfed94f34 bsp/riscv: Rework clock driver 
Use device tree provided timebase frequency.  Do not write to read-only
mtime register.

Update #3433.
 2018-06-28 15:03:19 +02:00
Sebastian Huber
1232cd4690 bsp/riscv: Add device tree support for console 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
c558cc4b00 bsp/riscv: Fix vector table for lp64 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
5f5c450aa4 bsp/riscv: Add SMP startup synchronization 
Update #3433.
 2018-06-28 15:02:13 +02:00
Sebastian Huber
fe2cd01ba7 bsp/riscv: Add device tree support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
2086948a7b riscv: Add dummy SMP support 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
853c5ef890 build: Enable RISC-V SMP build 
Update #3433.
 2018-06-28 15:02:12 +02:00
Sebastian Huber
7c3b0df107 riscv: Implement ISR set/get level 
Fix prototypes.

Update #3433.
 2018-06-28 15:02:08 +02:00
Sebastian Huber
9b2ef07f4b bsp/riscv: Load global pointer 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
b0ee7894d7 bsp/riscv: Use memset() to clear .bss 
Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
52f4fb65b3 riscv: Format assembler files 
Use tabs to match the GCC generated assembler output.

Update #3433.
 2018-06-27 08:58:18 +02:00
Sebastian Huber
fef0a414cf bsp/riscv: Do not clear integer registers at start 
There is no need to do this.

Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
380243627b bsp/riscv: Fix some warnings 
Update #3444.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
16d905f289 bsp/riscv: Add BSP options to define RAM region 
Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
37a1fc20e0 bsp/riscv: Remove unused BSP options 
Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
f3da074a12 bsp/riscv: Add new BSP variants 
The latest RISC-V tool chain introduced new multilib variants. Add
corresponding BSP variants.

Update #3433.
 2018-06-27 08:58:17 +02:00
Sebastian Huber
6f5d88a469 bsp/riscv_generic: Rename to "riscv" 
Update #3433.
 2018-06-27 08:58:17 +02:00