riscv: Fix SMP context switch support

Update #3433.
2018-06-29 12:08:01 +02:00
parent 109bc1c74b
commit 79d69aef54
1 changed files with 2 additions and 2 deletions
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -153,8 +153,8 @@ SYM(_CPU_Context_restore):
 	/* We may have a new heir */

 	/* Read the executing and heir */
-	lw	a4, PER_CPU_OFFSET_EXECUTING(a2)
-	lw	a5, PER_CPU_OFFSET_HEIR(a2)
+	LREG	a4, PER_CPU_OFFSET_EXECUTING(a2)
+	LREG	a5, PER_CPU_OFFSET_HEIR(a2)

 	/*
 	 * Update the executing only if necessary to avoid cache line