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Code Pull Requests Activity
33,995 Commits 7 Branches 54 Tags
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Commit Graph

95 Commits

Author SHA1 Message Date
Sebastian Huber
9eb9813dc1 bsps: Add missing DWARF 5 sections 
Sort alphabetically.
 2021-01-26 15:29:36 +01:00
Sebastian Huber
33c12d5f92 bsps: Support DWARF 5 sections 
GCC 11 uses DWARF 5 by default.
 2021-01-25 12:56:00 +01:00
Sebastian Huber
9f3a08ef2d bsps: Use header file for GIC architecture support 
This avoids a function call overhead in the interrupt dispatching.

Update #4202.
 2020-12-23 09:24:49 +01:00
Sebastian Huber
23d9223ad3 bsps/arm: Invalidate TLB in start.S 
Update #4202.
 2020-12-23 09:24:47 +01:00
Sebastian Huber
e164df5e33 bsps/arm: Clear SCTLR[M, I, A, C] in start.S 
Initialize the data and unified cache levels.  Invalidate the
instruction cache levels.

Update #4202.
 2020-12-23 09:19:28 +01:00
Sebastian Huber
b32fd22732 bsps/arm: Add arm-data-cache-loop-set-way.h 
This makes it possible to reuse this loop.

Update #4202.
 2020-12-23 09:19:28 +01:00
Sebastian Huber
46a3c0446f bsps/arm: Remove optional start hook arguments 
The start hook arguments are not used by a BSP.  Removing them avoids
the need for a stack during the very early system initialization.

Update #4202.
 2020-12-23 09:19:28 +01:00
Sebastian Huber
76a1a53780 bsps/arm: Invalidate branch predictors earlier 
Make sure the branch predictors are invalidated before the first branch
is executed.

Update #4202.
 2020-12-23 09:19:28 +01:00
Sebastian Huber
272534eb72 bsps/arm: Set VBAR in start.S 
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.

Set the VBAR to the normal vector table in start.S for the main
processor.  Secondary processors set it in bsp_start_hook_0().

Update #4202.
 2020-12-23 09:19:17 +01:00
Sebastian Huber
b5aceef5d9 bsps: Remove gicvx_interrupt_dispatch() 
Avoid one level of indirection.

Update #4202.
 2020-12-16 11:00:03 +01:00
Christian Mauderer
9b3def237a bsps/arm/imx*: Fix location of shared headers 
When moving the headers from the imx BSP to the shared area, the wrong
directory has been selected. This patch fixes that problem.

Update #4180
 2020-12-14 11:29:36 +01:00
Sebastian Huber
105e52032e bsps: Remove ARM GIC SGI target filter 
Remove the target filter for software-generated interrupts since this
feature is not supported by the affinity routing in GICv3.

Update #4202.
 2020-12-10 09:42:50 +01:00
Sebastian Huber
b6925e10c8 bsps: Fix GICv3 arm_gic_trigger_sgi() 
Use the targets parameter to determine the targets of the SGI.  Change
targets parameter type to 32-bit to ease the parameter passing.  GICv3
supports up to 16 targets.

Update #4202.
 2020-12-10 09:42:49 +01:00
Sebastian Huber
e68827e1d9 arm/cache-cp15: Support Armv8 
Update #4202.
 2020-12-10 07:58:03 +01:00
Kinsey Moore
a151ee167e bsps: Move ARM GICv2 driver to bsps/shared 
This moves the ARM GICv2 driver to bsps/shared to be usable by AArch64
code.
 2020-12-02 18:51:40 -06:00
Kinsey Moore
f0859573f9 bsps: Move zynq-uart to bsps/shared 
This moves the zynq-uart driver from bsps/arm/shared to bsps/shared to
accomodate use by AArch64 BSPs.
 2020-12-02 18:51:40 -06:00
Christian Mauderer
7141afbb0e bsp/imxrt: Add new BSP 
Update #4180
 2020-11-20 08:53:19 +01:00
Christian Mauderer
6cece58544 bsps/imx: Move imx-gpio to arm/shared 
Update #4180
 2020-11-20 08:53:18 +01:00
Christian Mauderer
e00f443428 imx: Move imx_iomux to arm/shared 
Update #4180
 2020-11-20 08:53:18 +01:00
Sebastian Huber
273613f1a8 bsps/arm: Sort fast text/data sections 2020-10-21 07:58:38 +02:00
Sebastian Huber
3fccdc956c bsps/arm: Add support for MPU region alignment 
Update #3910.
 2020-10-21 07:58:34 +02:00
Kinsey Moore
f8ad5bb2a4 bsps: Break out AArch32 GICv3 support 
This breaks out AArch32-specific code so that the shared GICv3 code can
be reused by other architectures.
 2020-10-05 16:11:39 -05:00
Kinsey Moore
1480c3f5e8 bsps: Break out AArch32 portions of GPT driver 
This breaks AArch32-specific portions of the ARM GPT driver into their
own file so that the generic code can be moved for reuse by other
architectures.
 2020-10-05 16:11:39 -05:00
Kinsey Moore
1c03649312 Move ARM PL011 UART driver 
This UART driver is now needed for BSPs other than ARM.
 2020-10-05 16:11:39 -05:00
Sebastian Huber
20d82377a6 arm: Fix arm_cp15_set_translation_table_entries() 
In a multi-processor system we must broadcast the TLB maintenance operation to
the Inner Shareable domain to ensure that the other processors update their TLB
caches accordingly.

Close #4068.
 2020-09-17 08:20:35 +02:00
Jan Sommer
b87efa7599 bsp/xilinx-zynq: Flush TX-Buffer before initializing uart 
Closes #4055
Closes #4056
 2020-08-22 17:29:25 +10:00
Sebastian Huber
95d37b6307 bsps/arm: Use _Assert() 2020-08-20 14:54:18 +02:00
Christian Mauderer
222d687969 bsps/arm: Fix uninitialized value in generic timer 
_CPU_Counter_frequency() can be called by the rtems_counter
initialization before arm_gt_clock_initialize() initializes the value
used in _CPU_Counter_frequency().

Closes #3961.
 2020-04-20 09:07:35 +02:00
Sebastian Huber
51307919b4 arm: ARMv7-M statically initialized vector table 
Statically initialize the ARMv7-M vector table to allow a placement in
ROM with read-only MPU settings.

Change licence to BSD-2-Clause in some files.
 2020-04-03 09:12:44 +02:00
Sebastian Huber
e58ecb8433 bsps/arm: Initialize priorities of PPIs 
At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs).  We have to initialize the
priority of the PPIs on secondary processors.
 2020-02-24 09:21:47 +01:00
Sebastian Huber
32991495b4 score: Statically allocate idle/MPCI stacks 
Place idle and MPCI stacks into extra linker sections.  This can be
optionally used by applications to control the placement of the stacks.

Update #3835.
 2020-02-12 09:08:36 +01:00
Sebastian Huber
b900f507cb arm/xilinx-zynq: Split console driver files 
This avoids to pull in via printk() the Termios support which pulls in
the file system support.  This fixes a spconfig02 test failure.
 2020-02-12 09:08:35 +01:00
Sebastian Huber
ffa1153170 bsps: Add RamEnd to linker command files 
Update #3838.
 2020-02-04 05:52:28 +01:00
Kinsey Moore
ebf0f8f13f bsps/arm/shared: Add GICv3 implementation 
This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
 2020-01-17 16:17:42 -06:00
Sebastian Huber
2497da06de bsps/arm: Export bsp_start_hook_0_done 
Close #3789.
 2019-12-19 10:59:20 +01:00
Jeff Kubascik
b51a1d07d0 bsps/arm: Unmask generic timer in interrupt handler 
Xen will mask the virtual timer before injecting the interrupt to the
guest.
 2019-12-05 07:25:52 +01:00
Jeff Kubascik
001cd9bd5c bsps/arm: Add zImage boot header 
Xen currently only supports the zImage loader for 32 bit guests on ARM
targets.
 2019-12-05 07:25:52 +01:00
Sebastian Huber
f9648baf65 bsps/arm: Add support for small pages MMU 
The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.

Enable it by default on the realview_pbx_a9_qemu BSP.
 2019-10-31 09:48:05 +01:00
Chris Johns
15b6f44deb arm/tlb: Fix the MP affinity check to invalidate ASIDs. 
- The TI's CortexA7 MP MPIDR register returns 0

Updates #3760
 2019-08-12 13:58:31 +10:00
Chris Johns
98d6792376 arm: Select the TLB invalidate based on the core's Id variant. 
Closes #3760
 2019-07-31 08:33:05 +10:00
Sebastian Huber
1e6380baf2 bsps/arm: Move HYP to SVC change to start.S 
This fixes the corruption of r3 by the call to
bsp_start_arm_drop_hyp_mode().

Moving the code makes it easier to review changes in start.S.

Close #3773.
 2019-07-26 08:12:20 +02:00
Sebastian Huber
0ee2125a92 bsps/arm: Move register init to start.S 
This makes it easier to review changes in start.S.

Update #3773.
 2019-07-26 08:00:48 +02:00
Sebastian Huber
0f5c1d5344 bsps/arm: Remove register init for ARMv7-M 
There are no known ARMv7-M chips with a dual lockstep mode.

Update #3773.
 2019-07-26 08:00:39 +02:00
Chris Johns
c43071f523 arm: Return the current handler from arm_cp15_set_exception_handler 
Closes #3762
 2019-06-28 09:01:27 +10:00
Sebastian Huber
7fdf48aaf2 score: Add _SMP_Othercast_action() 2019-05-20 08:49:39 +02:00
Sebastian Huber
658700449d score: Add _SMP_Broadcast_action() 2019-05-20 08:49:39 +02:00
Sebastian Huber
ad40d05eba score: Remove _SMP_Before_multitasking_action() 
Use _SMP_Multicast_action() instead.
 2019-04-12 09:44:48 +02:00
Jeff Kubascik
b0044305a6 bsp/zynq-uart: Move Zynq UART driver to shared directory 
This driver will be shared with the xilinx-zynqmp BSP.

Update #3682.
 2019-04-11 07:29:06 +02:00
Sebastian Huber
3fe215502a Remove superfluous <rtems/system.h> includes 2019-03-14 13:13:27 +01:00
Sebastian Huber
15359bb6cb bsps/arm: Adjust CMSIS Doxygen groups 
Update #3706.
 2019-03-08 07:42:54 +01:00