mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2025-11-16 04:24:45 +00:00
Compare commits
1 Commits
711257c0c3
...
3.5.16
| Author | SHA1 | Date | |
|---|---|---|---|
|
8cffa05ff7 |
6
.gitignore
vendored
6
.gitignore
vendored
@@ -1,6 +0,0 @@
|
||||
/build
|
||||
doc
|
||||
/*.ini
|
||||
.lock*
|
||||
*.pyc
|
||||
.waf*
|
||||
@@ -1,4 +0,0 @@
|
||||
include:
|
||||
- project: 'administration/integration'
|
||||
file:
|
||||
- 'ci/config/rtems.yml'
|
||||
@@ -1,288 +0,0 @@
|
||||
["defaults"]
|
||||
exclude = ["format", "spell"]
|
||||
|
||||
[[ignore."cpukit/dev"]]
|
||||
files = ["cpukit/dev/iovprintf.c"]
|
||||
|
||||
[[ignore."cpukit/include"]]
|
||||
files = [
|
||||
"cpukit/include/arpa/ftp.h",
|
||||
"cpukit/include/crypt.h",
|
||||
"cpukit/include/dlfcn.h",
|
||||
"cpukit/include/fdt.h",
|
||||
"cpukit/include/libfdt_env.h",
|
||||
"cpukit/include/libfdt.h",
|
||||
"cpukit/include/link_elf.h",
|
||||
"cpukit/include/link.h",
|
||||
"cpukit/include/md4.h",
|
||||
"cpukit/include/md5.h",
|
||||
"cpukit/include/rtems/jffs2.h",
|
||||
"cpukit/include/rtems/mouse_parser.h",
|
||||
"cpukit/include/sha224.h",
|
||||
"cpukit/include/sha256.h",
|
||||
"cpukit/include/sha384.h",
|
||||
"cpukit/include/sha512.h",
|
||||
"cpukit/include/sha512t.h",
|
||||
"cpukit/include/sys/_ffcounter.h",
|
||||
"cpukit/include/sys/cdefs_elf.h",
|
||||
"cpukit/include/sys/endian.h",
|
||||
"cpukit/include/sys/event.h",
|
||||
"cpukit/include/sys/exec_elf.h",
|
||||
"cpukit/include/sys/priority.h",
|
||||
"cpukit/include/sys/statvfs.h",
|
||||
"cpukit/include/sys/timeffc.h",
|
||||
"cpukit/include/sys/timepps.h",
|
||||
"cpukit/include/sys/timetc.h",
|
||||
"cpukit/include/sys/timex.h",
|
||||
"cpukit/include/sys/utsname.h",
|
||||
"cpukit/include/uuid/uuid.h",
|
||||
"cpukit/include/xz.h",
|
||||
"cpukit/include/zconf.h",
|
||||
"cpukit/include/zlib.h"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/include/machine"]]
|
||||
files = ["cpukit/include/machine/*.h"]
|
||||
|
||||
[[ignore."cpukit/jffs2"]]
|
||||
files = [
|
||||
"cpukit/libfs/src/jffs2/include/linux/jffs2.h",
|
||||
"cpukit/libfs/src/jffs2/src/acl.h",
|
||||
"cpukit/libfs/src/jffs2/src/build.c",
|
||||
"cpukit/libfs/src/jffs2/src/compat-crc32.c",
|
||||
"cpukit/libfs/src/jffs2/src/compr_rtime.c",
|
||||
"cpukit/libfs/src/jffs2/src/compr_zlib.c",
|
||||
"cpukit/libfs/src/jffs2/src/compr_rubin.c",
|
||||
"cpukit/libfs/src/jffs2/src/compr.c",
|
||||
"cpukit/libfs/src/jffs2/src/compr.h",
|
||||
"cpukit/libfs/src/jffs2/src/debug.c",
|
||||
"cpukit/libfs/src/jffs2/src/debug.h",
|
||||
"cpukit/libfs/src/jffs2/src/dir-rtems.c",
|
||||
"cpukit/libfs/src/jffs2/src/erase.c",
|
||||
"cpukit/libfs/src/jffs2/src/flashio.c",
|
||||
"cpukit/libfs/src/jffs2/src/fs-rtems.c",
|
||||
"cpukit/libfs/src/jffs2/src/gc.c",
|
||||
"cpukit/libfs/src/jffs2/src/jffs2_fs_i.h",
|
||||
"cpukit/libfs/src/jffs2/src/jffs2_fs_sb.h",
|
||||
"cpukit/libfs/src/jffs2/src/malloc-rtems.c",
|
||||
"cpukit/libfs/src/jffs2/src/nodelist.c",
|
||||
"cpukit/libfs/src/jffs2/src/nodelist.h",
|
||||
"cpukit/libfs/src/jffs2/src/nodemgmt.c",
|
||||
"cpukit/libfs/src/jffs2/src/read.c",
|
||||
"cpukit/libfs/src/jffs2/src/readinode.c",
|
||||
"cpukit/libfs/src/jffs2/src/scan.c",
|
||||
"cpukit/libfs/src/jffs2/src/summary.h",
|
||||
"cpukit/libfs/src/jffs2/src/wbuf.c",
|
||||
"cpukit/libfs/src/jffs2/src/write.c",
|
||||
"cpukit/libfs/src/jffs2/src/xattr.h"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/libcrypt"]]
|
||||
files = ["cpukit/libcrypt/*.c"]
|
||||
|
||||
[[ignore."cpukit/libcsupport"]]
|
||||
files = [
|
||||
"cpukit/libcsupport/src/cfmakeraw.c",
|
||||
"cpukit/libcsupport/src/cfmakesane.c",
|
||||
"cpukit/libcsupport/src/realpath.c"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/libmd"]]
|
||||
files = ["cpukit/libmd/*.c"]
|
||||
|
||||
[[ignore."cpukit/libdl"]]
|
||||
files = [
|
||||
"cpukit/libdl/fastlz.c",
|
||||
"cpukit/libdl/fastlz.h"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/dtc"]]
|
||||
files = [
|
||||
"cpukit/dtc/libfdt/*.c",
|
||||
"cpukit/dtc/libfdt/*.h",
|
||||
"cpukit/dtc/README.license",
|
||||
"cpukit/dtc/VERSION"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/mouse"]]
|
||||
files = ["cpukit/libmisc/mouse/mouse_parser.c"]
|
||||
|
||||
[[ignore."cpukit/score/cpu"]]
|
||||
files = [
|
||||
"cpukit/score/cpu/i386/include/machine/elf_machdep.h",
|
||||
"cpukit/score/cpu/m68k/include/machine/elf_machdep.h",
|
||||
"cpukit/score/cpu/mips/include/machine/elf_machdep.h",
|
||||
"cpukit/score/cpu/nios2/include/machine/elf_machdep.h",
|
||||
"cpukit/score/cpu/sparc/include/machine/elf_machdep.h",
|
||||
"cpukit/score/cpu/x86_64/include/machine/elf_machdep.h"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/score/kern"]]
|
||||
files = [
|
||||
"cpukit/score/src/kern_ntptime.c",
|
||||
"cpukit/score/src/kern_tc.c"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/shell"]]
|
||||
files = [
|
||||
"cpukit/libmisc/shell/cat_file.c",
|
||||
"cpukit/libmisc/shell/cmds.c",
|
||||
"cpukit/libmisc/shell/cmp-ls.c",
|
||||
"cpukit/libmisc/shell/dd-args.c",
|
||||
"cpukit/libmisc/shell/dd-conv_tab.c",
|
||||
"cpukit/libmisc/shell/dd-conv.c",
|
||||
"cpukit/libmisc/shell/dd-misc.c",
|
||||
"cpukit/libmisc/shell/dd-position.c",
|
||||
"cpukit/libmisc/shell/dd.h",
|
||||
"cpukit/libmisc/shell/err.c",
|
||||
"cpukit/libmisc/shell/err.h",
|
||||
"cpukit/libmisc/shell/errx.c",
|
||||
"cpukit/libmisc/shell/extern-cp.h",
|
||||
"cpukit/libmisc/shell/extern-dd.h",
|
||||
"cpukit/libmisc/shell/extern-ls.h",
|
||||
"cpukit/libmisc/shell/fdisk.c",
|
||||
"cpukit/libmisc/shell/filemode.c",
|
||||
"cpukit/libmisc/shell/fts.c",
|
||||
"cpukit/libmisc/shell/fts.h",
|
||||
"cpukit/libmisc/shell/hexdump-conv.c",
|
||||
"cpukit/libmisc/shell/hexdump-display.c",
|
||||
"cpukit/libmisc/shell/hexdump-odsyntax.c",
|
||||
"cpukit/libmisc/shell/hexdump-parse.c",
|
||||
"cpukit/libmisc/shell/hexdump.h",
|
||||
"cpukit/libmisc/shell/hexsyntax.c",
|
||||
"cpukit/libmisc/shell/login_check.c",
|
||||
"cpukit/libmisc/shell/login_prompt.c",
|
||||
"cpukit/libmisc/shell/main_alias.c",
|
||||
"cpukit/libmisc/shell/main_blkstats.c",
|
||||
"cpukit/libmisc/shell/main_blksync.c",
|
||||
"cpukit/libmisc/shell/main_cat.c",
|
||||
"cpukit/libmisc/shell/main_cd.c",
|
||||
"cpukit/libmisc/shell/main_chdir.c",
|
||||
"cpukit/libmisc/shell/main_chmod.c",
|
||||
"cpukit/libmisc/shell/main_chroot.c",
|
||||
"cpukit/libmisc/shell/main_cmdchmod.c",
|
||||
"cpukit/libmisc/shell/main_cmdchown.c",
|
||||
"cpukit/libmisc/shell/main_cmdls.c",
|
||||
"cpukit/libmisc/shell/main_cp.c",
|
||||
"cpukit/libmisc/shell/main_cpuinfo.c",
|
||||
"cpukit/libmisc/shell/main_cpuuse.c",
|
||||
"cpukit/libmisc/shell/main_date.c",
|
||||
"cpukit/libmisc/shell/main_dd.c",
|
||||
"cpukit/libmisc/shell/main_debugrfs.c",
|
||||
"cpukit/libmisc/shell/main_df.c",
|
||||
"cpukit/libmisc/shell/main_dir.c",
|
||||
"cpukit/libmisc/shell/main_echo.c",
|
||||
"cpukit/libmisc/shell/main_edit.c",
|
||||
"cpukit/libmisc/shell/main_exit.c",
|
||||
"cpukit/libmisc/shell/main_flashdev.c",
|
||||
"cpukit/libmisc/shell/main_getenv.c",
|
||||
"cpukit/libmisc/shell/main_halt.c",
|
||||
"cpukit/libmisc/shell/main_help.c",
|
||||
"cpukit/libmisc/shell/main_hexdump.c",
|
||||
"cpukit/libmisc/shell/main_i2cdetect.c",
|
||||
"cpukit/libmisc/shell/main_i2cget.c",
|
||||
"cpukit/libmisc/shell/main_i2cset.c",
|
||||
"cpukit/libmisc/shell/main_id.c",
|
||||
"cpukit/libmisc/shell/main_ln.c",
|
||||
"cpukit/libmisc/shell/main_logoff.c",
|
||||
"cpukit/libmisc/shell/main_ls.c",
|
||||
"cpukit/libmisc/shell/main_lsof.c",
|
||||
"cpukit/libmisc/shell/main_mallocinfo.c",
|
||||
"cpukit/libmisc/shell/main_md5.c",
|
||||
"cpukit/libmisc/shell/main_mdump.c",
|
||||
"cpukit/libmisc/shell/main_medit.c",
|
||||
"cpukit/libmisc/shell/main_mfill.c",
|
||||
"cpukit/libmisc/shell/main_mkdir.c",
|
||||
"cpukit/libmisc/shell/main_mknod.c",
|
||||
"cpukit/libmisc/shell/main_mkrfs.c",
|
||||
"cpukit/libmisc/shell/main_mmove.c",
|
||||
"cpukit/libmisc/shell/main_mount.c",
|
||||
"cpukit/libmisc/shell/main_msdosfmt.c",
|
||||
"cpukit/libmisc/shell/main_mv.c",
|
||||
"cpukit/libmisc/shell/main_perioduse.c",
|
||||
"cpukit/libmisc/shell/main_profreport.c",
|
||||
"cpukit/libmisc/shell/main_pwd.c",
|
||||
"cpukit/libmisc/shell/main_rm.c",
|
||||
"cpukit/libmisc/shell/main_rmdir.c",
|
||||
"cpukit/libmisc/shell/main_rtc.c",
|
||||
"cpukit/libmisc/shell/main_rtems.c",
|
||||
"cpukit/libmisc/shell/main_rtrace.c",
|
||||
"cpukit/libmisc/shell/main_setenv.c",
|
||||
"cpukit/libmisc/shell/main_sleep.c",
|
||||
"cpukit/libmisc/shell/main_spi.c",
|
||||
"cpukit/libmisc/shell/main_stackuse.c",
|
||||
"cpukit/libmisc/shell/main_time.c",
|
||||
"cpukit/libmisc/shell/main_top.c",
|
||||
"cpukit/libmisc/shell/main_tty.c",
|
||||
"cpukit/libmisc/shell/main_umask.c",
|
||||
"cpukit/libmisc/shell/main_unmount.c",
|
||||
"cpukit/libmisc/shell/main_unsetenv.c",
|
||||
"cpukit/libmisc/shell/main_whoami.c",
|
||||
"cpukit/libmisc/shell/main_wkspaceinfo.c",
|
||||
"cpukit/libmisc/shell/mknod-pack_dev.h",
|
||||
"cpukit/libmisc/shell/pathnames-mv.h",
|
||||
"cpukit/libmisc/shell/print_heapinfo.c",
|
||||
"cpukit/libmisc/shell/print-ls.c",
|
||||
"cpukit/libmisc/shell/pwcache.c",
|
||||
"cpukit/libmisc/shell/shell_cmdset.c",
|
||||
"cpukit/libmisc/shell/shell_getchar.c",
|
||||
"cpukit/libmisc/shell/shell_getprompt.c",
|
||||
"cpukit/libmisc/shell/shell_makeargs.c",
|
||||
"cpukit/libmisc/shell/shell_script.c",
|
||||
"cpukit/libmisc/shell/shell-wait-for-input.c",
|
||||
"cpukit/libmisc/shell/shell.c",
|
||||
"cpukit/libmisc/shell/shellconfig.c",
|
||||
"cpukit/libmisc/shell/sysexits.h",
|
||||
"cpukit/libmisc/shell/utils-cp.c",
|
||||
"cpukit/libmisc/shell/utils-ls.c",
|
||||
"cpukit/libmisc/shell/verr.c",
|
||||
"cpukit/libmisc/shell/verrx.c",
|
||||
"cpukit/libmisc/shell/vis.c",
|
||||
"cpukit/libmisc/shell/vis.h",
|
||||
"cpukit/libmisc/shell/vwarn.c",
|
||||
"cpukit/libmisc/shell/vwarnx.c",
|
||||
"cpukit/libmisc/shell/warn.c",
|
||||
"cpukit/libmisc/shell/warnx.c",
|
||||
"cpukit/libmisc/shell/write_file.c",
|
||||
"cpukit/libmisc/uuid/clear.c",
|
||||
"cpukit/libmisc/uuid/compare.c",
|
||||
"cpukit/libmisc/uuid/copy.c",
|
||||
"cpukit/libmisc/uuid/gen_uuid.c",
|
||||
"cpukit/libmisc/uuid/isnull.c",
|
||||
"cpukit/libmisc/uuid/pack.c",
|
||||
"cpukit/libmisc/uuid/parse.c",
|
||||
"cpukit/libmisc/uuid/unpack.c",
|
||||
"cpukit/libmisc/uuid/unparse.c",
|
||||
"cpukit/libmisc/uuid/uuid_time.c",
|
||||
"cpukit/libmisc/uuid/uuidd.h",
|
||||
"cpukit/libmisc/uuid/uuidP.h"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/xz"]]
|
||||
files = [
|
||||
"cpukit/compression/xz/*.h",
|
||||
"cpukit/compression/xz/*.c"
|
||||
]
|
||||
|
||||
[[ignore."cpukit/zlib"]]
|
||||
files = [
|
||||
"cpukit/compression/zlib/*.c",
|
||||
"cpukit/compression/zlib/*.h",
|
||||
"cpukit/compression/zlib/doc/*",
|
||||
"cpukit/compression/zlib/ChangeLog.zlib",
|
||||
"cpukit/compression/zlib/FAQ"
|
||||
]
|
||||
|
||||
# These files have test characters that fail the char test
|
||||
[[ignore."testsuites/fstests/fsdosfsname01"]]
|
||||
exclude = ["char"]
|
||||
files = [
|
||||
"testsuites/fstests/fsdosfsname01/init.c",
|
||||
"testsuites/fstests/fsdosfsname01/create_files.cs",
|
||||
"testsuites/fstests/fsdosfsname01/files.h"
|
||||
]
|
||||
|
||||
[[ignore."yaml"]]
|
||||
files = [
|
||||
"yaml/*"
|
||||
]
|
||||
261
CODEOWNERS
261
CODEOWNERS
@@ -1,261 +0,0 @@
|
||||
# Please keep users, directories and files sorted alphabetically.
|
||||
# Directories first
|
||||
#
|
||||
# If there is more than 1 user in a section it must be promoted to a group in
|
||||
# /approvers
|
||||
|
||||
[General Maintainer] @approvers/general/maintainer
|
||||
*
|
||||
|
||||
[Documentation] @approvers/docs
|
||||
*/README
|
||||
*.md
|
||||
*.rst
|
||||
*.txt
|
||||
|
||||
|
||||
# CPUKit
|
||||
########
|
||||
|
||||
[CPUKit libdebugger] @approvers/cpukit/libdebugger
|
||||
/cpukit/libdebugger
|
||||
|
||||
[CPUKit libdl] @approvers/cpukit/libdl
|
||||
/cpukit/libdl
|
||||
|
||||
[CPUKit libdrvmgr] @approvers/cpukit/libdrvmgr
|
||||
/cpukit/libdrvmgr
|
||||
|
||||
[CPUKit libgnat] @joel
|
||||
/cpukit/libgnat
|
||||
|
||||
[CPUKit librtemscxx] @approvers/cpukit/librtemscxx
|
||||
/cpukit/librtemscxx
|
||||
|
||||
[CPUKit libstdthreads] @approvers/cpukit/libstdthreads
|
||||
/cpukit/libstdthreads
|
||||
|
||||
|
||||
# Architectures
|
||||
###############
|
||||
|
||||
[Arch AArch64] @approvers/arch/aarch64
|
||||
/bsps/aarch64/
|
||||
/cpukit/score/cpu/aarch64/
|
||||
/spec/build/bsps/aarch64/
|
||||
/cpukit/libdebugger/rtems-debugger-aarch64.v
|
||||
/cpukit/libdl/rtl-mdreloc-aarch64.c
|
||||
/spec/build/cpukit/*aarch64.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch ARM] @approvers/arch/arm
|
||||
/bsps/arm/
|
||||
/bsps/include/arm/
|
||||
/bsps/include/xil/arm/
|
||||
/bsps/shared/freebsd/sys/arm/
|
||||
/bsps/shared/xil/arm/
|
||||
/cpukit/score/cpu/arm/
|
||||
/spec/build/bsps/arm/
|
||||
/cpukit/libdebugger/rtems-debugger-arm.c
|
||||
/cpukit/libdl/*arm*
|
||||
/spec/build/cpukit/*arm.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch Blackfin] @approvers/arch/bfin
|
||||
/bsps/bfin/
|
||||
/cpukit/score/cpu/bfin/
|
||||
/spec/build/bsps/bfin/
|
||||
/cpukit/libdl/rtl-mdreloc-bfin.c
|
||||
/spec/build/cpukit/cpubfin.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch i386] @approvers/arch/i386
|
||||
/bsps/i386/
|
||||
/cpukit/score/cpu/i386/
|
||||
/spec/build/bsps/i386/
|
||||
/cpukit/libdebugger/rtems-debugger-i386.c
|
||||
/cpukit/libdl/rtl-mdreloc-i386.c
|
||||
/spec/build/cpukit/*i386*
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch LatticeMico32] @approvers/arch/lm32
|
||||
/bsps/lm32/
|
||||
/cpukit/score/cpu/lm32/
|
||||
/spec/build/bsps/lm32/
|
||||
/cpukit/libdl/rtl-mdreloc-lm32.c
|
||||
/spec/build/cpukit/cpulm32.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch Motorola 68000] @approvers/arch/m68k
|
||||
/bsps/m68k/
|
||||
/cpukit/score/cpu/m68k/
|
||||
/spec/build/bsps/m68k/
|
||||
/cpukit/libdl/rtl-mdreloc-m68k.c
|
||||
/spec/build/cpukit/*m68k*
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch MicroBlaze] @approvers/arch/microblaze
|
||||
/bsps/include/xil/microblaze/
|
||||
/bsps/microblaze/
|
||||
/cpukit/score/cpu/microblaze/
|
||||
/spec/build/bsps/microblaze/
|
||||
/cpukit/libdebugger/rtems-debugger-microblaze.c
|
||||
/cpukit/libdl/rtl-mdreloc-microblaze.c
|
||||
/spec/build/cpukit/*microblaze*
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch MIPS] @approvers/arch/mips
|
||||
/bsps/mips/
|
||||
/cpukit/score/cpu/mips/
|
||||
/spec/build/bsps/mips/
|
||||
/cpukit/libdl/rtl-mdreloc-mips.c
|
||||
/spec/build/cpukit/*mips.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch Moxie] @approvers/arch/moxie
|
||||
/bsps/moxie/
|
||||
/cpukit/score/cpu/moxie/
|
||||
/spec/build/bsps/moxie/
|
||||
/cpukit/libdl/rtl-mdreloc-moxie.c
|
||||
/spec/build/cpukit/*moxie.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch Nios II] @approvers/arch/nios2
|
||||
/bsps/nios2/
|
||||
/cpukit/score/cpu/nios2/
|
||||
/spec/build/bsps/nios2/
|
||||
/spec/build/cpukit/*nios2.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch OpenRISC 1000] @approvers/arch/or1k
|
||||
/bsps/or1k/
|
||||
/cpukit/score/cpu/or1k/
|
||||
/spec/build/bsps/or1k/
|
||||
/spec/build/cpukit/*or1k.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch PowerPC] @approvers/arch/powerpc
|
||||
/bsps/powerpc/
|
||||
/cpukit/score/cpu/powerpc/
|
||||
/spec/build/bsps/powerpc/
|
||||
/cpukit/libdl/rtl-mdreloc-powerpc.c
|
||||
/spec/build/cpukit/*powerpc.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch RISC-V] @approvers/arch/risc-v
|
||||
/bsps/riscv
|
||||
/cpukit/score/cpu/riscv
|
||||
/spec/build/bsps/riscv
|
||||
/cpukit/libdl/rtl-mdreloc-riscv.c
|
||||
/spec/build/cpukit/*riscv.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch SuperH] @approvers/arch/superh
|
||||
/bsps/sh/
|
||||
/cpukit/score/cpu/sh/
|
||||
/spec/build/bsps/sh/
|
||||
/spec/build/cpukit/cpush.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch SPARC] @approvers/arch/sparc
|
||||
/bsps/sparc/
|
||||
/cpukit/score/cpu/sparc/
|
||||
/spec/build/bsps/sparc/
|
||||
/spec/build/cpukit/cpusparc.yml
|
||||
/spec/build/cpukit/objdlsparc.yml
|
||||
/spec/build/testsuites/validation/bsps/*-sparc-*
|
||||
/testsuites/validation/bsps/*-sparc-*
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch SPARC64] @approvers/arch/sparc64
|
||||
/bsps/sparc64/
|
||||
/cpukit/score/cpu/sparc64/
|
||||
/spec/build/bsps/sparc64/
|
||||
/spec/build/cpukit/*sparc64.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch V850] @approvers/arch/v850
|
||||
/bsps/v850/
|
||||
/cpukit/score/cpu/v850/
|
||||
/spec/build/bsps/v850/
|
||||
/cpukit/libdl/rtl-mdreloc-v850.c
|
||||
/spec/build/cpukit/*v850.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
|
||||
|
||||
[Arch X86_64] @approvers/arch/x86_64
|
||||
/bsps/x86_64/
|
||||
/cpukit/score/cpu/x86_64/
|
||||
/spec/build/bsps/x86_64/
|
||||
/spec/build/cpukit/*x8664.yml
|
||||
*/README @approvers/docs
|
||||
*.md @approvers/docs
|
||||
*.rst @approvers/docs
|
||||
*.txt @approvers/docs
|
||||
56
INSTALL
Normal file
56
INSTALL
Normal file
@@ -0,0 +1,56 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
NOTE: The string <release> should be replaced with
|
||||
the appropriate release number of RTEMS.
|
||||
|
||||
This file only discusses the installation of .tgz files.
|
||||
For more detailed information on the installation of RTEMS,
|
||||
refer to the Release Notes manual in the file
|
||||
/pub/rtems/releases/<release>/doc/c_or_ada/relnotes.tgz on
|
||||
lancelot.gcs.redstone.army.mil.
|
||||
|
||||
UNCOMPRESSING .tgz FILES
|
||||
===========================
|
||||
Many of the files found in this directory and its subdirectories
|
||||
are gzip'ed, tar archive files. These files have the ".tgz"
|
||||
extension. They were compressed with gzip version 1.2.4.
|
||||
|
||||
Use a command sequence similar to the following to uncompress each
|
||||
file:
|
||||
|
||||
gzcat FILE.tgz | tar xvof -
|
||||
|
||||
where FILE.tgz is the file to be installed. This procedure will
|
||||
extract the files in the archive into the current directory.
|
||||
All of the .tgz files associated with this release RTEMS will
|
||||
place their contents in a subdirectory rtems-<release> in the current
|
||||
directory.
|
||||
|
||||
If you are unsure of what is in an RTEMS archive file, then use
|
||||
the following command sequence to get a listing of the contents:
|
||||
|
||||
gzcat FILE.tgz | tar tvf -
|
||||
|
||||
NOTES:
|
||||
|
||||
(1) The "-o" option to tar is included on the tar command line
|
||||
so that the user extracting the tar archive will own the extracted
|
||||
files.
|
||||
|
||||
(2) gzcat is sometimes installed as zcat. Be warned that on many
|
||||
(most) UNIX machines, zcat is associated with compress (.Z files).
|
||||
|
||||
(3) If you do not have gzip 1.2.4, it is available from numerous sites
|
||||
including this one. Other sites include prep.ai.mit.edu and
|
||||
gatekeeper.dec.com.
|
||||
|
||||
(4) The GNU archive files included in this distribution are packaged
|
||||
exactly like they are on official GNU ftp sites. When extracting
|
||||
GNU archives, they will not extract under a rtems-<version>
|
||||
directory. They will extract themselves under a directory which
|
||||
is the name and version of the tool in question. For example,
|
||||
gcc-2.5.8.tgz will extract its contents into the subdirectory
|
||||
gcc-2.5.8.
|
||||
|
||||
118
LICENSE
Normal file
118
LICENSE
Normal file
@@ -0,0 +1,118 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
LICENSE INFORMATION
|
||||
|
||||
For the purposes of this document the Real Time Executive for
|
||||
Missile Systems (RTEMS) is defined to include all source code,
|
||||
documentation, shell utilities developed by On-Line Applications
|
||||
Research Corporation (OAR) under contract of the U.S. Army
|
||||
Missile Command. OAR obtained the copyright for RTEMS and
|
||||
subsequently assigned ownership of said copyright to the
|
||||
U.S. Government. As part of this transfer, OAR waived all
|
||||
claims of ownership for RTEMS. Since OAR no longer makes claims
|
||||
of ownership of RTEMS, OAR in no event shall be held liable
|
||||
for damages including any general, special, incidental or
|
||||
consequential damages arising out of the use or inability
|
||||
to use the RTEMS software or documentation or of the support
|
||||
services provided (including but not limited to loss of data or
|
||||
data being rendered inaccurate or losses sustained by you or
|
||||
third parties or a failure of the program to operate with any
|
||||
other programs), even if advised of the possibility of such damages.
|
||||
|
||||
Simply stated any file containing the U.S. Government
|
||||
copyright notice or relocatables derived from one or more of
|
||||
these files are covered by this agreement.
|
||||
|
||||
RTEMS may be reproduced by or for the U.S. Government pursuant
|
||||
to the copyright license under the clause at DFARS 252.227-7013.
|
||||
The following notice must appear in all copies of RTEMS and its
|
||||
derivatives:
|
||||
|
||||
COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
|
||||
On-Line Applications Research Corporation (OAR).
|
||||
All rights assigned to U.S. Government, 1994.
|
||||
|
||||
This material may be reproduced by or for the U.S. Government
|
||||
pursuant to the copyright license under the clause at DFARS
|
||||
252.227-7013. This notice must appear in all copies of this
|
||||
material and its derivatives.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions
|
||||
are met:
|
||||
|
||||
1. Redistributions of source code and documentation must retain the
|
||||
above copyright notice, this list of conditions and the following
|
||||
disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
Redistributions in binary form must contain or make available the
|
||||
RTEMS source code.
|
||||
|
||||
3. All advertising materials mentioning features or use of this software
|
||||
must display the following acknowledgement:
|
||||
This product includes software developed for the U.S. Government
|
||||
by On-Line Applications Research Corp.
|
||||
|
||||
4. Neither the name of the author nor the U.S. Government may be used to
|
||||
endorse or promote products derived from this software without specific
|
||||
prior written permission.
|
||||
|
||||
|
||||
RTEMS is provided "AS IS" without warranty of any kind, either
|
||||
expressed or implied, including, but not limited to, the implied
|
||||
warranties of merchantability, title and fitness for a
|
||||
particular purpose. The U.S. Government does not warrant that
|
||||
the RTEMS software or documentation will satisfy your requirements
|
||||
or that the software and documentation are without defect or error
|
||||
or that the operation of the software will be uninterrupted.
|
||||
|
||||
The U.S. Government shall in no event shall be held liable for
|
||||
damages including any general, special, incidental or consequential
|
||||
damages arising out of the use or inability to use the RTEMS software
|
||||
or documentation or of the support services provided (including
|
||||
but not limited to loss of data or data being rendered
|
||||
inaccurate or losses sustained by you or third parties or a
|
||||
failure of the program to operate with any other programs), even
|
||||
if the U.S. Government has been advised of the possibility of such damages.
|
||||
|
||||
The U.S. Government reserves the right to revise this material
|
||||
and to make changes from time to time in the content hereof without
|
||||
obligation to notify anyone or any organization of such revision
|
||||
or changes.
|
||||
|
||||
OAR remains the sole organization authorized by contract to
|
||||
distribute or provide support and training for the Real-Time
|
||||
Executive for Multiprocessor Systems (RTEMS).
|
||||
|
||||
In order to promote future research activities within the U.S.
|
||||
Government, we request that potential users of RTEMS notify us
|
||||
as to the systems that RTEMS is being utilized. This will allow
|
||||
us to publicize our Dual-Use / Reuse capabilities in support of
|
||||
the current administration's goals. This can be accomplished by
|
||||
calling the RTEMS phone numbers published in the documentation
|
||||
or by electronic mail to "rtems@redstone.army.mil". Your
|
||||
cooperation is greatly appreciated. Again, thank you for using
|
||||
RTEMS.
|
||||
|
||||
RTEMS
|
||||
U.S. ARMY Missile Command
|
||||
ATTN: AMSMI-RD-GC-S
|
||||
Redstone Arsenal, AL 35898-5254
|
||||
Voice: (205) 842-6906
|
||||
FAX: (205) 842-6917
|
||||
EMAIL: rtems@redstone.army.mil
|
||||
|
||||
|
||||
On-Line Applications Research Corporation.
|
||||
2227 Drake Avenue SW
|
||||
Suite 10-F
|
||||
Huntsville, AL 35805
|
||||
(205) 883-0131
|
||||
|
||||
|
||||
|
||||
|
||||
1321
LICENSE.md
1321
LICENSE.md
File diff suppressed because it is too large
Load Diff
93
README
Normal file
93
README
Normal file
@@ -0,0 +1,93 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
Directory Overview
|
||||
==================
|
||||
|
||||
This is the top level of the RTEMS directory structure. The following
|
||||
is a description of the files and directories in this directory:
|
||||
|
||||
INSTALL
|
||||
Rudimentary installation instructions. For more detailed
|
||||
information please see the Release Notes. The Postscript
|
||||
version of this manual can be found in the file
|
||||
c_or_ada/doc/relnotes.tgz.
|
||||
|
||||
LICENSE
|
||||
Required legalese.
|
||||
|
||||
README
|
||||
This file.
|
||||
|
||||
c
|
||||
This directory contains the source code for the C
|
||||
implementation of RTEMS as well as the test suites, sample
|
||||
applications, Board Support Packages, Device Drivers, and
|
||||
support libraries.
|
||||
|
||||
doc
|
||||
This directory contains the PDL for the RTEMS executive.
|
||||
|
||||
Ada versus C
|
||||
============
|
||||
|
||||
There are two implementations of RTEMS in this source tree --
|
||||
in Ada and in C. These two implementations are functionally
|
||||
and structurally equivalent. The C implementation follows
|
||||
the packaging conventions and hiearchical nature of the Ada
|
||||
implementation. In addition, a style has been followed which
|
||||
allows one to easily find the corresponding Ada and C
|
||||
implementations.
|
||||
|
||||
File names in C and code placement was carefully designed to insure
|
||||
a close mapping to the Ada implementation. The following file name
|
||||
extensions are used:
|
||||
|
||||
.adb - Ada body
|
||||
.ads - Ada specification
|
||||
.adp - Ada body requiring preprocessing
|
||||
.inc - include file for .adp files
|
||||
|
||||
.c - C body (non-inlined routines)
|
||||
.inl - C body (inlined routines)
|
||||
.h - C specification
|
||||
|
||||
In the executive source, XYZ.c and XYZ.inl correspond directly to a
|
||||
single XYZ.adb or XYZ.adp file. A .h file corresponds directly to
|
||||
the .ads file. There are only a handful of .inc files in the
|
||||
Ada source and these are used to insure that the desired simple
|
||||
inline textual expansion is performed. This avoids scoping and
|
||||
calling convention side-effects in carefully constructed tests
|
||||
which usually test context switch behavior.
|
||||
|
||||
In addition, in Ada code and data name references are always fully
|
||||
qualified as PACKAGE.NAME. In C, this convention is followed
|
||||
by having the package name as part of the name itself and using a
|
||||
capital letter to indicate the presence of a "." level. So we have
|
||||
PACKAGE.NAME in Ada and _Package_Name in C. The leading "_" in C
|
||||
is used to avoid naming conflicts between RTEMS and user variables.
|
||||
By using these conventions, one can easily compare the C and Ada
|
||||
implementations.
|
||||
|
||||
The most noticeable difference between the C and Ada83 code is
|
||||
the inability to easily obtain a "typed pointer" in Ada83.
|
||||
Using the "&" operator in C yields a pointer with a specific type.
|
||||
The 'Address attribute is the closest feature in Ada83. This
|
||||
returns a System.Address and this must be coerced via Unchecked_Conversion
|
||||
into an access type of the desired type. It is easy to view
|
||||
System.Address as similar to a "void *" in C, but this is not the case.
|
||||
A "void *" can be assigned to any other pointer type without an
|
||||
explicit conversion.
|
||||
|
||||
The solution adopted to this problem was to provide two routines for
|
||||
each access type in the Ada implementation -- one to convert from
|
||||
System.Address to the access type and another to go the opposite
|
||||
direction. This results in code which accomplishes the same thing
|
||||
as the corresponding C but it is easier to get lost in the clutter
|
||||
of the apparent subprogram invocations than the "less bulky"
|
||||
C equivalent.
|
||||
|
||||
A related difference is the types which are only in Ada which are used
|
||||
for pointers to arrays. These types do not exist and are not needed
|
||||
in the C implementation.
|
||||
46
README.md
46
README.md
@@ -1,46 +0,0 @@
|
||||
Real-Time Executive for Multiprocessing Systems
|
||||
===============================================
|
||||
|
||||
RTEMS is a real-time executive (kernel) which provides a high performance
|
||||
environment for embedded applications with the following features:
|
||||
|
||||
* Standards based user interfaces.
|
||||
* Multitasking capabilities.
|
||||
* Homogeneous and heterogeneous multiprocessor systems.
|
||||
* Event-driven, priority-based, preemptive scheduling.
|
||||
* Optional rate monotonic scheduling.
|
||||
* Intertask communication and synchronisation.
|
||||
* Priority inheritance.
|
||||
* Responsive interrupt management.
|
||||
* Dynamic memory allocation.
|
||||
* High level of user configurability.
|
||||
* Open source with a friendly user license.
|
||||
|
||||
|
||||
Project git repositories are located at:
|
||||
|
||||
* https://gitlab.rtems.org/rtems/
|
||||
|
||||
|
||||
Online documentation is available at:
|
||||
|
||||
* https://docs.rtems.org/
|
||||
|
||||
|
||||
RTEMS Doxygen for CPUKit:
|
||||
|
||||
* https://docs.rtems.org/doxygen/branches/master/
|
||||
|
||||
|
||||
RTEMS POSIX 1003.1 Compliance Guide:
|
||||
|
||||
* https://docs.rtems.org/branches/master/posix-compliance/
|
||||
|
||||
|
||||
RTEMS Mailing Lists for general purpose use the users list and for developers
|
||||
use the devel list.
|
||||
|
||||
* https://lists.rtems.org/mailman/listinfo
|
||||
|
||||
|
||||
The version number for this software is indicated in the VERSION file.
|
||||
18
SUPPORT
Normal file
18
SUPPORT
Normal file
@@ -0,0 +1,18 @@
|
||||
#
|
||||
# $Id$
|
||||
#
|
||||
|
||||
For support and training contact:
|
||||
|
||||
On-Line Applications Research
|
||||
2227 Drake Avenue SW Suite 10-F
|
||||
Huntsville AL 35805
|
||||
(205) 883-0131
|
||||
|
||||
OAR offers support and classes for RTEMS as well as custom
|
||||
development services such as ports to new processors and
|
||||
the development of custom board support packages and device
|
||||
drivers.
|
||||
|
||||
OAR developed RTEMS under contract to the U.S. Army Missile Command.
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief Console Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/bspIo.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <bsp/console-termios.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
arm_pl011_context a53_qemu_vpl011_context = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
|
||||
.regs = (arm_pl011_uart *) BSP_A53_QEMU_VPL011_BASE,
|
||||
.initial_baud = 115200,
|
||||
.clock = 24000000
|
||||
};
|
||||
|
||||
const console_device console_device_table[] = {
|
||||
{
|
||||
.device_file = "/dev/ttyS0",
|
||||
.probe = console_device_probe_default,
|
||||
.handler = &arm_pl011_fns,
|
||||
.context = &a53_qemu_vpl011_context.base
|
||||
}
|
||||
};
|
||||
|
||||
const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
|
||||
|
||||
static void output_char( char c )
|
||||
{
|
||||
arm_pl011_write_polled(&a53_qemu_vpl011_context.base, c);
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = output_char;
|
||||
|
||||
BSP_polling_getchar_function_type BSP_poll_char = NULL;
|
||||
@@ -1,74 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief Core BSP definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_A53_QEMU_BSP_H
|
||||
#define LIBBSP_AARCH64_A53_QEMU_BSP_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0x08010000
|
||||
#define BSP_ARM_GIC_DIST_BASE 0x08000000
|
||||
#define BSP_ARM_GIC_REDIST_BASE 0x080A0000
|
||||
|
||||
#define BSP_A53_QEMU_VPL011_BASE 0x9000000
|
||||
#define BSP_A53_QEMU_VPL011_LENGTH 0x1000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_A53_QEMU_BSP_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP IRQ definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_A53_IRQ_H
|
||||
#define LIBBSP_AARCH64_A53_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT 256
|
||||
|
||||
/* Interrupts vectors */
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define BSP_VPL011_SPI 32
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_A53_IRQ_H */
|
||||
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP tm27 header
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <dev/irq/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP Startup
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
rtems_cache_coherent_add_area(
|
||||
bsp_section_nocacheheap_begin,
|
||||
(uintptr_t) bsp_section_nocacheheap_size
|
||||
);
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP Startup Hooks
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#ifdef BSP_START_ENABLE_EL3_START_SUPPORT
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
#endif
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
|
||||
{
|
||||
AArch64_start_set_vector_base();
|
||||
bsp_start_copy_sections();
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -1,70 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A72
|
||||
*
|
||||
* @brief Console Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/bspIo.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <bsp/console-termios.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
arm_pl011_context a72_qemu_vpl011_context = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
|
||||
.regs = (arm_pl011_uart *) BSP_A72_QEMU_VPL011_BASE,
|
||||
.initial_baud = 115200,
|
||||
.clock = 24000000
|
||||
};
|
||||
|
||||
const console_device console_device_table[] = {
|
||||
{
|
||||
.device_file = "/dev/ttyS0",
|
||||
.probe = console_device_probe_default,
|
||||
.handler = &arm_pl011_fns,
|
||||
.context = &a72_qemu_vpl011_context.base
|
||||
}
|
||||
};
|
||||
|
||||
const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
|
||||
|
||||
static void output_char( char c )
|
||||
{
|
||||
arm_pl011_write_polled(&a72_qemu_vpl011_context.base, c);
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = output_char;
|
||||
|
||||
BSP_polling_getchar_function_type BSP_poll_char = NULL;
|
||||
@@ -1,74 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A72
|
||||
*
|
||||
* @brief Core BSP definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_A72_QEMU_BSP_H
|
||||
#define LIBBSP_AARCH64_A72_QEMU_BSP_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0x08010000
|
||||
#define BSP_ARM_GIC_DIST_BASE 0x08000000
|
||||
#define BSP_ARM_GIC_REDIST_BASE 0x080A0000
|
||||
|
||||
#define BSP_A72_QEMU_VPL011_BASE 0x9000000
|
||||
#define BSP_A72_QEMU_VPL011_LENGTH 0x1000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_A72_QEMU_BSP_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A72
|
||||
*
|
||||
* @brief BSP IRQ definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_A72_IRQ_H
|
||||
#define LIBBSP_AARCH64_A72_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT 1020
|
||||
|
||||
/* Interrupts vectors */
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define BSP_VPL011_SPI 32
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_A72_IRQ_H */
|
||||
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A72
|
||||
*
|
||||
* @brief BSP tm27 header
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <dev/irq/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP Startup
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
rtems_cache_coherent_add_area(
|
||||
bsp_section_nocacheheap_begin,
|
||||
(uintptr_t) bsp_section_nocacheheap_size
|
||||
);
|
||||
}
|
||||
@@ -1,52 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64A53
|
||||
*
|
||||
* @brief BSP Startup Hooks
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#ifdef BSP_START_ENABLE_EL3_START_SUPPORT
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
#endif
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
|
||||
{
|
||||
AArch64_start_set_vector_base();
|
||||
bsp_start_copy_sections();
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -1,267 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup aarch64_start
|
||||
*
|
||||
* @brief AArch64 MMU configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_SHARED_AARCH64_MMU_H
|
||||
#define LIBBSP_AARCH64_SHARED_AARCH64_MMU_H
|
||||
|
||||
#include <bsp/fatal.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <bspopts.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef struct {
|
||||
uintptr_t begin;
|
||||
uintptr_t end;
|
||||
uint64_t flags;
|
||||
} aarch64_mmu_config_entry;
|
||||
|
||||
#define AARCH64_MMU_DEFAULT_SECTIONS \
|
||||
{ \
|
||||
.begin = (uintptr_t) bsp_section_fast_text_begin, \
|
||||
.end = (uintptr_t) bsp_section_fast_text_end, \
|
||||
.flags = AARCH64_MMU_CODE_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_fast_data_begin, \
|
||||
.end = (uintptr_t) bsp_section_fast_data_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_start_begin, \
|
||||
.end = (uintptr_t) bsp_section_start_end, \
|
||||
.flags = AARCH64_MMU_CODE_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_vector_begin, \
|
||||
.end = (uintptr_t) bsp_section_vector_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_text_begin, \
|
||||
.end = (uintptr_t) bsp_section_text_end, \
|
||||
.flags = AARCH64_MMU_CODE_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_rodata_begin, \
|
||||
.end = (uintptr_t) bsp_section_rodata_end, \
|
||||
.flags = AARCH64_MMU_DATA_RO_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_data_begin, \
|
||||
.end = (uintptr_t) bsp_section_data_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_bss_begin, \
|
||||
.end = (uintptr_t) bsp_section_bss_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_rtemsstack_begin, \
|
||||
.end = (uintptr_t) bsp_section_rtemsstack_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_noinit_begin, \
|
||||
.end = (uintptr_t) bsp_section_noinit_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_work_begin, \
|
||||
.end = (uintptr_t) bsp_section_work_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_stack_begin, \
|
||||
.end = (uintptr_t) bsp_section_stack_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_nocache_begin, \
|
||||
.end = (uintptr_t) bsp_section_nocache_end, \
|
||||
.flags = AARCH64_MMU_DEVICE \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_section_nocachenoload_begin, \
|
||||
.end = (uintptr_t) bsp_section_nocachenoload_end, \
|
||||
.flags = AARCH64_MMU_DEVICE \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_translation_table_base, \
|
||||
.end = (uintptr_t) bsp_translation_table_end, \
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED \
|
||||
}, { \
|
||||
.begin = (uintptr_t) bsp_start_vector_table_begin, \
|
||||
.end = (uintptr_t) bsp_start_vector_table_end, \
|
||||
.flags = AARCH64_MMU_CODE_CACHED \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This is the AArch64 MMU configuration table.
|
||||
*
|
||||
* The default table is provided by the BSP. Applications may provide their
|
||||
* own.
|
||||
*/
|
||||
extern const aarch64_mmu_config_entry aarch64_mmu_config_table[];
|
||||
|
||||
/**
|
||||
* @brief This is the count of entries in the AArch64 MMU configuration table.
|
||||
*
|
||||
* The default table is provided by the BSP. Applications may provide their
|
||||
* own.
|
||||
*/
|
||||
extern const size_t aarch64_mmu_config_table_size;
|
||||
|
||||
/**
|
||||
* @brief This structure represents the state to maintain the MMU translation
|
||||
* tables.
|
||||
*/
|
||||
typedef struct {
|
||||
/**
|
||||
* @brief This member references the translation table base.
|
||||
*/
|
||||
uint64_t *ttb;
|
||||
|
||||
/**
|
||||
* @brief This member contains the count of used page tables.
|
||||
*
|
||||
* A maximum of ::AARCH64_MMU_TRANSLATION_TABLE_PAGES can be used.
|
||||
*/
|
||||
size_t used_page_tables;
|
||||
} aarch64_mmu_control;
|
||||
|
||||
/**
|
||||
* @brief This object is used to maintain the MMU translation tables.
|
||||
*/
|
||||
extern aarch64_mmu_control aarch64_mmu_instance;
|
||||
|
||||
/**
|
||||
* @brief Sets the MMU translation table entries associated with the memory
|
||||
* region.
|
||||
*
|
||||
* @param[in, out] control is a reference to the MMU control state.
|
||||
*
|
||||
* @param[in] config is the configuration entry with the memory region and
|
||||
* region attributes.
|
||||
*
|
||||
* @retval ::RTEMS_SUCCESSFUL The requested operation was successful.
|
||||
*
|
||||
* @retval ::RTEMS_INVALID_ADDRESS The begin address of the memory region
|
||||
* cannot be mapped by the MMU.
|
||||
*
|
||||
* @retval ::RTEMS_INVALID_SIZE The end address of the memory region cannot be
|
||||
* mapped by the MMU.
|
||||
*
|
||||
* @retval ::RTEMS_TOO_MANY There was no page table entry available to perform
|
||||
* the mapping.
|
||||
*/
|
||||
rtems_status_code aarch64_mmu_set_translation_table_entries(
|
||||
aarch64_mmu_control *control,
|
||||
const aarch64_mmu_config_entry *config
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Sets up the MMU translation table.
|
||||
*
|
||||
* The memory regions of the configuration table are mapped by the MMU. If a
|
||||
* mapping is infeasible, then the BSP fatal error
|
||||
* ::AARCH64_FATAL_MMU_CANNOT_MAP_BLOCK will be issued.
|
||||
*
|
||||
* @param[in, out] control is a reference to the MMU control state.
|
||||
*
|
||||
* @param[in] config_table is the configuration table with memory regions and
|
||||
* region attributes.
|
||||
*
|
||||
* @param config_count is the count of configuration table entries.
|
||||
*/
|
||||
void aarch64_mmu_setup_translation_table(
|
||||
aarch64_mmu_control *control,
|
||||
const aarch64_mmu_config_entry *config_table,
|
||||
size_t config_count
|
||||
);
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void
|
||||
aarch64_mmu_enable( const aarch64_mmu_control *control )
|
||||
{
|
||||
uint64_t sctlr;
|
||||
|
||||
/* CPUECTLR_EL1.SMPEN is already set on ZynqMP and is not writable */
|
||||
|
||||
/* Flush and invalidate cache */
|
||||
rtems_cache_flush_entire_data();
|
||||
|
||||
_AArch64_Write_ttbr0_el1( (uintptr_t) control->ttb );
|
||||
_AARCH64_Instruction_synchronization_barrier();
|
||||
|
||||
/* Enable MMU and cache */
|
||||
sctlr = _AArch64_Read_sctlr_el1();
|
||||
sctlr |= AARCH64_SCTLR_EL1_I | AARCH64_SCTLR_EL1_C | AARCH64_SCTLR_EL1_M;
|
||||
_AArch64_Write_sctlr_el1( sctlr );
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void
|
||||
aarch64_mmu_disable( void )
|
||||
{
|
||||
uint64_t sctlr;
|
||||
|
||||
/*
|
||||
* Flush data cache before disabling the MMU. While the MMU is disabled, all
|
||||
* accesses are treated as uncached device memory.
|
||||
*/
|
||||
rtems_cache_flush_entire_data();
|
||||
|
||||
/* Disable MMU */
|
||||
sctlr = _AArch64_Read_sctlr_el1();
|
||||
sctlr &= ~(AARCH64_SCTLR_EL1_M);
|
||||
_AArch64_Write_sctlr_el1( sctlr );
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void aarch64_mmu_setup( void )
|
||||
{
|
||||
/* Set TCR */
|
||||
/* 256TB/48 bits mappable (64-0x10) */
|
||||
_AArch64_Write_tcr_el1(
|
||||
AARCH64_TCR_EL1_T0SZ( 0x10 ) | AARCH64_TCR_EL1_IRGN0( 0x1 ) |
|
||||
AARCH64_TCR_EL1_ORGN0( 0x1 ) | AARCH64_TCR_EL1_SH0( 0x3 ) |
|
||||
AARCH64_TCR_EL1_TG0( 0x0 ) | AARCH64_TCR_EL1_IPS( 0x5ULL ) |
|
||||
AARCH64_TCR_EL1_EPD1
|
||||
);
|
||||
|
||||
/* Set MAIR */
|
||||
_AArch64_Write_mair_el1(
|
||||
AARCH64_MAIR_EL1_ATTR0( 0x0 ) | AARCH64_MAIR_EL1_ATTR1( 0x4 ) |
|
||||
AARCH64_MAIR_EL1_ATTR2( 0x44 ) | AARCH64_MAIR_EL1_ATTR3( 0xFF )
|
||||
);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_SHARED_AARCH64_MMU_H */
|
||||
@@ -1,86 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsLinkerSymbolsAArch64
|
||||
*
|
||||
* @brief This header file provides interfaces to AArch64-specific linker
|
||||
* symbols and sections.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_SHARED_LINKER_SYMBOLS_H
|
||||
#define LIBBSP_AARCH64_SHARED_LINKER_SYMBOLS_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @defgroup RTEMSBSPsLinkerSymbolsAArch64 AArch64 Linker Symbols
|
||||
*
|
||||
* @ingroup RTEMSBSPsLinkerSymbols
|
||||
*
|
||||
* @brief This group provides support for AArch64-specific linker symbols and
|
||||
* sections.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef ASM
|
||||
#define LINKER_SYMBOL(sym) extern char sym [];
|
||||
#else
|
||||
#define LINKER_SYMBOL(sym) .extern sym
|
||||
#endif
|
||||
|
||||
LINKER_SYMBOL(bsp_stack_exception_size)
|
||||
LINKER_SYMBOL(bsp_stack_hyp_size)
|
||||
|
||||
LINKER_SYMBOL(bsp_section_vector_begin)
|
||||
LINKER_SYMBOL(bsp_section_vector_end)
|
||||
LINKER_SYMBOL(bsp_section_vector_size)
|
||||
|
||||
LINKER_SYMBOL(bsp_vector_table_begin)
|
||||
LINKER_SYMBOL(bsp_vector_table_end)
|
||||
LINKER_SYMBOL(bsp_vector_table_size)
|
||||
|
||||
LINKER_SYMBOL(bsp_start_vector_table_begin)
|
||||
LINKER_SYMBOL(bsp_start_vector_table_end)
|
||||
LINKER_SYMBOL(bsp_start_vector_table_size)
|
||||
|
||||
LINKER_SYMBOL(bsp_translation_table_base)
|
||||
LINKER_SYMBOL(bsp_translation_table_end)
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_SHARED_LINKER_SYMBOLS_H */
|
||||
@@ -1,184 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup aarch64_start
|
||||
*
|
||||
* @brief Aarch64 system low level start.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_SHARED_START_H
|
||||
#define LIBBSP_AARCH64_SHARED_START_H
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include <bsp/linker-symbols.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @defgroup aarch64_start System Start
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief Aarch64 system low level start.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BSP_START_TEXT_SECTION __attribute__((section(".bsp_start_text")))
|
||||
|
||||
#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
|
||||
|
||||
/**
|
||||
* @brief System start entry.
|
||||
*/
|
||||
void _start(void);
|
||||
|
||||
/**
|
||||
* @brief Start entry hook 0.
|
||||
*
|
||||
* This hook will be called from the start entry code after all modes and
|
||||
* stack pointers are initialized but before the copying of the exception
|
||||
* vectors.
|
||||
*/
|
||||
void bsp_start_hook_0(void);
|
||||
|
||||
/**
|
||||
* @brief Start entry hook 1.
|
||||
*
|
||||
* This hook will be called from the start entry code after copying of the
|
||||
* exception vectors but before the call to boot_card().
|
||||
*/
|
||||
void bsp_start_hook_1(void);
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void
|
||||
bsp_start_memcpy_libc(void *dest, const void *src, size_t n)
|
||||
{
|
||||
if (dest != src) {
|
||||
memcpy(dest, src, n);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copies all standard sections from the load to the runtime area.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections(void)
|
||||
{
|
||||
/* Copy .text section */
|
||||
bsp_start_memcpy_libc(
|
||||
(int *) bsp_section_text_begin,
|
||||
(const int *) bsp_section_text_load_begin,
|
||||
(size_t) bsp_section_text_size
|
||||
);
|
||||
|
||||
/* Copy .rodata section */
|
||||
bsp_start_memcpy_libc(
|
||||
(int *) bsp_section_rodata_begin,
|
||||
(const int *) bsp_section_rodata_load_begin,
|
||||
(size_t) bsp_section_rodata_size
|
||||
);
|
||||
|
||||
/* Copy .data section */
|
||||
bsp_start_memcpy_libc(
|
||||
(int *) bsp_section_data_begin,
|
||||
(const int *) bsp_section_data_load_begin,
|
||||
(size_t) bsp_section_data_size
|
||||
);
|
||||
|
||||
/* Copy .fast_text section */
|
||||
bsp_start_memcpy_libc(
|
||||
(int *) bsp_section_fast_text_begin,
|
||||
(const int *) bsp_section_fast_text_load_begin,
|
||||
(size_t) bsp_section_fast_text_size
|
||||
);
|
||||
|
||||
/* Copy .fast_data section */
|
||||
bsp_start_memcpy_libc(
|
||||
(int *) bsp_section_fast_data_begin,
|
||||
(const int *) bsp_section_fast_data_load_begin,
|
||||
(size_t) bsp_section_fast_data_size
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Copies the .data, .fast_text and .fast_data sections from the load to
|
||||
* the runtime area using the C library memcpy().
|
||||
*
|
||||
* Works only in case the .start, .text and .rodata sections reside in one
|
||||
* memory region.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION static inline void bsp_start_copy_sections_compact(void)
|
||||
{
|
||||
/* Copy .data section */
|
||||
bsp_start_memcpy_libc(
|
||||
bsp_section_data_begin,
|
||||
bsp_section_data_load_begin,
|
||||
(size_t) bsp_section_data_size
|
||||
);
|
||||
|
||||
/* Copy .fast_text section */
|
||||
bsp_start_memcpy_libc(
|
||||
bsp_section_fast_text_begin,
|
||||
bsp_section_fast_text_load_begin,
|
||||
(size_t) bsp_section_fast_text_size
|
||||
);
|
||||
|
||||
/* Copy .fast_data section */
|
||||
bsp_start_memcpy_libc(
|
||||
bsp_section_fast_data_begin,
|
||||
bsp_section_fast_data_load_begin,
|
||||
(size_t) bsp_section_fast_data_size
|
||||
);
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void bsp_start_clear_bss(void)
|
||||
{
|
||||
memset(bsp_section_bss_begin, 0, (size_t) bsp_section_bss_size);
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline void
|
||||
AArch64_start_set_vector_base(void)
|
||||
{
|
||||
__asm__ volatile (
|
||||
"msr VBAR_EL1, %[vtable]\n"
|
||||
: : [vtable] "r" (bsp_start_vector_table_begin)
|
||||
);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_SHARED_START_H */
|
||||
@@ -1,88 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup DevIRQGIC
|
||||
*
|
||||
* @brief This header file provides interfaces of the ARM Generic Interrupt
|
||||
* Controller (GIC) support specific to the AArch64 architecture.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
|
||||
#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
|
||||
|
||||
#include <rtems/score/cpu.h>
|
||||
#include <rtems/score/cpu_irq.h>
|
||||
|
||||
#include <bsp/irq-generic.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @addtogroup DevIRQGIC
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
static inline uint32_t arm_interrupt_enable_interrupts(void)
|
||||
{
|
||||
uint32_t status = _CPU_ISR_Get_level();
|
||||
/* Enable interrupts for nesting */
|
||||
_CPU_ISR_Set_level(0);
|
||||
return status;
|
||||
}
|
||||
|
||||
static inline void arm_interrupt_restore_interrupts(uint32_t status)
|
||||
{
|
||||
/* Restore interrupts to previous level */
|
||||
_CPU_ISR_Set_level(status);
|
||||
}
|
||||
|
||||
static inline void arm_interrupt_facility_set_exception_handler(void)
|
||||
{
|
||||
AArch64_set_exception_handler(
|
||||
AARCH64_EXCEPTION_SPx_IRQ,
|
||||
_AArch64_Exception_interrupt_no_nest
|
||||
);
|
||||
AArch64_set_exception_handler(
|
||||
AARCH64_EXCEPTION_SP0_IRQ,
|
||||
_AArch64_Exception_interrupt_nest
|
||||
);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */
|
||||
@@ -1,180 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Console Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
* Copyright (C) 2023 Utkarsh Verma
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/bspIo.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/console.h>
|
||||
#include <bsp/fatal.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <bspopts.h>
|
||||
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <rtems/termiosdevice.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#define CONSOLE_DEVICE_CONTEXT_NAME(port_no) uart##port_no##_context
|
||||
|
||||
#define CONSOLE_DEVICE_CONTEXT( \
|
||||
port_no, _file_name, regs_base, _size, clock_freq, irq_no, \
|
||||
context_type, ... \
|
||||
) \
|
||||
static context_type CONSOLE_DEVICE_CONTEXT_NAME(port_no) = { \
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("UART" #port_no), \
|
||||
.regs = (volatile arm_pl011_uart *) regs_base, \
|
||||
.clock = clock_freq, \
|
||||
.initial_baud = 115200, \
|
||||
.irq = irq_no, \
|
||||
};
|
||||
|
||||
#define CONSOLE_DEVICE( \
|
||||
port_no, file_name, _base, _size, _clock, _irq,_context_type, dev_handler, \
|
||||
write_char_func, rx_pin, tx_pin, gpio_func, ... \
|
||||
) \
|
||||
[CONSOLE_DEVICE_PORT2ENUM(port_no)] = { \
|
||||
.file = file_name, \
|
||||
.context = &CONSOLE_DEVICE_CONTEXT_NAME(port_no).base, \
|
||||
.gpio = {.rx = rx_pin, .tx = tx_pin, .function = gpio_func}, \
|
||||
.handler = dev_handler, \
|
||||
.write_char_polled = write_char_func, \
|
||||
},
|
||||
|
||||
typedef struct {
|
||||
const unsigned int rx;
|
||||
const unsigned int tx;
|
||||
const raspberrypi_gpio_function function;
|
||||
} raspberrypi_console_device_gpio_config;
|
||||
|
||||
typedef struct {
|
||||
const char* file;
|
||||
rtems_termios_device_context* context;
|
||||
const raspberrypi_console_device_gpio_config gpio;
|
||||
|
||||
const rtems_termios_device_handler* handler;
|
||||
void (*write_char_polled)(rtems_termios_device_context*, char);
|
||||
} raspberrypi_console_device;
|
||||
|
||||
/* Initialize all console device contexts */
|
||||
CONSOLE_DEVICES(CONSOLE_DEVICE_CONTEXT)
|
||||
|
||||
/* Initialize all device configurations */
|
||||
static const raspberrypi_console_device devices[CONSOLE_DEVICE_COUNT] = {
|
||||
CONSOLE_DEVICES(CONSOLE_DEVICE)
|
||||
};
|
||||
|
||||
static rtems_status_code console_device_init_gpio(
|
||||
const raspberrypi_console_device_gpio_config *gpio
|
||||
)
|
||||
{
|
||||
rtems_status_code status = raspberrypi_gpio_set_function(
|
||||
gpio->rx,
|
||||
gpio->function
|
||||
);
|
||||
if (status != RTEMS_SUCCESSFUL)
|
||||
return status;
|
||||
|
||||
status = raspberrypi_gpio_set_function(gpio->tx, gpio->function);
|
||||
if (status != RTEMS_SUCCESSFUL)
|
||||
return status;
|
||||
|
||||
status = raspberrypi_gpio_set_pull(gpio->rx, GPIO_PULL_NONE);
|
||||
if (status != RTEMS_SUCCESSFUL)
|
||||
return status;
|
||||
|
||||
status = raspberrypi_gpio_set_pull(gpio->tx, GPIO_PULL_NONE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void output_char(const char ch) {
|
||||
const raspberrypi_console_device* device = &devices[BSP_CONSOLE_PORT];
|
||||
device->write_char_polled(device->context, ch);
|
||||
}
|
||||
|
||||
static int poll_char(void) {
|
||||
const raspberrypi_console_device* device = &devices[BSP_CONSOLE_PORT];
|
||||
return device->handler->poll_read(device->context);
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_uart_init(
|
||||
raspberrypi_console_device_port uart_num
|
||||
)
|
||||
{
|
||||
const raspberrypi_console_device *device = &devices[uart_num];
|
||||
|
||||
rtems_status_code status = console_device_init_gpio(&device->gpio);
|
||||
if (status != RTEMS_SUCCESSFUL) {
|
||||
return status;
|
||||
}
|
||||
|
||||
status = rtems_termios_device_install(
|
||||
device->file, device->handler, NULL, device->context
|
||||
);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
rtems_device_driver console_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
(void) major;
|
||||
(void) minor;
|
||||
(void) arg;
|
||||
|
||||
const raspberrypi_console_device* device = &devices[BSP_CONSOLE_PORT];
|
||||
rtems_status_code status = raspberrypi_uart_init(BSP_CONSOLE_PORT);
|
||||
if (status != RTEMS_SUCCESSFUL) {
|
||||
bsp_fatal(BSP_FATAL_CONSOLE_INSTALL_0);
|
||||
}
|
||||
|
||||
rtems_termios_initialize();
|
||||
|
||||
if (link(device->file, CONSOLE_DEVICE_NAME) != 0) {
|
||||
bsp_fatal(BSP_FATAL_CONSOLE_INSTALL_1);
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = output_char;
|
||||
BSP_polling_getchar_function_type BSP_poll_char = poll_char;
|
||||
@@ -1,300 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief Raspberry Pi specific DMA definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/raspberrypi-dma.h>
|
||||
#define DMA4_AD_SHIFT( addr ) ( addr >> 5 )
|
||||
#define DMA4_AD_UNSHIFT( addr ) ( addr << 5 )
|
||||
#define ADDRESS_LOW( addr ) ( (uintptr_t) ( addr ) & 0xFFFFFFFF )
|
||||
#define ADDRESS_HIGH( addr ) ( ( (uintptr_t) ( addr ) >> 32 ) & 0xFF )
|
||||
#define BUS_ADDR( addr ) ( ( ( addr ) & ~0xC0000000 ) | 0xC0000000 )
|
||||
|
||||
typedef struct {
|
||||
uint32_t transfer_info; /**< Control register */
|
||||
uint32_t source_addr; /**< Source address register */
|
||||
uint32_t destination_addr; /**< Destination address register */
|
||||
uint32_t transfer_length; /**< Transfer length register */
|
||||
uint32_t mode_2d_stride; /**< Stride register */
|
||||
uint32_t next_cb; /**< Next control block address register */
|
||||
uint32_t reserved[ 2 ]; /**< Reserved */
|
||||
} rpi_dma_control_block;
|
||||
|
||||
typedef struct {
|
||||
uint32_t transfer_info; /**< Control register */
|
||||
uint32_t source_addr; /**< Source address register */
|
||||
uint32_t destination_addr; /**< Destination address register */
|
||||
uint32_t transfer_length; /**< Transfer length register */
|
||||
uint32_t reserved_bit; /**< Reserved */
|
||||
uint32_t next_cb; /**< Next control block address register */
|
||||
uint32_t reserved[ 2 ]; /**< Reserved */
|
||||
} rpi_dma_lite_control_block;
|
||||
|
||||
typedef struct {
|
||||
uint32_t transfer_info; /**< Control register */
|
||||
uint32_t source_addr; /**< Source address register */
|
||||
uint32_t source_info; /**< Source information */
|
||||
uint32_t destination_addr; /**< Destination address register */
|
||||
uint32_t destination_info; /**< Destination information */
|
||||
uint32_t transfer_length; /**< Transfer length register */
|
||||
uint32_t next_cb; /**< Next control block address register */
|
||||
uint32_t reserved; /**< Reserved */
|
||||
} rpi_dma4_control_block;
|
||||
|
||||
static const uint32_t dma_base_addresses[] = {
|
||||
BCM2711_DMA0_BASE,
|
||||
BCM2711_DMA1_BASE,
|
||||
BCM2711_DMA2_BASE,
|
||||
BCM2711_DMA3_BASE,
|
||||
BCM2711_DMA4_BASE,
|
||||
BCM2711_DMA5_BASE,
|
||||
BCM2711_DMA6_BASE,
|
||||
BCM2711_DMA7_BASE,
|
||||
BCM2711_DMA8_BASE,
|
||||
BCM2711_DMA9_BASE,
|
||||
BCM2711_DMA10_BASE,
|
||||
BCM2711_DMA11_BASE,
|
||||
BCM2711_DMA12_BASE,
|
||||
BCM2711_DMA13_BASE,
|
||||
BCM2711_DMA14_BASE
|
||||
};
|
||||
|
||||
static inline uint32_t get_base_address( rpi_dma_channel channel )
|
||||
{
|
||||
if ( channel >= 0 && channel <= DMA4_CHANNEL_14 ) {
|
||||
return dma_base_addresses[ channel ];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static rpi_dma_control_block *rpi_dma_init_cb(
|
||||
void *source_address,
|
||||
void *destination_address,
|
||||
uint32_t transfer_length
|
||||
)
|
||||
{
|
||||
rpi_dma_control_block *cb = (rpi_dma_control_block *)
|
||||
rtems_heap_allocate_aligned_with_boundary(
|
||||
sizeof( rpi_dma_control_block ),
|
||||
CPU_CACHE_LINE_BYTES,
|
||||
0
|
||||
);
|
||||
if ( cb == NULL ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cb->source_addr = BUS_ADDR( (uint32_t) (uintptr_t) source_address );
|
||||
cb->destination_addr = BUS_ADDR( (uint32_t) (uintptr_t) destination_address );
|
||||
cb->transfer_length = transfer_length;
|
||||
cb->transfer_info = ( TI_DEST_INC | TI_SRC_INC );
|
||||
cb->mode_2d_stride = 0;
|
||||
cb->next_cb = 0;
|
||||
cb->reserved[ 0 ] = 0;
|
||||
cb->reserved[ 1 ] = 0;
|
||||
|
||||
return cb;
|
||||
}
|
||||
|
||||
static rpi_dma_lite_control_block *rpi_dma_lite_init_cb(
|
||||
void *source_address,
|
||||
void *destination_address,
|
||||
uint32_t transfer_length
|
||||
)
|
||||
{
|
||||
rpi_dma_lite_control_block *cb = (rpi_dma_lite_control_block *)
|
||||
rtems_heap_allocate_aligned_with_boundary(
|
||||
sizeof( rpi_dma_control_block ),
|
||||
CPU_CACHE_LINE_BYTES,
|
||||
0
|
||||
);
|
||||
if ( cb == NULL ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cb->source_addr = BUS_ADDR( (uint32_t) (uintptr_t) source_address );
|
||||
cb->destination_addr = BUS_ADDR( (uint32_t) (uintptr_t) destination_address );
|
||||
cb->transfer_length = transfer_length;
|
||||
cb->transfer_info = ( TI_DEST_INC | TI_SRC_INC );
|
||||
cb->next_cb = 0;
|
||||
cb->reserved_bit = 0;
|
||||
cb->reserved[ 0 ] = 0;
|
||||
cb->reserved[ 1 ] = 0;
|
||||
|
||||
return cb;
|
||||
}
|
||||
|
||||
static rpi_dma4_control_block *rpi_dma4_init_cb(
|
||||
void *source_address,
|
||||
void *destination_address,
|
||||
uint32_t transfer_length
|
||||
)
|
||||
{
|
||||
rpi_dma4_control_block *cb = (rpi_dma4_control_block *)
|
||||
rtems_heap_allocate_aligned_with_boundary(
|
||||
sizeof( rpi_dma4_control_block ),
|
||||
CPU_CACHE_LINE_BYTES,
|
||||
0
|
||||
);
|
||||
if ( cb == NULL ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cb->source_addr = (uint32_t) ADDRESS_LOW( source_address );
|
||||
cb->source_info = SI_SRC_INC | ADDRESS_HIGH( source_address );
|
||||
cb->destination_addr = (uint32_t) ADDRESS_LOW( destination_address );
|
||||
cb->destination_info = DI_DEST_INC | ADDRESS_HIGH( destination_address );
|
||||
cb->transfer_length = transfer_length;
|
||||
cb->transfer_info = 0;
|
||||
cb->next_cb = 0;
|
||||
cb->reserved = 0;
|
||||
|
||||
return cb;
|
||||
}
|
||||
|
||||
static inline void rpi_dma_free_control_block(
|
||||
rpi_dma_channel channel,
|
||||
uint32_t base_address
|
||||
)
|
||||
{
|
||||
uint32_t cb_ad_reg = BCM2835_REG( base_address + CONBLK_AD_OFFSET );
|
||||
if ( cb_ad_reg == 0 ) {
|
||||
return;
|
||||
}
|
||||
|
||||
uintptr_t cb_addr;
|
||||
if ( channel >= DMA4_CHANNEL_11 && channel <= DMA4_CHANNEL_14 ) {
|
||||
cb_addr = DMA4_AD_UNSHIFT( cb_ad_reg );
|
||||
} else {
|
||||
cb_addr = (uintptr_t) cb_ad_reg;
|
||||
}
|
||||
|
||||
if ( cb_addr != 0 ) {
|
||||
void *cb = (void *) cb_addr;
|
||||
free( cb );
|
||||
BCM2835_REG( base_address + CONBLK_AD_OFFSET ) = 0;
|
||||
}
|
||||
}
|
||||
|
||||
rtems_status_code rpi_dma_start_transfer( rpi_dma_channel channel )
|
||||
{
|
||||
uint32_t base_address = get_base_address( channel );
|
||||
if ( !base_address ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
BCM2835_REG( base_address + CS_OFFSET ) = CS_WAIT_FOR_OUTSTANDING_WRITES |
|
||||
CS_PANIC_PRIORITY_SHIFT |
|
||||
CS_PRIORITY_SHIFT;
|
||||
BCM2835_REG( base_address + CS_OFFSET ) |= CS_ACTIVE;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_status_code rpi_dma_wait( rpi_dma_channel channel )
|
||||
{
|
||||
uint32_t base_address = get_base_address( channel );
|
||||
if ( !base_address ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
while (( BCM2835_REG( base_address + CS_OFFSET ) & CS_ACTIVE ));
|
||||
|
||||
rpi_dma_free_control_block( channel, base_address );
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_status_code rpi_dma_mem_to_mem_init(
|
||||
rpi_dma_channel channel,
|
||||
void *source_address,
|
||||
void *destination_address,
|
||||
uint32_t transfer_length
|
||||
)
|
||||
{
|
||||
uint32_t base_address = get_base_address( channel );
|
||||
if ( !base_address ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
if ( ( (uintptr_t) source_address % CPU_CACHE_LINE_BYTES ) != 0 ||
|
||||
( (uintptr_t) destination_address % CPU_CACHE_LINE_BYTES ) != 0 ) {
|
||||
return RTEMS_INVALID_ADDRESS;
|
||||
}
|
||||
|
||||
void *control_block = NULL;
|
||||
size_t cb_size = 0;
|
||||
|
||||
if ( channel < DMA_LITE_CHANNEL_7 ) {
|
||||
control_block = rpi_dma_init_cb(
|
||||
source_address,
|
||||
destination_address,
|
||||
transfer_length
|
||||
);
|
||||
cb_size = sizeof( rpi_dma_control_block );
|
||||
} else if ( channel > DMA_CHANNEL_6 && channel < DMA4_CHANNEL_11 ) {
|
||||
control_block = rpi_dma_lite_init_cb(
|
||||
source_address,
|
||||
destination_address,
|
||||
transfer_length
|
||||
);
|
||||
cb_size = sizeof( rpi_dma_lite_control_block );
|
||||
} else if ( channel > DMA_LITE_CHANNEL_10 && channel <= DMA4_CHANNEL_14 ) {
|
||||
control_block = rpi_dma4_init_cb(
|
||||
source_address,
|
||||
destination_address,
|
||||
transfer_length
|
||||
);
|
||||
cb_size = sizeof( rpi_dma4_control_block );
|
||||
} else {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
if ( control_block == NULL ) {
|
||||
return RTEMS_NO_MEMORY;
|
||||
}
|
||||
|
||||
BCM2835_REG( base_address + CS_OFFSET ) = CS_RESET | CS_ABORT;
|
||||
rtems_cache_flush_multiple_data_lines( control_block, cb_size );
|
||||
rtems_cache_flush_multiple_data_lines( source_address, transfer_length );
|
||||
rtems_cache_invalidate_multiple_data_lines(
|
||||
destination_address,
|
||||
transfer_length
|
||||
);
|
||||
|
||||
if ( ( channel >= DMA4_CHANNEL_11 ) && ( channel <= DMA4_CHANNEL_14 ) ) {
|
||||
uint32_t cb_addr = (uint32_t) (uintptr_t) control_block;
|
||||
uint32_t dma4_cb_addr = DMA4_AD_SHIFT( cb_addr );
|
||||
BCM2835_REG( base_address + CONBLK_AD_OFFSET ) = dma4_cb_addr;
|
||||
} else {
|
||||
BCM2835_REG( base_address + CONBLK_AD_OFFSET ) = (uint32_t) (uintptr_t
|
||||
) control_block;
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,79 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief This file provides the base Raspberrypi4 device tree
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
amba@7c000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x7c000000 0x00 0xfc000000 0x3800000>, <0x40000000 0x00 0xff800000 0x800000>;
|
||||
|
||||
interrupt-controller@40041000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <2>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x40041000 0x1000>, <0x40042000 0x2000>, <0x40044000 0x2000>, <0x40046000 0x2000>;
|
||||
interrupt-controller;
|
||||
phandle = <1>;
|
||||
};
|
||||
|
||||
ethernet@7d580000 {
|
||||
phy-mode = "rgmii-rxid";
|
||||
phy-handle = <&phy0>;
|
||||
compatible = "brcm,bcm2711-genet-v5";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x7d580000 0x10000>;
|
||||
interrupt-parent = <1>;
|
||||
interrupts = <0x0 0x9d 0x4> , <0x0 0x9e 0x4>;
|
||||
|
||||
mdio@e14 {
|
||||
compatible = "brcm,genet-mdio-v5";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xe14 0x8>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,50 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief This source file contains the implementatin of bsp_fdt_get().
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/fdt.h>
|
||||
|
||||
const void *bsp_fdt_get(void)
|
||||
{
|
||||
return bcm2711_rpi_4_b_dtb;
|
||||
}
|
||||
|
||||
uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
|
||||
{
|
||||
if (icells != 3) {
|
||||
return 0;
|
||||
}
|
||||
return (intr[0] == 0 ? 32 : 16) + intr[1];
|
||||
}
|
||||
@@ -1,88 +0,0 @@
|
||||
/*
|
||||
* Declarations for C structure representing binary file bcm2711-rpi-4-b.dtb
|
||||
*
|
||||
* WARNING: Automatically generated -- do not edit!
|
||||
*/
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
const unsigned char bcm2711_rpi_4_b_dtb[] = {
|
||||
0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x03, 0x8b, 0x00, 0x00, 0x00, 0x38,
|
||||
0x00, 0x00, 0x02, 0xfc, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
|
||||
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f,
|
||||
0x00, 0x00, 0x02, 0xc4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x01, 0x61, 0x6d, 0x62, 0x61, 0x40, 0x37, 0x63, 0x30,
|
||||
0x30, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1b, 0x73, 0x69, 0x6d, 0x70,
|
||||
0x6c, 0x65, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20,
|
||||
0x00, 0x00, 0x00, 0x26, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xfc, 0x00, 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0xff, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x01, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70,
|
||||
0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72,
|
||||
0x40, 0x34, 0x30, 0x30, 0x34, 0x31, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1b,
|
||||
0x61, 0x72, 0x6d, 0x2c, 0x67, 0x69, 0x63, 0x2d, 0x34, 0x30, 0x30, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x3e, 0x40, 0x04, 0x10, 0x00,
|
||||
0x00, 0x00, 0x10, 0x00, 0x40, 0x04, 0x20, 0x00, 0x00, 0x00, 0x20, 0x00,
|
||||
0x40, 0x04, 0x40, 0x00, 0x00, 0x00, 0x20, 0x00, 0x40, 0x04, 0x60, 0x00,
|
||||
0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
|
||||
0x40, 0x37, 0x64, 0x35, 0x38, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x5f,
|
||||
0x72, 0x67, 0x6d, 0x69, 0x69, 0x2d, 0x72, 0x78, 0x69, 0x64, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x68,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x16,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x62, 0x72, 0x63, 0x6d, 0x2c, 0x62, 0x63, 0x6d,
|
||||
0x32, 0x37, 0x31, 0x31, 0x2d, 0x67, 0x65, 0x6e, 0x65, 0x74, 0x2d, 0x76,
|
||||
0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3e,
|
||||
0x7d, 0x58, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x84,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9d, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9e, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x01, 0x6d, 0x64, 0x69, 0x6f, 0x40, 0x65, 0x31, 0x34,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x62, 0x72, 0x63, 0x6d, 0x2c, 0x67, 0x65, 0x6e,
|
||||
0x65, 0x74, 0x2d, 0x6d, 0x64, 0x69, 0x6f, 0x2d, 0x76, 0x35, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x0e, 0x14,
|
||||
0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x2d, 0x70, 0x68, 0x79, 0x40, 0x31, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3e,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64,
|
||||
0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23,
|
||||
0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63,
|
||||
0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x72, 0x61,
|
||||
0x6e, 0x67, 0x65, 0x73, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
|
||||
0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,
|
||||
0x67, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
|
||||
0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70,
|
||||
0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x6d,
|
||||
0x6f, 0x64, 0x65, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x68, 0x61, 0x6e, 0x64,
|
||||
0x6c, 0x65, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74,
|
||||
0x2d, 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x69, 0x6e, 0x74, 0x65,
|
||||
0x72, 0x72, 0x75, 0x70, 0x74, 0x73, 0x00,
|
||||
};
|
||||
|
||||
const size_t bcm2711_rpi_4_b_dtb_size = sizeof(bcm2711_rpi_4_b_dtb);
|
||||
@@ -1,110 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief GPIO Driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 Utkarsh Verma
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/rtems/status.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
#define BSP_GPIO_BASE BCM2711_GPIO_BASE
|
||||
#define BSP_GPIO_SIZE BCM2711_GPIO_SIZE
|
||||
#define BSP_GPIO_PIN_COUNT BCM2711_GPIO_PIN_COUNT
|
||||
|
||||
#define GPFSEL0 BCM2835_REG(BSP_GPIO_BASE + 0x00)
|
||||
#define GPSET0 BCM2835_REG(BSP_GPIO_BASE + 0x1c)
|
||||
#define GPCLR0 BCM2835_REG(BSP_GPIO_BASE + 0x28)
|
||||
#define GPIO_PUP_PDN_CTRL_REG0 BCM2835_REG(BSP_GPIO_BASE + 0xe4)
|
||||
#define FSELn_SIZE 3
|
||||
#define CLRn_SIZE 1
|
||||
#define SETn_SIZE 1
|
||||
#define REG_SET 1
|
||||
|
||||
static rtems_status_code raspberrypi_gpio_set_reg(
|
||||
volatile uint32_t *base_reg,
|
||||
const unsigned int pin,
|
||||
const uint32_t value,
|
||||
const unsigned int field_size
|
||||
)
|
||||
{
|
||||
unsigned int field_mask, n_fields, shift, tmp;
|
||||
volatile uint32_t *reg;
|
||||
|
||||
if (pin > BSP_GPIO_PIN_COUNT)
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
|
||||
field_mask = (1 << field_size) - 1;
|
||||
if (value > field_mask)
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
|
||||
/* GPIO registers are uniformly subdivided */
|
||||
n_fields = sizeof(uint32_t) * 8 / field_size;
|
||||
|
||||
/* Registers are sequentially mapped for each `n_field` GPIOs */
|
||||
reg = base_reg + pin / n_fields;
|
||||
shift = (pin % n_fields) * field_size;
|
||||
|
||||
tmp = *reg;
|
||||
tmp &= ~(field_mask << shift); /* Clear the field */
|
||||
tmp |= value << shift; /* Set value to the field */
|
||||
*reg = tmp;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_gpio_set_function(
|
||||
const unsigned int pin,
|
||||
const raspberrypi_gpio_function value
|
||||
)
|
||||
{
|
||||
return raspberrypi_gpio_set_reg(&GPFSEL0, pin, value, FSELn_SIZE);
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_gpio_clear_pin(const unsigned int pin)
|
||||
{
|
||||
return raspberrypi_gpio_set_reg(&GPCLR0, pin, REG_SET, CLRn_SIZE);
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_gpio_set_pin(const unsigned int pin)
|
||||
{
|
||||
return raspberrypi_gpio_set_reg(&GPSET0, pin, REG_SET, SETn_SIZE);
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_gpio_set_pull(
|
||||
const unsigned int pin,
|
||||
const raspberrypi_gpio_pull value
|
||||
)
|
||||
{
|
||||
return raspberrypi_gpio_set_reg(&GPIO_PUP_PDN_CTRL_REG0, pin, value, 2);
|
||||
}
|
||||
@@ -1,397 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup raspberrypi_4_i2c
|
||||
*
|
||||
* @brief I2C Driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/raspberrypi-i2c.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <dev/i2c/i2c.h>
|
||||
|
||||
#define C_REG( bus ) BCM2835_REG( ( bus )->base_address + BCM2711_I2C_CONTROL )
|
||||
#define C_I2CEN ( 1 << 15 )
|
||||
#define C_INTR ( 1 << 10 )
|
||||
#define C_INTT ( 1 << 9 )
|
||||
#define C_INTD ( 1 << 8 )
|
||||
#define C_ST ( 1 << 7 )
|
||||
#define C_CLEAR ( 1 << 5 )
|
||||
#define C_READ ( 1 << 0 )
|
||||
|
||||
#define BSC_CORE_CLK_HZ 150000000
|
||||
|
||||
#define S_REG( bus ) BCM2835_REG( ( bus )->base_address + BCM2711_I2C_STATUS )
|
||||
#define S_CLKT ( 1 << 9 )
|
||||
#define S_ERR ( 1 << 8 )
|
||||
#define S_RXF ( 1 << 7 )
|
||||
#define S_TXE ( 1 << 6 )
|
||||
#define S_RXD ( 1 << 5 )
|
||||
#define S_TXD ( 1 << 4 )
|
||||
#define S_RXR ( 1 << 3 )
|
||||
#define S_TXW ( 1 << 2 )
|
||||
#define S_DONE ( 1 << 1 )
|
||||
#define S_TA ( 1 << 0 )
|
||||
#define S_ERROR ( S_CLKT | S_ERR | S_DONE )
|
||||
|
||||
typedef struct {
|
||||
i2c_bus base;
|
||||
rtems_binary_semaphore sem;
|
||||
uint32_t input_clock;
|
||||
uintptr_t base_address;
|
||||
raspberrypi_bsc_masters device;
|
||||
uint32_t remaining_bytes;
|
||||
uint32_t remaining_transfers;
|
||||
uint8_t *current_buffer;
|
||||
uint32_t current_buffer_size;
|
||||
bool read_transfer;
|
||||
} raspberrypi_i2c_bus;
|
||||
|
||||
static int rpi_i2c_bus_transfer( raspberrypi_i2c_bus *bus )
|
||||
{
|
||||
while ( bus->remaining_bytes > 0 ) {
|
||||
if ( bus->read_transfer ) {
|
||||
while ( ( S_REG( bus ) & ( S_RXD | S_CLKT ) ) == 0 ) {
|
||||
}
|
||||
if ( S_REG( bus ) & S_CLKT ) {
|
||||
return -EIO;
|
||||
}
|
||||
*bus->current_buffer = BCM2835_REG(
|
||||
bus->base_address + BCM2711_I2C_FIFO
|
||||
) &
|
||||
BCM2711_I2C_FIFO_MASK;
|
||||
|
||||
++bus->current_buffer;
|
||||
if ( ( S_REG( bus ) & S_ERR ) || ( S_REG( bus ) & S_CLKT ) ) {
|
||||
return -EIO;
|
||||
}
|
||||
} else {
|
||||
#ifdef BSP_I2C_USE_INTERRUPTS
|
||||
C_REG( bus ) |= C_INTT;
|
||||
|
||||
if ( rtems_binary_semaphore_wait_timed_ticks(
|
||||
&bus->sem,
|
||||
bus->base.timeout
|
||||
) != RTEMS_SUCCESSFUL ) {
|
||||
rtems_binary_semaphore_try_wait( &bus->sem );
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
#else
|
||||
while ( ( S_REG( bus ) & ( S_TXW | S_CLKT ) ) == 0 ) {
|
||||
}
|
||||
if ( S_REG( bus ) & S_CLKT ) {
|
||||
return -EIO;
|
||||
}
|
||||
#endif
|
||||
BCM2835_REG(
|
||||
bus->base_address + BCM2711_I2C_FIFO
|
||||
) = *bus->current_buffer;
|
||||
|
||||
++bus->current_buffer;
|
||||
if ( ( S_REG( bus ) & S_ERR ) || ( S_REG( bus ) & S_CLKT ) ) {
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
--bus->remaining_bytes;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rpi_i2c_destroy( i2c_bus *base )
|
||||
{
|
||||
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
|
||||
|
||||
i2c_bus_destroy_and_free( &bus->base );
|
||||
}
|
||||
|
||||
static int rpi_i2c_set_clock( i2c_bus *base, unsigned long clock )
|
||||
{
|
||||
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
|
||||
uint32_t clock_rate;
|
||||
uint16_t divider;
|
||||
|
||||
divider = BSC_CORE_CLK_HZ / clock;
|
||||
|
||||
clock_rate = BSC_CORE_CLK_HZ / divider;
|
||||
|
||||
while ( clock_rate > clock ) {
|
||||
++divider;
|
||||
clock_rate = BSC_CORE_CLK_HZ / divider;
|
||||
}
|
||||
|
||||
BCM2835_REG( bus->base_address + BCM2711_I2C_DIV ) = divider;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rpi_i2c_setup_and_transfer( raspberrypi_i2c_bus *bus )
|
||||
{
|
||||
int rv;
|
||||
while ( bus->remaining_transfers > 0 ) {
|
||||
bus->remaining_bytes = bus->remaining_transfers > 1 ?
|
||||
BCM2711_I2C_DLEN_MASK :
|
||||
( bus->current_buffer_size & BCM2711_I2C_DLEN_MASK
|
||||
);
|
||||
BCM2835_REG( bus->base_address + BCM2711_I2C_DLEN ) = bus->remaining_bytes;
|
||||
/* Clear the error bits before starting new transfer */
|
||||
S_REG( bus ) = S_ERROR;
|
||||
C_REG( bus ) |= C_ST;
|
||||
|
||||
rv = rpi_i2c_bus_transfer( bus );
|
||||
|
||||
if ( rv < 0 ) {
|
||||
return rv;
|
||||
}
|
||||
|
||||
#ifdef BSP_I2C_USE_INTERRUPTS
|
||||
C_REG( bus ) |= C_INTD;
|
||||
if ( rtems_binary_semaphore_wait_timed_ticks(
|
||||
&bus->sem,
|
||||
bus->base.timeout
|
||||
) != 0 ) {
|
||||
rtems_binary_semaphore_try_wait( &bus->sem );
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
#else
|
||||
while ( ( S_REG( bus ) & ( S_DONE | S_CLKT ) ) == 0 ) {
|
||||
}
|
||||
if ( S_REG( bus ) & S_CLKT ) {
|
||||
return -EIO;
|
||||
}
|
||||
#endif
|
||||
|
||||
--bus->remaining_transfers;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef BSP_I2C_USE_INTERRUPTS
|
||||
static void i2c_handler( void *args )
|
||||
{
|
||||
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) args;
|
||||
if ( C_REG( bus ) & C_INTT ) {
|
||||
C_REG( bus ) &= ~C_INTT;
|
||||
} else if ( C_REG( bus ) & C_INTD ) {
|
||||
C_REG( bus ) &= ~C_INTD;
|
||||
}
|
||||
rtems_binary_semaphore_post( &bus->sem );
|
||||
}
|
||||
#endif
|
||||
|
||||
static int rpi_i2c_transfer( i2c_bus *base, i2c_msg *msgs, uint32_t msg_count )
|
||||
{
|
||||
raspberrypi_i2c_bus *bus = (raspberrypi_i2c_bus *) base;
|
||||
int rv = 0;
|
||||
uint32_t i;
|
||||
uint8_t msbs;
|
||||
int supported_flags = I2C_M_TEN | I2C_M_RD;
|
||||
|
||||
for ( i = 0; i < msg_count; i++ ) {
|
||||
if ( msgs[ i ].len == 0 || msgs[ i ].buf == NULL ) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ( ( msgs[ i ].flags & ~supported_flags ) != 0 ) {
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
for ( i = 0; i < msg_count; i++ ) {
|
||||
bus->current_buffer = msgs[ i ].buf;
|
||||
bus->current_buffer_size = msgs[ i ].len;
|
||||
bus->remaining_transfers = ( bus->current_buffer_size +
|
||||
( BCM2711_I2C_DLEN_MASK - 1 ) ) /
|
||||
BCM2711_I2C_DLEN_MASK;
|
||||
|
||||
/* 10-bit slave address */
|
||||
if ( msgs[ i ].flags & I2C_M_TEN ) {
|
||||
/* Add the 8 lsbs of the 10-bit slave address to the fifo register */
|
||||
BCM2835_REG(
|
||||
bus->base_address + BCM2711_I2C_FIFO
|
||||
) = msgs[ i ].addr & BCM2711_I2C_FIFO_MASK;
|
||||
|
||||
msbs = msgs[ i ].addr >> 8;
|
||||
BCM2835_REG(
|
||||
bus->base_address + BCM2711_I2C_SLAVE_ADDRESS
|
||||
) = BCM2711_10_BIT_ADDR_MASK | msbs;
|
||||
|
||||
} else {
|
||||
BCM2835_REG(
|
||||
bus->base_address + BCM2711_I2C_SLAVE_ADDRESS
|
||||
) = msgs[ i ].addr;
|
||||
}
|
||||
|
||||
if ( msgs[ i ].flags & I2C_M_RD ) {
|
||||
C_REG( bus ) |= C_CLEAR | C_READ;
|
||||
bus->read_transfer = true;
|
||||
} else {
|
||||
C_REG( bus ) |= C_CLEAR;
|
||||
C_REG( bus ) &= ~C_READ;
|
||||
bus->read_transfer = false;
|
||||
}
|
||||
/* Disable clock stretch timeout */
|
||||
BCM2835_REG( bus->base_address + BCM2711_I2C_CLKT ) = 0;
|
||||
|
||||
rv = rpi_i2c_setup_and_transfer( bus );
|
||||
if ( rv < 0 ) {
|
||||
return rv;
|
||||
}
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
static rtems_status_code rpi_i2c_gpio_init(
|
||||
raspberrypi_bsc_masters device,
|
||||
raspberrypi_i2c_bus *bus
|
||||
)
|
||||
{
|
||||
switch ( device ) {
|
||||
case raspberrypi_bscm0:
|
||||
raspberrypi_gpio_set_function( 0, GPIO_AF0 );
|
||||
raspberrypi_gpio_set_function( 1, GPIO_AF0 );
|
||||
bus->base_address = BCM2711_I2C0_BASE;
|
||||
break;
|
||||
case raspberrypi_bscm1:
|
||||
raspberrypi_gpio_set_function( 2, GPIO_AF0 );
|
||||
raspberrypi_gpio_set_function( 3, GPIO_AF0 );
|
||||
bus->base_address = BCM2711_I2C1_BASE;
|
||||
break;
|
||||
case raspberrypi_bscm3:
|
||||
raspberrypi_gpio_set_function( 4, GPIO_AF5 );
|
||||
raspberrypi_gpio_set_function( 5, GPIO_AF5 );
|
||||
bus->base_address = BCM2711_I2C3_BASE;
|
||||
break;
|
||||
case raspberrypi_bscm4:
|
||||
raspberrypi_gpio_set_function( 6, GPIO_AF5 );
|
||||
raspberrypi_gpio_set_function( 7, GPIO_AF5 );
|
||||
bus->base_address = BCM2711_I2C4_BASE;
|
||||
break;
|
||||
case raspberrypi_bscm5:
|
||||
raspberrypi_gpio_set_function( 10, GPIO_AF5 );
|
||||
raspberrypi_gpio_set_function( 11, GPIO_AF5 );
|
||||
bus->base_address = BCM2711_I2C5_BASE;
|
||||
break;
|
||||
case raspberrypi_bscm6:
|
||||
raspberrypi_gpio_set_function( 22, GPIO_AF5 );
|
||||
raspberrypi_gpio_set_function( 23, GPIO_AF5 );
|
||||
bus->base_address = BCM2711_I2C6_BASE;
|
||||
break;
|
||||
default:
|
||||
return RTEMS_INVALID_ADDRESS;
|
||||
}
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static char *rpi_select_bus( raspberrypi_bsc_masters device )
|
||||
{
|
||||
switch ( device ) {
|
||||
case raspberrypi_bscm0:
|
||||
return "/dev/i2c-0";
|
||||
case raspberrypi_bscm1:
|
||||
return "/dev/i2c-1";
|
||||
case raspberrypi_bscm3:
|
||||
return "/dev/i2c-3";
|
||||
case raspberrypi_bscm4:
|
||||
return "/dev/i2c-4";
|
||||
case raspberrypi_bscm5:
|
||||
return "/dev/i2c-5";
|
||||
case raspberrypi_bscm6:
|
||||
return "/dev/i2c-6";
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
|
||||
rtems_status_code rpi_i2c_init(
|
||||
raspberrypi_bsc_masters device,
|
||||
uint32_t bus_clock
|
||||
)
|
||||
{
|
||||
raspberrypi_i2c_bus *bus;
|
||||
rtems_status_code sc;
|
||||
const char *bus_path;
|
||||
|
||||
if ( device != raspberrypi_bscm0 && device != raspberrypi_bscm1 &&
|
||||
device != raspberrypi_bscm3 && device != raspberrypi_bscm4 &&
|
||||
device != raspberrypi_bscm5 && device != raspberrypi_bscm6 ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
bus_path = rpi_select_bus( device );
|
||||
if ( bus_path == NULL ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
bus = (raspberrypi_i2c_bus *) i2c_bus_alloc_and_init( sizeof( *bus ) );
|
||||
if ( bus == NULL ) {
|
||||
return RTEMS_NO_MEMORY;
|
||||
}
|
||||
|
||||
sc = rpi_i2c_gpio_init( device, bus );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
i2c_bus_destroy_and_free( &bus->base );
|
||||
return sc;
|
||||
}
|
||||
|
||||
/* Enable I2C */
|
||||
C_REG( bus ) = C_CLEAR;
|
||||
C_REG( bus ) = C_I2CEN;
|
||||
|
||||
#ifdef BSP_I2C_USE_INTERRUPTS
|
||||
sc = rtems_interrupt_handler_install(
|
||||
BCM2711_IRQ_I2C,
|
||||
"I2C",
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
(rtems_interrupt_handler) i2c_handler,
|
||||
bus
|
||||
);
|
||||
rtems_binary_semaphore_init( &bus->sem, "RPII2C" );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return -EIO;
|
||||
}
|
||||
#endif
|
||||
|
||||
sc = rpi_i2c_set_clock( &bus->base, bus_clock );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
i2c_bus_destroy_and_free( &bus->base );
|
||||
return sc;
|
||||
}
|
||||
|
||||
bus->base.transfer = rpi_i2c_transfer;
|
||||
bus->base.set_clock = rpi_i2c_set_clock;
|
||||
bus->base.destroy = rpi_i2c_destroy;
|
||||
bus->base.functionality = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
|
||||
|
||||
return i2c_bus_register( &bus->base, bus_path );
|
||||
}
|
||||
@@ -1,78 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief Core BSP definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
/*Raspberry pi MMU initialization */
|
||||
BSP_START_TEXT_SECTION void raspberrypi_4_setup_mmu_and_cache(void);
|
||||
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_FDT_IS_SUPPORTED
|
||||
extern const unsigned char bcm2711_rpi_4_b_dtb[];
|
||||
extern const size_t bcm2711_rpi_4_b_dtb_size;
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0xFF842000
|
||||
#define BSP_ARM_GIC_DIST_BASE 0xFF841000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H */
|
||||
@@ -1,79 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Console Configuration
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 Utkarsh Verma
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_CONSOLE_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_BSP_CONSOLE_H
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <bsp/raspberrypi-uart.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define CONSOLE_DEVICES RASPBERRYPI_CONSOLE_DEVICES
|
||||
|
||||
#define CONSOLE_DEVICE_PORT2ENUM(port_no) UART##port_no
|
||||
#define CONSOLE_DEVICE_ENUM(port_no, ...) CONSOLE_DEVICE_PORT2ENUM(port_no),
|
||||
|
||||
typedef enum {
|
||||
CONSOLE_DEVICES(CONSOLE_DEVICE_ENUM)
|
||||
CONSOLE_DEVICE_COUNT,
|
||||
} raspberrypi_console_device_port;
|
||||
|
||||
/**
|
||||
* @brief Initialize gpio of UART and install UART to the dev directory.
|
||||
*
|
||||
* @param uart_num The optional devices are UART0, UART2, UART3, UART4, UART5.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL Successful operation.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
* @retval RTEMS_NO_MEMORY Not enough memory to create a device node.
|
||||
* @retval RTEMS_UNSATISFIED Creation of the device file failed.
|
||||
* @retval RTEMS_INCORRECT_STATE Termios is not initialized.
|
||||
*/
|
||||
rtems_status_code raspberrypi_uart_init(
|
||||
raspberrypi_console_device_port uart_num
|
||||
);
|
||||
|
||||
#undef CONSOLE_DEVICE_ENUM
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_BSP_CONSOLE_H */
|
||||
@@ -1,121 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup raspberrypi_interrupt
|
||||
*
|
||||
* @brief Interrupt definitions.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Copyright (c) 2013 Alan Cudmore
|
||||
* Copyright (c) 2022 Mohd Noor Aman
|
||||
* Copyright (c) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H
|
||||
#define LIBBSP_ARM_RASPBERRYPI_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup raspberrypi_interrupt Interrupt Support
|
||||
*
|
||||
* @ingroup RTEMSBSPsARMRaspberryPi
|
||||
*
|
||||
* @brief Interrupt support.
|
||||
*/
|
||||
|
||||
#define BCM2835_INTC_TOTAL_IRQ 216
|
||||
|
||||
#define BCM2835_IRQ_SET1_MIN 0
|
||||
#define BCM2835_IRQ_SET2_MIN 32
|
||||
|
||||
#define BCM2711_IRQ_VC_PERIPHERAL_BASE 96
|
||||
|
||||
/* Interrupt Vectors: System Timer */
|
||||
#define BCM2835_IRQ_ID_GPU_TIMER_M0 (BCM2711_IRQ_VC_PERIPHERAL_BASE + 0)
|
||||
#define BCM2835_IRQ_ID_GPU_TIMER_M1 (BCM2711_IRQ_VC_PERIPHERAL_BASE + 1)
|
||||
#define BCM2835_IRQ_ID_GPU_TIMER_M2 (BCM2711_IRQ_VC_PERIPHERAL_BASE + 2)
|
||||
#define BCM2835_IRQ_ID_GPU_TIMER_M3 (BCM2711_IRQ_VC_PERIPHERAL_BASE + 3)
|
||||
|
||||
/* Interrupt Vectors: SPI */
|
||||
#define BCM2711_IRQ_SPI (BCM2711_IRQ_VC_PERIPHERAL_BASE + 54)
|
||||
|
||||
/* Interrupt Vectors: I2C */
|
||||
#define BCM2711_IRQ_I2C ( BCM2711_IRQ_VC_PERIPHERAL_BASE + 53 )
|
||||
|
||||
/* Interrupt Vectors: Videocore */
|
||||
#define BCM2711_IRQ_VC_PERIPHERAL_BASE 96
|
||||
#define BCM2711_IRQ_AUX (BCM2711_IRQ_VC_PERIPHERAL_BASE + 29)
|
||||
#define BCM2711_IRQ_PL011_UART (BCM2711_IRQ_VC_PERIPHERAL_BASE + 57)
|
||||
|
||||
#define BCM2835_IRQ_ID_USB 9
|
||||
#define BCM2835_IRQ_ID_AUX 29
|
||||
#define BCM2835_IRQ_ID_SPI_SLAVE 43
|
||||
#define BCM2835_IRQ_ID_PWA0 45
|
||||
#define BCM2835_IRQ_ID_PWA1 46
|
||||
#define BCM2835_IRQ_ID_SMI 48
|
||||
#define BCM2835_IRQ_ID_GPIO_0 49
|
||||
#define BCM2835_IRQ_ID_GPIO_1 50
|
||||
#define BCM2835_IRQ_ID_GPIO_2 51
|
||||
#define BCM2835_IRQ_ID_GPIO_3 52
|
||||
#define BCM2835_IRQ_ID_I2C 53
|
||||
#define BCM2835_IRQ_ID_SPI 54
|
||||
#define BCM2835_IRQ_ID_PCM 55
|
||||
#define BCM2835_IRQ_ID_UART 57
|
||||
#define BCM2835_IRQ_ID_SD 62
|
||||
|
||||
#define BCM2835_IRQ_ID_BASIC_BASE_ID 64
|
||||
#define BCM2835_IRQ_ID_TIMER_0 64
|
||||
#define BCM2835_IRQ_ID_MAILBOX_0 65
|
||||
#define BCM2835_IRQ_ID_DOORBELL_0 66
|
||||
#define BCM2835_IRQ_ID_DOORBELL_1 67
|
||||
#define BCM2835_IRQ_ID_GPU0_HALTED 68
|
||||
#define BCM2835_IRQ_ID_GPU1_HALTED 69
|
||||
#define BCM2835_IRQ_ID_ILL_ACCESS_1 70
|
||||
#define BCM2835_IRQ_ID_ILL_ACCESS_0 71
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define BSP_VPL011_SPI 32
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT BCM2835_INTC_TOTAL_IRQ
|
||||
#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
|
||||
|
||||
#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
|
||||
@@ -1,133 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief Raspberry Pi specific DMA definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_DMA_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_DMA_H
|
||||
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <rtems/malloc.h>
|
||||
#include <rtems/rtems/cache.h>
|
||||
#include <rtems/score/basedefs.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/**
|
||||
* @brief DMA channel identifiers for BCM2711 (0–6 full, 7–10 lite, 11–14 DMA4).
|
||||
*/
|
||||
typedef enum {
|
||||
DMA_CHANNEL_0,
|
||||
DMA_CHANNEL_1,
|
||||
DMA_CHANNEL_2,
|
||||
DMA_CHANNEL_3,
|
||||
DMA_CHANNEL_4,
|
||||
DMA_CHANNEL_5,
|
||||
DMA_CHANNEL_6,
|
||||
DMA_LITE_CHANNEL_7,
|
||||
DMA_LITE_CHANNEL_8,
|
||||
DMA_LITE_CHANNEL_9,
|
||||
DMA_LITE_CHANNEL_10,
|
||||
DMA4_CHANNEL_11,
|
||||
DMA4_CHANNEL_12,
|
||||
DMA4_CHANNEL_13,
|
||||
DMA4_CHANNEL_14,
|
||||
} rpi_dma_channel;
|
||||
/**
|
||||
* @brief Start a previously initialized DMA transfer on @a channel.
|
||||
*
|
||||
* Expects the channel's CONBLK_AD to point to a valid
|
||||
* control block. Sets ACTIVE and required priorities.
|
||||
*
|
||||
* @param channel DMA channel to start.
|
||||
* @retval RTEMS_SUCCESSFUL on success.
|
||||
* @retval RTEMS_INVALID_NUMBER if @a channel is invalid.
|
||||
*/
|
||||
rtems_status_code rpi_dma_start_transfer( rpi_dma_channel channel );
|
||||
|
||||
/**
|
||||
* @brief Block until the current DMA transfer on @a channel completes.
|
||||
*
|
||||
* Busy-waits for ACTIVE to clear and frees the control block previously
|
||||
* programmed into CONBLK_AD (including DMA4 address unshifting). Does **not**
|
||||
* invalidate/flush user buffers beyond setup done by the init helpers.
|
||||
*
|
||||
* @param channel DMA channel to wait on.
|
||||
* @retval RTEMS_SUCCESSFUL on success.
|
||||
* @retval RTEMS_INVALID_NUMBER if @a channel is invalid.
|
||||
* @retval RTEMS_UNSATISFIED if the channel reports an error.
|
||||
*/
|
||||
|
||||
rtems_status_code rpi_dma_wait( rpi_dma_channel channel );
|
||||
|
||||
/**
|
||||
* @brief Initialize a memcpy-style DMA transfer from @a source_address to
|
||||
* @a destination_address of @a transfer_length bytes on @a channel.
|
||||
*
|
||||
* Allocates and prepares the channel-specific control block, performs required
|
||||
* cache maintenance (flush control block and source; invalidate destination),
|
||||
* issues CS reset/abort, and writes CONBLK_AD (with DMA4 address packing via
|
||||
* DMA4_AD_SHIFT). This function does **not** start the transfer; call
|
||||
* ::rpi_dma_start_transfer() and then ::rpi_dma_wait().
|
||||
*
|
||||
* @param channel DMA channel to use (0–6 noarmal DMA, 7–10 lite,
|
||||
* 11–14 DMA4).
|
||||
* @param source_address Source buffer (must be CPU_CACHE_LINE_BYTES
|
||||
* aligned).
|
||||
* @param destination_address Destination buffer (must be CPU_CACHE_LINE_BYTES
|
||||
* aligned).
|
||||
* @param transfer_length Number of bytes to copy.
|
||||
* @retval RTEMS_SUCCESSFUL on success.
|
||||
* @retval RTEMS_INVALID_NUMBER if @a channel is invalid/unsupported or has
|
||||
* no base address.
|
||||
* @retval RTEMS_INVALID_ADDRESS if @a source_address or @a
|
||||
* destination_address are misaligned.
|
||||
* @retval RTEMS_NO_MEMORY if control block allocation failed.
|
||||
*/
|
||||
rtems_status_code rpi_dma_mem_to_mem_init(
|
||||
rpi_dma_channel channel,
|
||||
void *source_address,
|
||||
void *destination_address,
|
||||
uint32_t transfer_length
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_DMA_H */
|
||||
@@ -1,100 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup raspberrypi_4_i2c
|
||||
*
|
||||
* @brief Raspberry Pi specific I2C definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_I2C_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_I2C_H
|
||||
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <dev/i2c/i2c.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief I2C controller instances on Raspberry Pi 4.
|
||||
*/
|
||||
typedef enum {
|
||||
/**
|
||||
* @brief BSC Master 0 (GPIO 0/1)
|
||||
*/
|
||||
raspberrypi_bscm0,
|
||||
|
||||
/**
|
||||
* @brief BSC Master 1 (GPIO 2/3)
|
||||
*/
|
||||
raspberrypi_bscm1,
|
||||
|
||||
/**
|
||||
* @brief BSC Master 3 (GPIO 4/5)
|
||||
*/
|
||||
raspberrypi_bscm3,
|
||||
|
||||
/**
|
||||
* @brief BSC Master 4 (GPIO 6/7)
|
||||
*/
|
||||
raspberrypi_bscm4,
|
||||
|
||||
/**
|
||||
* @brief BSC Master 5 (GPIO 10/11)
|
||||
*/
|
||||
raspberrypi_bscm5,
|
||||
|
||||
/**
|
||||
* @brief BSC Master 6 (GPIO 22/23)
|
||||
*/
|
||||
raspberrypi_bscm6
|
||||
} raspberrypi_bsc_masters;
|
||||
|
||||
/**
|
||||
* @brief Initialize the I2C bus for a specified master.
|
||||
*
|
||||
* @param device The BSC master to initialize.
|
||||
* @param bus_clock The desired bus clock frequency in Hz.
|
||||
*
|
||||
* @return RTEMS status code indicating success or failure.
|
||||
*/
|
||||
rtems_status_code rpi_i2c_init(
|
||||
raspberrypi_bsc_masters device,
|
||||
uint32_t bus_clock
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_I2C_H */
|
||||
@@ -1,118 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief Raspberry Pi specific PWM definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H
|
||||
|
||||
#include "bsp/raspberrypi.h"
|
||||
#include "bsp/rpi-gpio.h"
|
||||
#include "bsp/utility.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum { raspberrypi_pwm0, raspberrypi_pwm1 } raspberrypi_pwm_channel;
|
||||
|
||||
typedef enum {
|
||||
raspberrypi_pwm_master0,
|
||||
raspberrypi_pwm_master1
|
||||
} raspberrypi_pwm_master;
|
||||
|
||||
/**
|
||||
* @name PWM_CONTROL register bits
|
||||
* @{
|
||||
*/
|
||||
#define C_MSEN2 BSP_BIT32( 15 ) /**< Channel 2 Mark-Space enable */
|
||||
#define C_USEF2 BSP_BIT32( 13 ) /**< Channel 2 use FIFO */
|
||||
#define C_POLA2 BSP_BIT32( 12 ) /**< Channel 2 invert polarity */
|
||||
#define C_SBIT2 BSP_BIT32( 11 ) /**< Channel 2 silence bit high */
|
||||
#define C_RPTL2 BSP_BIT32( 10 ) /**< Channel 2 repeat on underrun */
|
||||
#define C_MODE2 BSP_BIT32( 9 ) /**< Channel 2 serializer mode */
|
||||
#define C_PWEN2 BSP_BIT32( 8 ) /**< Channel 2 enable output */
|
||||
#define C_MSEN1 BSP_BIT32( 7 ) /**< Channel 1 Mark-Space enable */
|
||||
#define C_CLRF BSP_BIT32( 6 ) /**< Clear FIFO */
|
||||
#define C_USEF1 BSP_BIT32( 5 ) /**< Channel 1 use FIFO */
|
||||
#define C_POLA1 BSP_BIT32( 4 ) /**< Channel 1 invert polarity */
|
||||
#define C_SBIT1 BSP_BIT32( 3 ) /**< Channel 1 silence bit high */
|
||||
#define C_RPTL1 BSP_BIT32( 2 ) /**< Channel 1 repeat underrun */
|
||||
#define C_MODE1 BSP_BIT32( 1 ) /**< Channel 1 serializer mode */
|
||||
#define C_PWEN1 BSP_BIT32( 0 ) /**< Channel 1 enable output */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Set PWM clock divider.
|
||||
* @param divisor 1 – 4095; PWMCLK = 19.2 MHz / @p divisor.
|
||||
* @retval RTEMS_SUCCESSFUL OK
|
||||
* @retval RTEMS_INVALID_NUMBER 0 or >4095
|
||||
*/
|
||||
rtems_status_code rpi_pwm_set_clock( uint32_t divisor );
|
||||
|
||||
/**
|
||||
* @brief Update duty-cycle register.
|
||||
* @param master Selects the hardware instance to be used
|
||||
* (raspberrypi_pwm_master0 = PWM0, raspberrypi_pwm_master1 = PWM1)
|
||||
* @param channel Selects the channel for @p master (raspberrypi_pwm0 = PWMx_0,
|
||||
* raspberrypi_pwm1 = PWMx_1)
|
||||
* @param data Initial duty count, 1 – current range value.(0 rejected)
|
||||
*/
|
||||
rtems_status_code rpi_pwm_set_data(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel,
|
||||
uint32_t data
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Main PWM initialization function. This functions sets up the PWM
|
||||
* master, channel, duty cycle and GPIO pin.
|
||||
* @param master Selects the hardware instance to be used
|
||||
* (raspberrypi_pwm_master0 = PWM0, raspberrypi_pwm_master1 = PWM1)
|
||||
* @param channel Selects the channel for @p master (raspberrypi_pwm0 = PWMx_0,
|
||||
* raspberrypi_pwm1 = PWMx_1)
|
||||
* @param range Period register value (> 0)
|
||||
* @param data Initial duty count, 1 – @p range (0 rejected)
|
||||
*/
|
||||
rtems_status_code rpi_pwm_init(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel,
|
||||
uint32_t range,
|
||||
uint32_t data
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_PWM_H */
|
||||
@@ -1,130 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup raspberrypi_4_spi
|
||||
*
|
||||
* @brief Raspberry Pi specific SPI definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_SPI_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_4_SPI_H
|
||||
|
||||
#include <bsp/utility.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t spics;
|
||||
#define RPI_SPICS_LEN_LONG BSP_BIT32(25)
|
||||
#define RPI_SPICS_DMA_LEN BSP_BIT32(24)
|
||||
#define RPI_SPICS_CSPOL2 BSP_BIT32(23)
|
||||
#define RPI_SPICS_CSPOL1 BSP_BIT32(22)
|
||||
#define RPI_SPICS_CSPOL0 BSP_BIT32(21)
|
||||
#define RPI_SPICS_RXF BSP_BIT32(20)
|
||||
#define RPI_SPICS_RXR BSP_BIT32(19)
|
||||
#define RPI_SPICS_TXD BSP_BIT32(18)
|
||||
#define RPI_SPICS_RXD BSP_BIT32(17)
|
||||
#define RPI_SPICS_DONE BSP_BIT32(16)
|
||||
#define RPI_SPICS_LEN BSP_BIT32(13)
|
||||
#define RPI_SPICS_REN BSP_BIT32(12)
|
||||
#define RPI_SPICS_ADCS BSP_BIT32(11)
|
||||
#define RPI_SPICS_INTR BSP_BIT32(10)
|
||||
#define RPI_SPICS_INTD BSP_BIT32(9)
|
||||
#define RPI_SPICS_DMAEN BSP_BIT32(8)
|
||||
#define RPI_SPICS_TA BSP_BIT32(7)
|
||||
#define RPI_SPICS_CSPOL BSP_BIT32(6)
|
||||
#define RPI_SPICS_CLEAR_TX BSP_BIT32(5)
|
||||
#define RPI_SPICS_CLEAR_RX BSP_BIT32(4)
|
||||
#define RPI_SPICS_CPOL BSP_BIT32(3)
|
||||
#define RPI_SPICS_CPHA BSP_BIT32(2)
|
||||
#define RPI_SPICS_CS(val) BSP_FLD32(val, 0, 1)
|
||||
#define RPI_SPICS_CS_SET(reg,val) BSP_FLD32SET(reg, val, 0, 1)
|
||||
uint32_t spififo;
|
||||
#define RPI_SPIFIFO_DATA(val) BSP_FLD32(val, 0, 31)
|
||||
#define RPI_SPIFIFO_DATA_GET(reg) BSP_FLD32GET(reg, 0, 31)
|
||||
#define RPI_SPIFIFO_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
|
||||
uint32_t spiclk;
|
||||
#define RPI_SPICLK_CDIV(val) BSP_FLD32(val, 0, 15)
|
||||
#define RPI_SPICLK_CDIV_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define RPI_SPICLK_CDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
uint32_t spidlen;
|
||||
#define RPI_SPIDLEN_LEN(val) BSP_FLD32(val, 0, 15)
|
||||
#define RPI_SPIDLEN_LEN_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define RPI_SPIDLEN_LEN_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
uint32_t spiltoh;
|
||||
#define RPI_SPILTOH_TOH(val) BSP_FLD32(val, 0, 3)
|
||||
#define RPI_SPILTOH_TOH_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define RPI_SPILTOH_TOH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
uint32_t spidc;
|
||||
#define RPI_SPIDC_RPANIC(val) BSP_FLD32(val, 24, 31)
|
||||
#define RPI_SPIDC_RPANIC_GET(reg) BSP_FLD32GET(reg, 24, 31)
|
||||
#define RPI_SPIDC_RPANIC_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31)
|
||||
#define RPI_SPIDC_RDREQ(val) BSP_FLD32(val, 16, 23)
|
||||
#define RPI_SPIDC_RDREQ_GET(reg) BSP_FLD32GET(reg, 16, 23)
|
||||
#define RPI_SPIDC_RDREQ_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23)
|
||||
#define RPI_SPIDC_TPANIC(val) BSP_FLD32(val, 8, 15)
|
||||
#define RPI_SPIDC_TPANIC_GET(reg) BSP_FLD32GET(reg, 8, 15)
|
||||
#define RPI_SPIDC_TPANIC_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
|
||||
#define RPI_SPIDC_TDREQ(val) BSP_FLD32(val, 0, 7)
|
||||
#define RPI_SPIDC_TDREQ_GET(reg) BSP_FLD32GET(reg, 0, 7)
|
||||
#define RPI_SPIDC_TDREQ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
|
||||
} raspberrypi_spi;
|
||||
|
||||
typedef enum {
|
||||
raspberrypi_SPI0,
|
||||
raspberrypi_SPI3,
|
||||
raspberrypi_SPI4,
|
||||
raspberrypi_SPI5,
|
||||
raspberrypi_SPI6
|
||||
} raspberrypi_spi_device;
|
||||
|
||||
/**
|
||||
* @brief Register a spi device.
|
||||
*
|
||||
* @param device The optional devices are raspberrypi_SPI0, raspberrypi_SPI3,
|
||||
* raspberrypi_SPI4, raspberrypi_SPI5, raspberrypi_SPI6.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL Successfully registered SPI device.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
* @retval RTEMS_UNSATISFIED This status code indicates that the request was
|
||||
* not satisfied.
|
||||
*/
|
||||
rtems_status_code raspberrypi_spi_init(raspberrypi_spi_device device);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_SPI_H */
|
||||
@@ -1,81 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Raspberry Pi 4B Console Device Definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 Utkarsh Verma
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_RASPBERRYPI_UART_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_BSP_RASPBERRYPI_UART_H
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This macro exists to serve as a common point of definition for the
|
||||
* parameters of the UARTs present in the Raspberry Pi 4. It is used in
|
||||
* multiple locations with different rendering macros to prevent duplication
|
||||
* of information.
|
||||
*/
|
||||
#define RASPBERRYPI_CONSOLE_DEVICES(CONSOLE_DEVICE_DEFINITION_RENDERER) \
|
||||
CONSOLE_DEVICE_DEFINITION_RENDERER( \
|
||||
0, "/dev/ttyAMA0", BCM2711_UART0_BASE,BCM2711_UART0_SIZE, \
|
||||
BSP_PL011_CLOCK_FREQ, BCM2711_IRQ_PL011_UART, arm_pl011_context, \
|
||||
&arm_pl011_fns, arm_pl011_write_polled, 15, 14, GPIO_AF0) \
|
||||
CONSOLE_DEVICE_DEFINITION_RENDERER( \
|
||||
2, "/dev/ttyAMA1", BCM2711_UART2_BASE, BCM2711_UART2_SIZE, \
|
||||
BSP_PL011_CLOCK_FREQ, BCM2711_IRQ_PL011_UART, arm_pl011_context, \
|
||||
&arm_pl011_fns, arm_pl011_write_polled, 1, 0, GPIO_AF4) \
|
||||
CONSOLE_DEVICE_DEFINITION_RENDERER( \
|
||||
3, "/dev/ttyAMA2", BCM2711_UART3_BASE, BCM2711_UART3_SIZE, \
|
||||
BSP_PL011_CLOCK_FREQ, BCM2711_IRQ_PL011_UART, arm_pl011_context, \
|
||||
&arm_pl011_fns, arm_pl011_write_polled, 5, 4, GPIO_AF4) \
|
||||
CONSOLE_DEVICE_DEFINITION_RENDERER( \
|
||||
4, "/dev/ttyAMA3", BCM2711_UART4_BASE, BCM2711_UART4_SIZE, \
|
||||
BSP_PL011_CLOCK_FREQ, BCM2711_IRQ_PL011_UART, arm_pl011_context, \
|
||||
&arm_pl011_fns, arm_pl011_write_polled, 9, 8, GPIO_AF4) \
|
||||
CONSOLE_DEVICE_DEFINITION_RENDERER( \
|
||||
5, "/dev/ttyAMA4", BCM2711_UART5_BASE, BCM2711_UART5_SIZE, \
|
||||
BSP_PL011_CLOCK_FREQ, BCM2711_IRQ_PL011_UART, arm_pl011_context, \
|
||||
&arm_pl011_fns, arm_pl011_write_polled, 13, 12, GPIO_AF4)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_BSP_RASPBERRYPI_UART_H */
|
||||
@@ -1,639 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup raspberrypi_4_regs
|
||||
*
|
||||
* @brief Register definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2022 Mohd Noor Aman
|
||||
* Copyright (c) 2024 Ning Yang
|
||||
* Copyright (c) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
|
||||
|
||||
#include <bsp/utility.h>
|
||||
#include <bspopts.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup raspberrypi_reg Register Definitions
|
||||
*
|
||||
* @ingroup RTEMSBSPsARMRaspberryPi
|
||||
*
|
||||
* @brief Register Definitions
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name Register Macros
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_REG( x ) ( *(volatile uintptr_t *) ( x ) )
|
||||
#define BCM2711_BIT( n ) ( 1 << ( n ) )
|
||||
#define BCM2835_REG( addr ) ( *(volatile uint32_t *) (uintptr_t) ( addr ) )
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Peripheral Base Register Address
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RPI_PERIPHERAL_BASE 0xFE000000
|
||||
#define BASE_OFFSET 0xFE000000
|
||||
#define RPI_PERIPHERAL_SIZE 0x01800000
|
||||
|
||||
/**
|
||||
* @name Bus to Physical address translation
|
||||
* Macro.
|
||||
* @{
|
||||
*/
|
||||
#define BUS_TO_PHY( x ) ( ( x ) - BASE_OFFSET )
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Internal ARM Timer Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_CLOCK_FREQ 250000000
|
||||
|
||||
#define BCM2711_TIMER_BASE ( RPI_PERIPHERAL_BASE + 0xB400 )
|
||||
|
||||
#define BCM2711_TIMER_LOD ( BCM2711_TIMER_BASE + 0x00 )
|
||||
#define BCM2711_TIMER_VAL ( BCM2711_TIMER_BASE + 0x04 )
|
||||
#define BCM2711_TIMER_CTL ( BCM2711_TIMER_BASE + 0x08 )
|
||||
#define BCM2711_TIMER_CLI ( BCM2711_TIMER_BASE + 0x0C )
|
||||
#define BCM2711_TIMER_RIS ( BCM2711_TIMER_BASE + 0x10 )
|
||||
#define BCM2711_TIMER_MIS ( BCM2711_TIMER_BASE + 0x14 )
|
||||
#define BCM2711_TIMER_RLD ( BCM2711_TIMER_BASE + 0x18 )
|
||||
#define BCM2711_TIMER_DIV ( BCM2711_TIMER_BASE + 0x1C )
|
||||
#define BCM2711_TIMER_CNT ( BCM2711_TIMER_BASE + 0x20 )
|
||||
|
||||
#define BCM2711_TIMER_PRESCALE 0xF9
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Power Management and Watchdog Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
|
||||
|
||||
#define BCM2711_PM_BASE ( RPI_PERIPHERAL_BASE + 0x100000 )
|
||||
|
||||
#define BCM2711_PM_GNRIC ( BCM2711_PM_BASE + 0x00 )
|
||||
#define BCM2711_PM_GNRIC_POWUP 0x00000001
|
||||
#define BCM2711_PM_GNRIC_POWOK 0x00000002
|
||||
#define BCM2711_PM_GNRIC_ISPOW 0x00000004
|
||||
#define BCM2711_PM_GNRIC_MEMREP 0x00000008
|
||||
#define BCM2711_PM_GNRIC_MRDONE 0x00000010
|
||||
#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
|
||||
#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
|
||||
#define BCM2711_PM_GNRIC_ENAB 0x00001000
|
||||
#define BCM2711_PM_GNRIC_CFG 0x007f0000
|
||||
|
||||
#define BCM2711_PM_AUDIO ( BCM2711_PM_BASE + 0x04 )
|
||||
#define BCM2711_PM_AUDIO_APSM 0x000fffff
|
||||
#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
|
||||
#define BCM2711_PM_AUDIO_RSTN 0x00200000
|
||||
|
||||
#define BCM2711_PM_STATUS ( BCM2711_PM_BASE + 0x18 )
|
||||
|
||||
#define BCM2711_PM_RSTC ( BCM2711_PM_BASE + 0x1c )
|
||||
#define BCM2711_PM_RSTC_DRCFG 0x00000003
|
||||
#define BCM2711_PM_RSTC_WRCFG 0x00000030
|
||||
#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
|
||||
#define BCM2711_PM_RSTC_WRCFG_CLR 0xffffffcf
|
||||
#define BCM2711_PM_RSTC_SRCFG 0x00000300
|
||||
#define BCM2711_PM_RSTC_QRCFG 0x00003000
|
||||
#define BCM2711_PM_RSTC_FRCFG 0x00030000
|
||||
#define BCM2711_PM_RSTC_HRCFG 0x00300000
|
||||
#define BCM2711_PM_RSTC_RESET 0x00000102
|
||||
|
||||
#define BCM2711_PM_RSTS ( BCM2711_PM_BASE + 0x20 )
|
||||
#define BCM2711_PM_RSTS_HADDRQ 0x00000001
|
||||
#define BCM2711_PM_RSTS_HADDRF 0x00000002
|
||||
#define BCM2711_PM_RSTS_HADDRH 0x00000004
|
||||
#define BCM2711_PM_RSTS_HADWRQ 0x00000010
|
||||
#define BCM2711_PM_RSTS_HADWRF 0x0000002
|
||||
#define BCM2711_PM_RSTS_HADWRH 0x00000040
|
||||
#define BCM2711_PM_RSTS_HADSRQ 0x00000100
|
||||
#define BCM2711_PM_RSTS_HADSRF 0x00000200
|
||||
#define BCM2711_PM_RSTS_HADSRH 0x00000400
|
||||
#define BCM2711_PM_RSTS_HADPOR 0x00001000
|
||||
|
||||
#define BCM2711_PM_WDOG ( BCM2711_PM_BASE + 0x24 )
|
||||
#define BCM2711_PM_WDOG_MASK 0x000fffff
|
||||
|
||||
/** @} */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name AUX Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_AUX_BASE ( RPI_PERIPHERAL_BASE + 0x215000 )
|
||||
|
||||
#define AUX_ENABLES ( BCM2711_AUX_BASE + 0x04 )
|
||||
#define AUX_MU_IO_REG ( BCM2711_AUX_BASE + 0x40 )
|
||||
#define AUX_MU_IER_REG ( BCM2711_AUX_BASE + 0x44 )
|
||||
#define AUX_MU_IIR_REG ( BCM2711_AUX_BASE + 0x48 )
|
||||
#define AUX_MU_LCR_REG ( BCM2711_AUX_BASE + 0x4C )
|
||||
#define AUX_MU_MCR_REG ( BCM2711_AUX_BASE + 0x50 )
|
||||
#define AUX_MU_LSR_REG ( BCM2711_AUX_BASE + 0x54 )
|
||||
#define AUX_MU_MSR_REG ( BCM2711_AUX_BASE + 0x58 )
|
||||
#define AUX_MU_SCRATCH ( BCM2711_AUX_BASE + 0x5C )
|
||||
#define AUX_MU_CNTL_REG ( BCM2711_AUX_BASE + 0x60 )
|
||||
#define AUX_MU_STAT_REG ( BCM2711_AUX_BASE + 0x64 )
|
||||
#define AUX_MU_BAUD_REG ( BCM2711_AUX_BASE + 0x68 )
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PL011 UARTs
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define BCM2711_PL011_BASE ( RPI_PERIPHERAL_BASE + 0x201000 )
|
||||
#define BCM2711_PL011_SIZE 0xc00
|
||||
#define BCM2711_PL011_DEVICE_SIZE 0x200
|
||||
|
||||
#define BCM2711_UART0_BASE ( BCM2711_PL011_BASE + 0x000 )
|
||||
#define BCM2711_UART0_SIZE BCM2711_PL011_DEVICE_SIZE
|
||||
#define BCM2711_UART2_BASE ( BCM2711_PL011_BASE + 0x400 )
|
||||
#define BCM2711_UART2_SIZE BCM2711_PL011_DEVICE_SIZE
|
||||
#define BCM2711_UART3_BASE ( BCM2711_PL011_BASE + 0x600 )
|
||||
#define BCM2711_UART3_SIZE BCM2711_PL011_DEVICE_SIZE
|
||||
#define BCM2711_UART4_BASE ( BCM2711_PL011_BASE + 0x800 )
|
||||
#define BCM2711_UART4_SIZE BCM2711_PL011_DEVICE_SIZE
|
||||
#define BCM2711_UART5_BASE ( BCM2711_PL011_BASE + 0xa00 )
|
||||
#define BCM2711_UART5_SIZE BCM2711_PL011_DEVICE_SIZE
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name GPU Timer Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* NOTE: The GPU uses Compare registers 0 and 2 for
|
||||
* it's own RTOS. 1 and 3 are available for use in
|
||||
* RTEMS.
|
||||
*/
|
||||
#define BCM2711_GPU_TIMER_BASE ( RPI_PERIPHERAL_BASE + 0x3000 )
|
||||
|
||||
#define BCM2711_GPU_TIMER_CS ( BCM2711_GPU_TIMER_BASE + 0x00 )
|
||||
#define BCM2711_GPU_TIMER_CS_M0 0x00000001
|
||||
#define BCM2711_GPU_TIMER_CS_M1 0x00000002
|
||||
#define BCM2711_GPU_TIMER_CS_M2 0x00000004
|
||||
#define BCM2711_GPU_TIMER_CS_M3 0x00000008
|
||||
#define BCM2711_GPU_TIMER_CLO ( BCM2711_GPU_TIMER_BASE + 0x04 )
|
||||
#define BCM2711_GPU_TIMER_CHI ( BCM2711_GPU_TIMER_BASE + 0x08 )
|
||||
#define BCM2711_GPU_TIMER_C0 ( BCM2711_GPU_TIMER_BASE + 0x0C )
|
||||
#define BCM2711_GPU_TIMER_C1 ( BCM2711_GPU_TIMER_BASE + 0x10 )
|
||||
#define BCM2711_GPU_TIMER_C2 ( BCM2711_GPU_TIMER_BASE + 0x14 )
|
||||
#define BCM2711_GPU_TIMER_C3 ( BCM2711_GPU_TIMER_BASE + 0x18 )
|
||||
|
||||
/**
|
||||
* NOTE: compatible with the BCM2835 system timer
|
||||
*/
|
||||
#define BCM2835_GPU_TIMER_CS_M3 BCM2711_GPU_TIMER_CS_M3
|
||||
#define BCM2835_GPU_TIMER_C3 BCM2711_GPU_TIMER_C3
|
||||
#define BCM2835_GPU_TIMER_CLO BCM2711_GPU_TIMER_CLO
|
||||
#define BCM2835_GPU_TIMER_CS BCM2711_GPU_TIMER_CS
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name GPIO Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_GPIO_BASE ( RPI_PERIPHERAL_BASE + 0x200000 )
|
||||
#define BCM2711_GPIO_SIZE 0xf4
|
||||
|
||||
#define BCM2711_GPIO_PIN_COUNT 58
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name EMMC Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* NOTE: Since the SD controller follows the SDHCI standard,
|
||||
* the rtems-libbsd tree already provides the remaining registers.
|
||||
*/
|
||||
|
||||
#define BCM2711_EMMC_BASE ( RPI_PERIPHERAL_BASE + 0x300000 )
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name SPI Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_SPI0_BASE ( RPI_PERIPHERAL_BASE + 0x204000 )
|
||||
#define BCM2711_SPI3_BASE ( RPI_PERIPHERAL_BASE + 0x204600 )
|
||||
#define BCM2711_SPI4_BASE ( RPI_PERIPHERAL_BASE + 0x204800 )
|
||||
#define BCM2711_SPI5_BASE ( RPI_PERIPHERAL_BASE + 0x204A00 )
|
||||
#define BCM2711_SPI6_BASE ( RPI_PERIPHERAL_BASE + 0x204C00 )
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWM Clock Manager Register and Offsets
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define BCM2711_CM_PWM_BASE ( RPI_PERIPHERAL_BASE + 0x00101000 )
|
||||
#define BCM2711_CM_PWM_CTL 0xA0
|
||||
#define BCM2711_CM_PWM_DIV 0xA4
|
||||
#define CM_PWM_PASSWD ( 0x5A << 24 )
|
||||
#define CM_PWM_CTL_SRC_OSC BSP_BIT32( 0 )
|
||||
#define CM_PWM_CTL_BUSY BSP_BIT32( 7 )
|
||||
#define CM_PWM_CTL_ENAB BSP_BIT32( 4 )
|
||||
#define CM_PWM_DIV_MASK 0xFFF
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name PWM Registers and offsets
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define BCM2711_PWM0_BASE ( RPI_PERIPHERAL_BASE + 0x0020C000 )
|
||||
#define BCM2711_PWM1_BASE ( RPI_PERIPHERAL_BASE + 0x0020C800 )
|
||||
#define BCM2711_PWM_CONTROL 0x00
|
||||
#define BCM2711_PWM_STATUS 0x04
|
||||
#define BCM2711_PWM_DMAC 0x08
|
||||
#define BCM2711_PWM_RNG1 0x10
|
||||
#define BCM2711_PWM_DAT1 0x14
|
||||
#define BCM2711_PWM_FIFO 0x18
|
||||
#define BCM2711_PWM_RNG2 0x20
|
||||
#define BCM2711_PWM_DAT2 0x24
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name I2C Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define BCM2711_I2C0_BASE ( RPI_PERIPHERAL_BASE + 0x00205000 )
|
||||
#define BCM2711_I2C1_BASE ( RPI_PERIPHERAL_BASE + 0x00804000 )
|
||||
#define BCM2711_I2C3_BASE ( RPI_PERIPHERAL_BASE + 0x00205600 )
|
||||
#define BCM2711_I2C4_BASE ( RPI_PERIPHERAL_BASE + 0x00205800 )
|
||||
#define BCM2711_I2C5_BASE ( RPI_PERIPHERAL_BASE + 0x00205a80 )
|
||||
#define BCM2711_I2C6_BASE ( RPI_PERIPHERAL_BASE + 0x00205c00 )
|
||||
#define BCM2711_I2C_CONTROL 0x0
|
||||
#define BCM2711_I2C_STATUS 0x4
|
||||
#define BCM2711_I2C_DLEN 0x8
|
||||
#define BCM2711_I2C_SLAVE_ADDRESS 0xc
|
||||
#define BCM2711_I2C_FIFO 0x10
|
||||
#define BCM2711_I2C_DIV 0x14
|
||||
#define BCM2711_DELAY 0x18
|
||||
#define BCM2711_I2C_CLKT 0x1c
|
||||
#define BCM2711_I2C_FIFO_MASK 0xFF
|
||||
#define BCM2711_I2C_DLEN_MASK 0xFFFF
|
||||
#define BCM2711_10_BIT_ADDR_MASK 0x78
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name DMA Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_DMA0_BASE ( RPI_PERIPHERAL_BASE + 0x00007000 )
|
||||
#define BCM2711_DMA1_BASE ( BCM2711_DMA0_BASE + 0x100 )
|
||||
#define BCM2711_DMA2_BASE ( BCM2711_DMA0_BASE + 0x200 )
|
||||
#define BCM2711_DMA3_BASE ( BCM2711_DMA0_BASE + 0x300 )
|
||||
#define BCM2711_DMA4_BASE ( BCM2711_DMA0_BASE + 0x400 )
|
||||
#define BCM2711_DMA5_BASE ( BCM2711_DMA0_BASE + 0x500 )
|
||||
#define BCM2711_DMA6_BASE ( BCM2711_DMA0_BASE + 0x600 )
|
||||
#define BCM2711_DMA7_BASE ( BCM2711_DMA0_BASE + 0x700 )
|
||||
#define BCM2711_DMA8_BASE ( BCM2711_DMA0_BASE + 0x800 )
|
||||
#define BCM2711_DMA9_BASE ( BCM2711_DMA0_BASE + 0x900 )
|
||||
#define BCM2711_DMA10_BASE ( BCM2711_DMA0_BASE + 0xa00 )
|
||||
#define BCM2711_DMA11_BASE ( BCM2711_DMA0_BASE + 0xb00 )
|
||||
#define BCM2711_DMA12_BASE ( BCM2711_DMA0_BASE + 0xc00 )
|
||||
#define BCM2711_DMA13_BASE ( BCM2711_DMA0_BASE + 0xd00 )
|
||||
#define BCM2711_DMA14_BASE ( BCM2711_DMA0_BASE + 0xe00 )
|
||||
#define ENABLE ( RPI_PERIPHERAL_BASE + 0x00007FF0 )
|
||||
#define CS_OFFSET 0x00
|
||||
#define CONBLK_AD_OFFSET 0x04
|
||||
#define DEBUG_OFFSET 0x020
|
||||
#define INT_STATUS_OFFSET 0xfe0
|
||||
#define CS_RESET ( 1 << 31 )
|
||||
#define CS_ABORT ( 1 << 30 )
|
||||
#define CS_END ( 1 << 1 )
|
||||
#define CS_WAIT_FOR_OUTSTANDING_WRITES ( 1 << 28 )
|
||||
#define CS_PRIORITY_SHIFT ( 1 << 16 )
|
||||
#define CS_PANIC_PRIORITY_SHIFT ( 15 << 20 )
|
||||
#define CS_ACTIVE ( 1 << 0 )
|
||||
#define CS_ERROR ( 1 << 8 )
|
||||
#define TI_DEST_INC ( 1 << 4 )
|
||||
#define TI_SRC_INC ( 1 << 8 )
|
||||
#define TI_SRC_WIDTH ( 1 << 9 )
|
||||
#define TI_DEST_WIDTH ( 1 << 5 )
|
||||
#define TI_PERMAP( x ) ( ( x ) << 16 )
|
||||
#define TI_SRC_DREQ ( 1 << 10 )
|
||||
#define TI_DEST_DREQ ( 1 << 6 )
|
||||
#define TI_WAIT_RESP ( 1 << 3 )
|
||||
#define TI_NO_WIDE_BURSTS ( 1 << 26 )
|
||||
#define SI_SRC_INC ( 1 << 12 )
|
||||
#define DI_DEST_INC ( 1 << 12 )
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Mailbox Registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_MBOX_BASE ( RPI_PERIPHERAL_BASE + 0xB880 )
|
||||
|
||||
#define BCM2711_MBOX_READ ( BCM2711_MBOX_BASE + 0x00 )
|
||||
#define BCM2711_MBOX_PEEK ( BCM2711_MBOX_BASE + 0x10 )
|
||||
#define BCM2711_MBOX_SENDER ( BCM2711_MBOX_BASE + 0x14 )
|
||||
#define BCM2711_MBOX_STATUS ( BCM2711_MBOX_BASE + 0x18 )
|
||||
#define BCM2711_MBOX_WRITE ( BCM2711_MBOX_BASE + 0x20 )
|
||||
#define BCM2711_MBOX_CONFIG ( BCM2711_MBOX_BASE + 0x1C )
|
||||
|
||||
#define BCM2711_MBOX_RESPONSE 0x80000000
|
||||
#define BCM2711_MBOX_FULL 0x80000000
|
||||
#define BCM2711_MBOX_EMPTY 0x40000000
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Mailbox Channels
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Power Manager channel */
|
||||
#define BCM2711_MBOX_CHANNEL_PM 0
|
||||
/* Framebuffer channel */
|
||||
#define BCM2711_MBOX_CHANNEL_FB 1
|
||||
/* Virtual UART channel */
|
||||
#define BCM2711_MBOX_CHANNEL_VUART 2
|
||||
/* VCHIQ channel */
|
||||
#define BCM2711_MBOX_CHANNEL_VCHIQ 3
|
||||
/* LEDs channel */
|
||||
#define BCM2711_MBOX_CHANNEL_LED 4
|
||||
/* Button channel */
|
||||
#define BCM2711_MBOX_CHANNEL_BUTTON 5
|
||||
/* Touch screen channel */
|
||||
#define BCM2711_MBOX_CHANNEL_TOUCHS 6
|
||||
|
||||
#define BCM2711_MBOX_CHANNEL_COUNT 7
|
||||
/* Property tags (ARM <-> VC) channel */
|
||||
#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
|
||||
/* Property tags (VC <-> ARM) channel */
|
||||
#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Raspberry Pi 2 Interrupt Register Defines
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Timers interrupt control registers */
|
||||
#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
|
||||
#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
|
||||
#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
|
||||
#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
|
||||
|
||||
#define BCM2711_CORE_TIMER_IRQ_CTRL( cpuidx ) \
|
||||
( BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * ( cpuidx ) )
|
||||
|
||||
/**
|
||||
* @name Raspberry Pi 4 ARM_LOCAL registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
|
||||
#define BCM2711_LOCAL_REGS_SIZE 0x100
|
||||
|
||||
#define BCM2711_LOCAL_ARM_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x00 )
|
||||
#define BCM2711_LOCAL_CORE_IRQ_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x0c )
|
||||
#define BCM2711_LOCAL_PMU_CONTROL_SET ( BCM2711_LOCAL_REGS_BASE + 0x10 )
|
||||
#define BCM2711_LOCAL_PMU_CONTROL_CLR ( BCM2711_LOCAL_REGS_BASE + 0x14 )
|
||||
#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 ( BCM2711_LOCAL_REGS_BASE + 0x24 )
|
||||
#define BCM2711_LOCAL_AXI_QUIET_TIME ( BCM2711_LOCAL_REGS_BASE + 0x30 )
|
||||
#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL ( BCM2711_LOCAL_REGS_BASE + 0x34 )
|
||||
#define BCM2711_LOCAL_LOCAL_TIMER_IRQ ( BCM2711_LOCAL_REGS_BASE + 0x38 )
|
||||
|
||||
#define BCM2711_LOCAL_TIMER_CNTRL0 ( BCM2711_LOCAL_REGS_BASE + 0x40 )
|
||||
#define BCM2711_LOCAL_TIMER_CNTRL1 ( BCM2711_LOCAL_REGS_BASE + 0x44 )
|
||||
#define BCM2711_LOCAL_TIMER_CNTRL2 ( BCM2711_LOCAL_REGS_BASE + 0x48 )
|
||||
#define BCM2711_LOCAL_TIMER_CNTRL3 ( BCM2711_LOCAL_REGS_BASE + 0x4c )
|
||||
|
||||
#define BCM2711_LOCAL_MAILBOX_CNTRL0 ( BCM2711_LOCAL_REGS_BASE + 0x50 )
|
||||
#define BCM2711_LOCAL_MAILBOX_CNTRL1 ( BCM2711_LOCAL_REGS_BASE + 0x54 )
|
||||
#define BCM2711_LOCAL_MAILBOX_CNTRL2 ( BCM2711_LOCAL_REGS_BASE + 0x58 )
|
||||
#define BCM2711_LOCAL_MAILBOX_CNTRL3 ( BCM2711_LOCAL_REGS_BASE + 0x5c )
|
||||
|
||||
#define BCM2711_LOCAL_IRQ_SOURCE0 ( BCM2711_LOCAL_REGS_BASE + 0x60 )
|
||||
#define BCM2711_LOCAL_IRQ_SOURCE1 ( BCM2711_LOCAL_REGS_BASE + 0x64 )
|
||||
#define BCM2711_LOCAL_IRQ_SOURCE2 ( BCM2711_LOCAL_REGS_BASE + 0x68 )
|
||||
#define BCM2711_LOCAL_IRQ_SOURCE3 ( BCM2711_LOCAL_REGS_BASE + 0x6c )
|
||||
|
||||
#define BCM2711_LOCAL_FIQ_SOURCE0 ( BCM2711_LOCAL_REGS_BASE + 0x70 )
|
||||
#define BCM2711_LOCAL_FIQ_SOURCE1 ( BCM2711_LOCAL_REGS_BASE + 0x74 )
|
||||
#define BCM2711_LOCAL_FIQ_SOURCE2 ( BCM2711_LOCAL_REGS_BASE + 0x78 )
|
||||
#define BCM2711_LOCAL_FIQ_SOURCE3 ( BCM2711_LOCAL_REGS_BASE + 0x7c )
|
||||
|
||||
/**
|
||||
* @name Raspberry Pi 4 Mailbox registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
|
||||
#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
|
||||
#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
|
||||
#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
|
||||
#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
|
||||
#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
|
||||
#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
|
||||
#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
|
||||
#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
|
||||
#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
|
||||
#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
|
||||
#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
|
||||
#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
|
||||
#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
|
||||
#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
|
||||
#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
|
||||
|
||||
#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
|
||||
#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
|
||||
#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
|
||||
#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
|
||||
#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
|
||||
#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
|
||||
#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
|
||||
#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
|
||||
#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
|
||||
#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
|
||||
#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
|
||||
#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
|
||||
#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
|
||||
#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
|
||||
#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
|
||||
#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
|
||||
|
||||
/**
|
||||
* @name Raspberry Pi 4 ARM_C FIQ and IRQ registers
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BCM2711_ARMC_REGS_BASE ( RPI_PERIPHERAL_BASE + 0xB200 )
|
||||
#define BCM2711_ARMC_REGS_SIZE 0x200
|
||||
|
||||
#define BCM2711_ARMC_IRQ0_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x00 )
|
||||
#define BCM2711_ARMC_IRQ0_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x04 )
|
||||
#define BCM2711_ARMC_IRQ0_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x08 )
|
||||
#define BCM2711_ARMC_IRQ0_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x10 )
|
||||
#define BCM2711_ARMC_IRQ0_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x14 )
|
||||
#define BCM2711_ARMC_IRQ0_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x18 )
|
||||
#define BCM2711_ARMC_IRQ0_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x20 )
|
||||
#define BCM2711_ARMC_IRQ0_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x24 )
|
||||
#define BCM2711_ARMC_IRQ0_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x28 )
|
||||
|
||||
#define BCM2711_ARMC_IRQ_STATUS0 ( BCM2711_ARMC_REGS_BASE + 0x30 )
|
||||
#define BCM2711_ARMC_IRQ_STATUS1 ( BCM2711_ARMC_REGS_BASE + 0x34 )
|
||||
#define BCM2711_ARMC_IRQ_STATUS2 ( BCM2711_ARMC_REGS_BASE + 0x38 )
|
||||
|
||||
#define BCM2711_ARMC_IRQ1_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x40 )
|
||||
#define BCM2711_ARMC_IRQ1_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x44 )
|
||||
#define BCM2711_ARMC_IRQ1_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x48 )
|
||||
#define BCM2711_ARMC_IRQ1_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x50 )
|
||||
#define BCM2711_ARMC_IRQ1_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x54 )
|
||||
#define BCM2711_ARMC_IRQ1_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x58 )
|
||||
#define BCM2711_ARMC_IRQ1_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x60 )
|
||||
#define BCM2711_ARMC_IRQ1_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x64 )
|
||||
#define BCM2711_ARMC_IRQ1_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x68 )
|
||||
|
||||
#define BCM2711_ARMC_IRQ2_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x80 )
|
||||
#define BCM2711_ARMC_IRQ2_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x84 )
|
||||
#define BCM2711_ARMC_IRQ2_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x88 )
|
||||
#define BCM2711_ARMC_IRQ2_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x90 )
|
||||
#define BCM2711_ARMC_IRQ2_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x94 )
|
||||
#define BCM2711_ARMC_IRQ2_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x98 )
|
||||
#define BCM2711_ARMC_IRQ2_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xA0 )
|
||||
#define BCM2711_ARMC_IRQ2_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xA4 )
|
||||
#define BCM2711_ARMC_IRQ2_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xA8 )
|
||||
|
||||
#define BCM2711_ARMC_IRQ3_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0xC0 )
|
||||
#define BCM2711_ARMC_IRQ3_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0xC4 )
|
||||
#define BCM2711_ARMC_IRQ3_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0xC8 )
|
||||
#define BCM2711_ARMC_IRQ3_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xD0 )
|
||||
#define BCM2711_ARMC_IRQ3_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xD4 )
|
||||
#define BCM2711_ARMC_IRQ3_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xD8 )
|
||||
#define BCM2711_ARMC_IRQ3_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0xE0 )
|
||||
#define BCM2711_ARMC_IRQ3_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0xE4 )
|
||||
#define BCM2711_ARMC_IRQ3_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0xE8 )
|
||||
|
||||
#define BCM2711_ARMC_FIQ0_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x100 )
|
||||
#define BCM2711_ARMC_FIQ0_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x104 )
|
||||
#define BCM2711_ARMC_FIQ0_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x108 )
|
||||
#define BCM2711_ARMC_FIQ0_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x110 )
|
||||
#define BCM2711_ARMC_FIQ0_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x114 )
|
||||
#define BCM2711_ARMC_FIQ0_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x118 )
|
||||
#define BCM2711_ARMC_FIQ0_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x120 )
|
||||
#define BCM2711_ARMC_FIQ0_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x124 )
|
||||
#define BCM2711_ARMC_FIQ0_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x128 )
|
||||
|
||||
#define BCM2711_ARMC_FIQ1_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x140 )
|
||||
#define BCM2711_ARMC_FIQ1_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x144 )
|
||||
#define BCM2711_ARMC_FIQ1_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x148 )
|
||||
#define BCM2711_ARMC_FIQ1_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x150 )
|
||||
#define BCM2711_ARMC_FIQ1_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x154 )
|
||||
#define BCM2711_ARMC_FIQ1_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x158 )
|
||||
#define BCM2711_ARMC_FIQ1_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x160 )
|
||||
#define BCM2711_ARMC_FIQ1_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x164 )
|
||||
#define BCM2711_ARMC_FIQ1_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x168 )
|
||||
|
||||
#define BCM2711_ARMC_FIQ2_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x180 )
|
||||
#define BCM2711_ARMC_FIQ2_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x184 )
|
||||
#define BCM2711_ARMC_FIQ2_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x188 )
|
||||
#define BCM2711_ARMC_FIQ2_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x190 )
|
||||
#define BCM2711_ARMC_FIQ2_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x194 )
|
||||
#define BCM2711_ARMC_FIQ2_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x198 )
|
||||
#define BCM2711_ARMC_FIQ2_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1A0 )
|
||||
#define BCM2711_ARMC_FIQ2_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1A4 )
|
||||
#define BCM2711_ARMC_FIQ2_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1A8 )
|
||||
|
||||
#define BCM2711_ARMC_FIQ3_PENDING0 ( BCM2711_ARMC_REGS_BASE + 0x1C0 )
|
||||
#define BCM2711_ARMC_FIQ3_PENDING1 ( BCM2711_ARMC_REGS_BASE + 0x1C4 )
|
||||
#define BCM2711_ARMC_FIQ3_PENDING2 ( BCM2711_ARMC_REGS_BASE + 0x1C8 )
|
||||
#define BCM2711_ARMC_FIQ3_SET_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1D0 )
|
||||
#define BCM2711_ARMC_FIQ3_SET_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1D4 )
|
||||
#define BCM2711_ARMC_FIQ3_SET_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1D8 )
|
||||
#define BCM2711_ARMC_FIQ3_CLR_EN_0 ( BCM2711_ARMC_REGS_BASE + 0x1E0 )
|
||||
#define BCM2711_ARMC_FIQ3_CLR_EN_1 ( BCM2711_ARMC_REGS_BASE + 0x1E4 )
|
||||
#define BCM2711_ARMC_FIQ3_CLR_EN_2 ( BCM2711_ARMC_REGS_BASE + 0x1E8 )
|
||||
|
||||
#define BCM2711_ARMC_SWIRQ_SET ( BCM2711_ARMC_REGS_BASE + 0x1F0 )
|
||||
#define BCM2711_ARMC_SWIRQ_CLEAR ( BCM2711_ARMC_REGS_BASE + 0x1F4 )
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
|
||||
@@ -1,126 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Raspberry Pi 4B specific GPIO definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 Utkarsh Verma
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_RPI_GPIO_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_BSP_RPI_GPIO_H
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <rtems/rtems/status.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Raspberry Pi GPIO functions.
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
GPIO_INPUT,
|
||||
GPIO_OUTPUT,
|
||||
GPIO_AF5,
|
||||
GPIO_AF4,
|
||||
GPIO_AF0,
|
||||
GPIO_AF1,
|
||||
GPIO_AF2,
|
||||
GPIO_AF3,
|
||||
} raspberrypi_gpio_function;
|
||||
|
||||
typedef enum {
|
||||
GPIO_PULL_NONE,
|
||||
GPIO_PULL_UP,
|
||||
GPIO_PULL_DOWN,
|
||||
} raspberrypi_gpio_pull;
|
||||
|
||||
/**
|
||||
* @brief Set the operation of the general-purpose I/O pins. Each of the 58
|
||||
* GPIO pins has at least two alternative functions as defined.
|
||||
*
|
||||
* @param pin The GPIO pin.
|
||||
* @param value The optional functions are GPIO_INPUT, GPIO_OUTPUT, GPIO_AF5,
|
||||
* GPIO_AF4, GPIO_AF0, GPIO_AF1, GPIO_AF2, GPIO_AF3.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL GPIO function successfully configured.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
*/
|
||||
rtems_status_code raspberrypi_gpio_set_function(
|
||||
const unsigned int pin,
|
||||
const raspberrypi_gpio_function value
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief Set a GPIO pin.
|
||||
*
|
||||
* @param pin The GPIO pin.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL GPIO pin set successfully.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
*/
|
||||
rtems_status_code raspberrypi_gpio_set_pin(const unsigned int pin);
|
||||
|
||||
/**
|
||||
* @brief Clear a GPIO pin.
|
||||
*
|
||||
* @param pin The GPIO pin.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL GPIO pin clear successfully.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
*/
|
||||
rtems_status_code raspberrypi_gpio_clear_pin(const unsigned int pin);
|
||||
|
||||
/**
|
||||
* @brief Control the actuation of the internal pull-up/down resistors.
|
||||
*
|
||||
* @param pin The GPIO pin.
|
||||
* @param value The optional value are GPIO_PULL_NONE, GPIO_PULL_UP,
|
||||
* GPIO_PULL_DOWN.
|
||||
*
|
||||
* @retval RTEMS_SUCCESSFUL GPIO pull set successfully.
|
||||
* @retval RTEMS_INVALID_NUMBER This status code indicates that a specified
|
||||
* number was invalid.
|
||||
*/
|
||||
rtems_status_code raspberrypi_gpio_set_pull(
|
||||
const unsigned int pin,
|
||||
const raspberrypi_gpio_pull value
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_RASPBERRYPI_BSP_RPI_GPIO_H */
|
||||
@@ -1,97 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief API of the Watchdog driver for the raspberrypi4 bsp in RTEMS.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_RASPBERRYPI_BSP_RPI_WATCHDOG_H
|
||||
#define LIBBSP_AARCH64_RASPBERRYPI_BSP_RPI_WATCHDOG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @note a brief example of expected usage.
|
||||
*
|
||||
* void raspberrypi_watchdog_example()
|
||||
* {
|
||||
* raspberrypi_watchdog_init();
|
||||
* raspberrypi_watchdog_start(15000);
|
||||
*
|
||||
* raspberrypi_watchdog_reload();
|
||||
* ...
|
||||
* raspberrypi_watchdog_reload();
|
||||
*
|
||||
* raspberrypi_watchdog_stop();
|
||||
* }
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize BSP watchdog routines.
|
||||
*/
|
||||
void raspberrypi_watchdog_init(void);
|
||||
|
||||
/**
|
||||
* @brief Turn on the watchdog / begin the counter at the desired value.
|
||||
*
|
||||
* @param timeout Watchdog timeout value in ms.
|
||||
* The watchdog device has 20 bits of timeout, so it only
|
||||
* supports a maximum of 15999 ms for its timeout.
|
||||
* This value should be between 0 and 15999.
|
||||
*/
|
||||
void raspberrypi_watchdog_start(uint32_t timeout_ms);
|
||||
|
||||
/**
|
||||
* @brief Turn off the watchdog.
|
||||
*/
|
||||
void raspberrypi_watchdog_stop(void);
|
||||
|
||||
/**
|
||||
* @brief Reload watchdog.
|
||||
*/
|
||||
void raspberrypi_watchdog_reload(void);
|
||||
|
||||
/**
|
||||
* @brief Get the remaining time of the watchdog.
|
||||
* The return value is still valid when the watchdog has been stopped.
|
||||
*
|
||||
* @retval Watchdog remaining time in ms.
|
||||
*/
|
||||
uint32_t raspberrypi_watchdog_get_remaining_time(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief BSP tm27 header
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <dev/irq/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -1,198 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief PWM Support
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Shaunak Datar
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "bsp/raspberrypi-pwm.h"
|
||||
|
||||
// Clock manager macros
|
||||
#define BCM2711_CM_PWM( x ) BCM2835_REG( BCM2711_CM_PWM_BASE + ( x ) )
|
||||
#define CM_PWM_CTL_ENABLE_OSC \
|
||||
( CM_PWM_PASSWD | CM_PWM_CTL_ENAB | CM_PWM_CTL_SRC_OSC )
|
||||
#define CM_PWM_CTL_DISABLE ( CM_PWM_PASSWD | CM_PWM_CTL_SRC_OSC )
|
||||
|
||||
static inline bool rpi_pwm_validate(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel
|
||||
)
|
||||
{
|
||||
return ( ( master == raspberrypi_pwm_master0 ) ||
|
||||
( master == raspberrypi_pwm_master1 ) ) &&
|
||||
( ( channel == raspberrypi_pwm0 ) || ( channel == raspberrypi_pwm1 ) );
|
||||
}
|
||||
|
||||
rtems_status_code rpi_pwm_set_clock( uint32_t divisor )
|
||||
{
|
||||
if ( !( divisor > 0 && divisor < 4096 ) ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
/* Stop Clock */
|
||||
BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) = CM_PWM_CTL_DISABLE;
|
||||
while ( BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) & CM_PWM_CTL_BUSY );
|
||||
|
||||
/* Set divisor */
|
||||
divisor &= CM_PWM_DIV_MASK;
|
||||
BCM2711_CM_PWM( BCM2711_CM_PWM_DIV ) = CM_PWM_PASSWD | ( divisor << 12 );
|
||||
|
||||
/* Select src = osc(1) and enable */
|
||||
BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) = CM_PWM_CTL_ENABLE_OSC;
|
||||
while ( !( BCM2711_CM_PWM( BCM2711_CM_PWM_CTL ) & CM_PWM_CTL_BUSY ) );
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code rpi_pwm_set_control(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel
|
||||
)
|
||||
{
|
||||
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
|
||||
BCM2711_PWM0_BASE :
|
||||
BCM2711_PWM1_BASE;
|
||||
uint32_t control_reg = pwm_base + BCM2711_PWM_CONTROL;
|
||||
uint32_t control = BCM2835_REG( control_reg );
|
||||
|
||||
if ( channel == raspberrypi_pwm0 ) {
|
||||
control &= ~( C_MODE1 | C_POLA1 | C_SBIT1 | C_RPTL1 | C_USEF1 );
|
||||
control |= ( C_PWEN1 | C_CLRF | C_MSEN1 );
|
||||
} else {
|
||||
control &= ~( C_MODE2 | C_POLA2 | C_SBIT2 | C_RPTL2 | C_USEF2 );
|
||||
control |= ( C_PWEN2 | C_CLRF | C_MSEN2 );
|
||||
}
|
||||
BCM2835_REG( control_reg ) = control;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code rpi_pwm_set_range(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel,
|
||||
uint32_t range
|
||||
)
|
||||
{
|
||||
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
|
||||
BCM2711_PWM0_BASE :
|
||||
BCM2711_PWM1_BASE;
|
||||
uint32_t range_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_RNG1 :
|
||||
BCM2711_PWM_RNG2;
|
||||
|
||||
BCM2835_REG( pwm_base + range_offset ) = range;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_status_code rpi_pwm_set_data(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel,
|
||||
uint32_t data
|
||||
)
|
||||
{
|
||||
if ( !( rpi_pwm_validate( master, channel ) ) || data == 0 ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
uint32_t pwm_base = ( master == raspberrypi_pwm_master0 ) ?
|
||||
BCM2711_PWM0_BASE :
|
||||
BCM2711_PWM1_BASE;
|
||||
uint32_t range_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_RNG1 :
|
||||
BCM2711_PWM_RNG2;
|
||||
|
||||
if ( data > BCM2835_REG( pwm_base + range_offset ) ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
uint32_t data_offset = ( channel == raspberrypi_pwm0 ) ? BCM2711_PWM_DAT1 :
|
||||
BCM2711_PWM_DAT2;
|
||||
|
||||
BCM2835_REG( pwm_base + data_offset ) = data;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static rtems_status_code rpi_pwm_set_gpio(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel
|
||||
)
|
||||
{
|
||||
rtems_status_code sc;
|
||||
|
||||
if ( master == raspberrypi_pwm_master0 ) {
|
||||
if ( channel == raspberrypi_pwm0 ) {
|
||||
sc = raspberrypi_gpio_set_function( 18, GPIO_AF5 );
|
||||
} else {
|
||||
sc = raspberrypi_gpio_set_function( 19, GPIO_AF5 );
|
||||
}
|
||||
} else {
|
||||
if ( channel == raspberrypi_pwm0 ) {
|
||||
sc = raspberrypi_gpio_set_function( 40, GPIO_AF0 );
|
||||
} else {
|
||||
sc = raspberrypi_gpio_set_function( 41, GPIO_AF0 );
|
||||
}
|
||||
}
|
||||
|
||||
return sc;
|
||||
}
|
||||
|
||||
rtems_status_code rpi_pwm_init(
|
||||
raspberrypi_pwm_master master,
|
||||
raspberrypi_pwm_channel channel,
|
||||
uint32_t range,
|
||||
uint32_t data
|
||||
)
|
||||
{
|
||||
rtems_status_code sc;
|
||||
|
||||
if ( !( rpi_pwm_validate( master, channel ) ) || range == 0 ) {
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
sc = rpi_pwm_set_gpio( master, channel );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
sc = rpi_pwm_set_range( master, channel, range );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
sc = rpi_pwm_set_data( master, channel, data );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
sc = rpi_pwm_set_control( master, channel );
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,582 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief SPI Driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/raspberrypi-spi.h>
|
||||
#include <bsp/rpi-gpio.h>
|
||||
|
||||
#include <dev/spi/spi.h>
|
||||
#include <bspopts.h>
|
||||
|
||||
typedef struct {
|
||||
spi_bus base;
|
||||
volatile raspberrypi_spi *regs;
|
||||
const spi_ioc_transfer *msg;
|
||||
uint32_t msg_todo;
|
||||
uint8_t *rx_buf;
|
||||
const uint8_t *tx_buf;
|
||||
uint32_t todo;
|
||||
uint8_t num_cs;
|
||||
uint32_t in_transfer;
|
||||
rtems_id task_id;
|
||||
rtems_vector_number irq;
|
||||
}raspberrypi_spi_bus;
|
||||
|
||||
static int raspberrypi_spi_check_msg(
|
||||
raspberrypi_spi_bus *bus,
|
||||
const spi_ioc_transfer *msg,
|
||||
uint32_t n
|
||||
)
|
||||
{
|
||||
while (n > 0) {
|
||||
if (msg->bits_per_word != 8) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if ((msg->mode &
|
||||
~(SPI_CPHA | SPI_CPOL | SPI_NO_CS)) != 0) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (msg->cs >= bus->num_cs) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
++msg;
|
||||
--n;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Calculates a clock divider to be used with the GPU core clock rate
|
||||
* to set a SPI clock rate the closest (<=) to a desired frequency. */
|
||||
static rtems_status_code rpi_spi_calculate_clock_divider(
|
||||
uint32_t clock_hz,
|
||||
uint16_t *clock_divider
|
||||
)
|
||||
{
|
||||
uint16_t divider;
|
||||
uint32_t clock_rate;
|
||||
|
||||
/* Calculates an initial clock divider. */
|
||||
divider = GPU_CORE_CLOCK_RATE / clock_hz;
|
||||
|
||||
/* Because the divider must be a power of two (as per the BCM2835 datasheet),
|
||||
* calculate the next greater power of two. */
|
||||
--divider;
|
||||
|
||||
divider |= (divider >> 1);
|
||||
divider |= (divider >> 2);
|
||||
divider |= (divider >> 4);
|
||||
divider |= (divider >> 8);
|
||||
|
||||
++divider;
|
||||
|
||||
clock_rate = GPU_CORE_CLOCK_RATE / divider;
|
||||
|
||||
/* If the resulting clock rate is greater than the desired frequency,
|
||||
* try the next greater power of two divider. */
|
||||
while (clock_rate > clock_hz) {
|
||||
divider = (divider << 1);
|
||||
|
||||
clock_rate = GPU_CORE_CLOCK_RATE / divider;
|
||||
}
|
||||
|
||||
*clock_divider = divider;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int raspberrypi_spi_config(
|
||||
raspberrypi_spi_bus *bus,
|
||||
volatile raspberrypi_spi *regs,
|
||||
uint32_t speed_hz,
|
||||
uint32_t mode,
|
||||
uint8_t cs
|
||||
)
|
||||
{
|
||||
spi_bus *base = &bus->base;
|
||||
uint32_t spics = regs->spics;
|
||||
rtems_status_code sc;
|
||||
uint16_t clock_divider;
|
||||
|
||||
/* Calculate the most appropriate clock divider. */
|
||||
sc = rpi_spi_calculate_clock_divider(speed_hz, &clock_divider);
|
||||
if (sc != RTEMS_SUCCESSFUL) {
|
||||
return sc;
|
||||
}
|
||||
/* Set the bus clock divider. */
|
||||
regs->spiclk = RPI_SPICLK_CDIV_SET(regs->spiclk, clock_divider);
|
||||
|
||||
if ((mode & SPI_CPHA) != 0) {
|
||||
spics |= RPI_SPICS_CPHA;
|
||||
} else {
|
||||
spics &= ~RPI_SPICS_CPHA;
|
||||
}
|
||||
|
||||
if ((mode & SPI_CPOL) != 0) {
|
||||
spics |= RPI_SPICS_CPOL;
|
||||
} else {
|
||||
spics &= ~RPI_SPICS_CPOL;
|
||||
}
|
||||
|
||||
if ((mode & SPI_CS_HIGH) != 0) {
|
||||
spics |= RPI_SPICS_CSPOL;
|
||||
} else {
|
||||
spics &= ~RPI_SPICS_CSPOL;
|
||||
}
|
||||
|
||||
spics = RPI_SPICS_CS_SET(spics, cs);
|
||||
|
||||
regs->spics = spics;
|
||||
|
||||
base->speed_hz = speed_hz;
|
||||
base->mode = mode;
|
||||
base->cs = cs;
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef BSP_SPI_USE_INTERRUPTS
|
||||
static void raspberrypi_spi_done(raspberrypi_spi_bus *bus)
|
||||
{
|
||||
volatile raspberrypi_spi *regs;
|
||||
regs = bus->regs;
|
||||
regs->spics = regs->spics & ~RPI_SPICS_TA;
|
||||
rtems_event_transient_send(bus->task_id);
|
||||
}
|
||||
|
||||
static bool raspberrpi_spi_TX_FULL(volatile raspberrypi_spi *regs)
|
||||
{
|
||||
return !(regs->spics & RPI_SPICS_TXD);
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_push(
|
||||
raspberrypi_spi_bus *bus,
|
||||
volatile raspberrypi_spi *regs
|
||||
)
|
||||
{
|
||||
uint8_t val;
|
||||
while (bus->todo > 0 && !raspberrpi_spi_TX_FULL(regs)) {
|
||||
val = 0;
|
||||
if (bus->tx_buf != NULL) {
|
||||
val = *bus->tx_buf;
|
||||
++bus->tx_buf;
|
||||
}
|
||||
|
||||
--bus->todo;
|
||||
regs->spififo = val;
|
||||
++bus->in_transfer;
|
||||
}
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_next_msg(raspberrypi_spi_bus *bus)
|
||||
{
|
||||
const spi_ioc_transfer *msg;
|
||||
spi_bus *base;
|
||||
volatile raspberrypi_spi *regs;
|
||||
regs=bus->regs;
|
||||
|
||||
if (bus->msg_todo > 0) {
|
||||
base = &bus->base;
|
||||
msg = bus->msg;
|
||||
|
||||
if (
|
||||
msg->speed_hz != base->speed_hz
|
||||
|| msg->mode != base->mode
|
||||
|| msg->cs != base->cs
|
||||
) {
|
||||
raspberrypi_spi_config(
|
||||
bus,
|
||||
regs,
|
||||
msg->speed_hz,
|
||||
msg->mode,
|
||||
msg->cs
|
||||
);
|
||||
}
|
||||
|
||||
bus->todo = msg->len;
|
||||
bus->rx_buf = msg->rx_buf;
|
||||
bus->tx_buf = msg->tx_buf;
|
||||
raspberrypi_spi_push(bus, regs);
|
||||
} else {
|
||||
raspberrypi_spi_done(bus);
|
||||
}
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_start(raspberrypi_spi_bus *bus)
|
||||
{
|
||||
volatile raspberrypi_spi *regs;
|
||||
regs = bus->regs;
|
||||
|
||||
regs->spics = regs->spics | RPI_SPICS_INTR | RPI_SPICS_INTD;
|
||||
/*
|
||||
* Set TA = 1. This will immediately trigger a first interrupt with
|
||||
* DONE = 1.
|
||||
*/
|
||||
regs->spics = regs->spics | RPI_SPICS_TA;
|
||||
}
|
||||
|
||||
static bool raspberrypi_spi_irq(volatile raspberrypi_spi *regs)
|
||||
{
|
||||
/* Check whether the interrupt is generated by this SPI device */
|
||||
if(regs->spics & RPI_SPICS_INTD && regs->spics & RPI_SPICS_DONE) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
if(regs->spics & RPI_SPICS_INTR && regs->spics & RPI_SPICS_RXR) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_interrupt(void *arg)
|
||||
{
|
||||
raspberrypi_spi_bus *bus;
|
||||
volatile raspberrypi_spi *regs;
|
||||
uint32_t val;
|
||||
|
||||
bus = arg;
|
||||
regs = bus->regs;
|
||||
|
||||
if (raspberrypi_spi_irq(regs)) {
|
||||
|
||||
if (bus->todo > 0) {
|
||||
raspberrypi_spi_push(bus, regs);
|
||||
} else {
|
||||
--bus->msg_todo;
|
||||
++bus->msg;
|
||||
raspberrypi_spi_next_msg(bus);
|
||||
}
|
||||
|
||||
while (regs->spics & RPI_SPICS_RXD && bus->in_transfer > 0) {
|
||||
/* RX FIFO contains at least 1 byte. */
|
||||
val = regs->spififo;
|
||||
if (bus->rx_buf != NULL) {
|
||||
*bus->rx_buf = (uint8_t)val;
|
||||
++bus->rx_buf;
|
||||
}
|
||||
--bus->in_transfer;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
#else
|
||||
static void raspberrypi_spi_polling_tx_rx(raspberrypi_spi_bus *bus)
|
||||
{
|
||||
volatile raspberrypi_spi *regs = bus->regs;
|
||||
|
||||
const unsigned char *sbuffer = bus->tx_buf;
|
||||
unsigned char *rbuffer;
|
||||
unsigned int size;
|
||||
unsigned int read_count, write_count;
|
||||
unsigned int data;
|
||||
|
||||
while (bus->msg_todo) {
|
||||
rbuffer = bus->rx_buf;
|
||||
size = bus->todo;
|
||||
|
||||
regs->spics = regs->spics | RPI_SPICS_CLEAR_RX | RPI_SPICS_CLEAR_TX
|
||||
| RPI_SPICS_TA;
|
||||
|
||||
read_count = 0;
|
||||
write_count = 0;
|
||||
|
||||
while (read_count < size || write_count < size) {
|
||||
if (write_count < size && regs->spics & RPI_SPICS_TXD) {
|
||||
if (sbuffer) {
|
||||
regs->spififo = *sbuffer++;
|
||||
} else {
|
||||
regs->spififo = 0;
|
||||
}
|
||||
|
||||
write_count++;
|
||||
}
|
||||
|
||||
if (read_count < size && regs->spics & RPI_SPICS_RXD) {
|
||||
data = regs->spififo;
|
||||
|
||||
if (rbuffer) {
|
||||
*rbuffer++ = data;
|
||||
}
|
||||
|
||||
read_count++;
|
||||
}
|
||||
}
|
||||
|
||||
while (!(regs->spics & RPI_SPICS_DONE)) {
|
||||
/*wait*/
|
||||
}
|
||||
regs->spics = (regs->spics & ~RPI_SPICS_TA);
|
||||
|
||||
bus->msg_todo--;
|
||||
|
||||
bus->msg++;
|
||||
bus->rx_buf = bus->msg->rx_buf;
|
||||
bus->tx_buf = bus->msg->tx_buf;
|
||||
bus->todo = bus->msg->len;
|
||||
}
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_transfer_msg(
|
||||
raspberrypi_spi_bus *bus
|
||||
)
|
||||
{
|
||||
volatile raspberrypi_spi *regs = bus->regs;
|
||||
uint32_t msg_todo = bus->msg_todo;
|
||||
const spi_ioc_transfer *msg = bus->msg;
|
||||
|
||||
if (msg_todo > 0) {
|
||||
if (
|
||||
msg->speed_hz != bus->base.speed_hz
|
||||
|| msg->mode != bus->base.mode
|
||||
|| msg->cs != bus->base.cs
|
||||
) {
|
||||
raspberrypi_spi_config(
|
||||
bus,
|
||||
regs,
|
||||
msg->speed_hz,
|
||||
msg->mode,
|
||||
msg->cs
|
||||
);
|
||||
}
|
||||
|
||||
bus->todo = msg->len;
|
||||
bus->rx_buf = msg->rx_buf;
|
||||
bus->tx_buf = msg->tx_buf;
|
||||
raspberrypi_spi_polling_tx_rx(bus);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static int raspberrypi_spi_transfer(
|
||||
spi_bus *base,
|
||||
const spi_ioc_transfer *msgs,
|
||||
uint32_t msg_count
|
||||
)
|
||||
{
|
||||
int rv = 0;
|
||||
raspberrypi_spi_bus *bus;
|
||||
bus = (raspberrypi_spi_bus *) base;
|
||||
|
||||
rv = raspberrypi_spi_check_msg(bus, msgs, msg_count);
|
||||
if (rv == 0) {
|
||||
bus->msg_todo = msg_count;
|
||||
bus->msg = msgs;
|
||||
#ifdef BSP_SPI_USE_INTERRUPTS
|
||||
bus->task_id = rtems_task_self();
|
||||
|
||||
raspberrypi_spi_start(bus);
|
||||
rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT);
|
||||
#else
|
||||
raspberrypi_spi_transfer_msg(bus);
|
||||
#endif
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
static void raspberrypi_spi_destroy(spi_bus *base)
|
||||
{
|
||||
raspberrypi_spi_bus *bus;
|
||||
bus = (raspberrypi_spi_bus *) base;
|
||||
|
||||
#ifdef BSP_SPI_USE_INTERRUPTS
|
||||
rtems_interrupt_handler_remove(
|
||||
bus->irq,
|
||||
raspberrypi_spi_interrupt,
|
||||
bus
|
||||
);
|
||||
#endif
|
||||
|
||||
spi_bus_destroy_and_free(&bus->base);
|
||||
}
|
||||
|
||||
static int raspberrypi_spi_setup(spi_bus *base)
|
||||
{
|
||||
raspberrypi_spi_bus *bus;
|
||||
uint32_t mode = base->mode;
|
||||
|
||||
bus = (raspberrypi_spi_bus *) base;
|
||||
|
||||
if (mode & SPI_LOOP) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return raspberrypi_spi_config(
|
||||
bus,
|
||||
bus->regs,
|
||||
bus->base.speed_hz,
|
||||
bus->base.mode,
|
||||
bus->base.cs
|
||||
);
|
||||
}
|
||||
|
||||
static rtems_status_code raspberrypi_spi_init_gpio(
|
||||
raspberrypi_spi_device device
|
||||
)
|
||||
{
|
||||
switch (device) {
|
||||
case raspberrypi_SPI0:
|
||||
raspberrypi_gpio_set_function(7, GPIO_AF0); /* CS1 */
|
||||
raspberrypi_gpio_set_pull(7, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(8, GPIO_AF0); /* CS0 */
|
||||
raspberrypi_gpio_set_pull(8, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(9, GPIO_AF0); /* MISO */
|
||||
raspberrypi_gpio_set_function(10, GPIO_AF0); /* MOSI */
|
||||
raspberrypi_gpio_set_function(11, GPIO_AF0); /* SCLK */
|
||||
break;
|
||||
case raspberrypi_SPI3:
|
||||
raspberrypi_gpio_set_function(24, GPIO_AF5);
|
||||
raspberrypi_gpio_set_pull(24, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(0, GPIO_AF3);
|
||||
raspberrypi_gpio_set_pull(0, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(1, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(2, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(3, GPIO_AF3);
|
||||
break;
|
||||
case raspberrypi_SPI4:
|
||||
raspberrypi_gpio_set_function(25, GPIO_AF5);
|
||||
raspberrypi_gpio_set_pull(25, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(4, GPIO_AF3);
|
||||
raspberrypi_gpio_set_pull(4, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(5, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(6, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(7, GPIO_AF3);
|
||||
break;
|
||||
case raspberrypi_SPI5:
|
||||
raspberrypi_gpio_set_function(26, GPIO_AF5);
|
||||
raspberrypi_gpio_set_pull(26, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(12, GPIO_AF3);
|
||||
raspberrypi_gpio_set_pull(12, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(13, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(14, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(15, GPIO_AF3);
|
||||
break;
|
||||
case raspberrypi_SPI6:
|
||||
raspberrypi_gpio_set_function(27, GPIO_AF5);
|
||||
raspberrypi_gpio_set_pull(27, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(18, GPIO_AF3);
|
||||
raspberrypi_gpio_set_pull(18, GPIO_PULL_NONE);
|
||||
raspberrypi_gpio_set_function(19, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(20, GPIO_AF3);
|
||||
raspberrypi_gpio_set_function(21, GPIO_AF3);
|
||||
break;
|
||||
default:
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
break;
|
||||
}
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
rtems_status_code raspberrypi_spi_init(raspberrypi_spi_device device)
|
||||
{
|
||||
raspberrypi_spi_bus *bus;
|
||||
int eno;
|
||||
volatile raspberrypi_spi *regs;
|
||||
const char *bus_path;
|
||||
|
||||
bus = (raspberrypi_spi_bus *) spi_bus_alloc_and_init(sizeof(*bus));
|
||||
if (bus == NULL) {
|
||||
return RTEMS_UNSATISFIED;
|
||||
}
|
||||
|
||||
switch (device) {
|
||||
case raspberrypi_SPI0:
|
||||
regs = (volatile raspberrypi_spi *) BCM2711_SPI0_BASE;
|
||||
bus_path = "/dev/spidev0";
|
||||
break;
|
||||
case raspberrypi_SPI3:
|
||||
regs = (volatile raspberrypi_spi *) BCM2711_SPI3_BASE;
|
||||
bus_path = "/dev/spidev3";
|
||||
break;
|
||||
case raspberrypi_SPI4:
|
||||
regs = (volatile raspberrypi_spi *) BCM2711_SPI4_BASE;
|
||||
bus_path = "/dev/spidev4";
|
||||
break;
|
||||
case raspberrypi_SPI5:
|
||||
regs = (volatile raspberrypi_spi *) BCM2711_SPI5_BASE;
|
||||
bus_path = "/dev/spidev5";
|
||||
break;
|
||||
case raspberrypi_SPI6:
|
||||
regs = (volatile raspberrypi_spi *) BCM2711_SPI6_BASE;
|
||||
bus_path = "/dev/spidev6";
|
||||
break;
|
||||
default:
|
||||
spi_bus_destroy_and_free(&bus->base);
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
break;
|
||||
}
|
||||
|
||||
bus->regs = regs;
|
||||
bus->num_cs = 2;
|
||||
|
||||
bus->base.transfer = raspberrypi_spi_transfer;
|
||||
bus->base.destroy = raspberrypi_spi_destroy;
|
||||
bus->base.setup = raspberrypi_spi_setup;
|
||||
bus->base.bits_per_word = 8;
|
||||
bus->base.max_speed_hz = 250000000;
|
||||
bus->base.cs = 0;
|
||||
#ifdef BSP_SPI_USE_INTERRUPTS
|
||||
bus->irq = BCM2711_IRQ_SPI;
|
||||
|
||||
eno = rtems_interrupt_handler_install(
|
||||
bus->irq,
|
||||
"SPI",
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
raspberrypi_spi_interrupt,
|
||||
bus
|
||||
);
|
||||
if (eno != RTEMS_SUCCESSFUL) {
|
||||
return EAGAIN;
|
||||
}
|
||||
#endif
|
||||
|
||||
eno = spi_bus_register(&bus->base, bus_path);
|
||||
if (eno != 0) {
|
||||
spi_bus_destroy_and_free(&bus->base);
|
||||
return RTEMS_UNSATISFIED;
|
||||
}
|
||||
|
||||
eno = raspberrypi_spi_init_gpio(device);
|
||||
if (eno != 0) {
|
||||
spi_bus_destroy_and_free(&bus->base);
|
||||
return RTEMS_INVALID_NUMBER;
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Reset Driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/watchdog.h>
|
||||
#include <bsp/bootcard.h>
|
||||
|
||||
void bsp_reset( rtems_fatal_source source, rtems_fatal_code code )
|
||||
{
|
||||
(void) source;
|
||||
(void) code;
|
||||
|
||||
/* Restart with enough of a delay to finish printing the exit spill. */
|
||||
raspberrypi_watchdog_start(20);
|
||||
|
||||
while (1) ;
|
||||
}
|
||||
@@ -1,56 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief BSP SMP Support
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/score/smpimpl.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
|
||||
#include <bsp/irq.h>
|
||||
|
||||
static uintptr_t *cpu_addr[] =
|
||||
{
|
||||
[0] = (uintptr_t *)0xd8,
|
||||
[1] = (uintptr_t *)0xe0,
|
||||
[2] = (uintptr_t *)0xe8,
|
||||
[3] = (uintptr_t *)0xf0
|
||||
};
|
||||
|
||||
bool _CPU_SMP_Start_processor( uint32_t cpu_index )
|
||||
{
|
||||
BCM2711_REG(cpu_addr[cpu_index]) = (uintptr_t)_start;
|
||||
_AARCH64_Send_event();
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
return true;
|
||||
}
|
||||
@@ -1,49 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief BSP Startup
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
rtems_cache_coherent_add_area(
|
||||
bsp_section_nocacheheap_begin,
|
||||
(uintptr_t) bsp_section_nocacheheap_size
|
||||
);
|
||||
}
|
||||
@@ -1,84 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief BSP Startup Hooks
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/start.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
#include <rtems/score/smpimpl.h>
|
||||
#include <rtems/score/smp.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#endif
|
||||
|
||||
#ifdef BSP_START_ENABLE_EL3_START_SUPPORT
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
#endif
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
|
||||
{
|
||||
#ifdef RTEMS_SMP
|
||||
uint32_t cpu_index_self = _SMP_Get_current_processor();
|
||||
if ( cpu_index_self != 0 ) {
|
||||
if (
|
||||
cpu_index_self >= rtems_configuration_get_maximum_processors()
|
||||
|| !_SMP_Should_start_processor( cpu_index_self )
|
||||
) {
|
||||
while ( true ) {
|
||||
_AARCH64_Wait_for_event();
|
||||
}
|
||||
}
|
||||
AArch64_start_set_vector_base();
|
||||
arm_gic_irq_initialize_secondary_cpu();
|
||||
rpi_setup_secondary_cpu_mmu_and_cache();
|
||||
bsp_interrupt_vector_enable( ARM_GIC_IRQ_SGI_0 );
|
||||
_SMP_Start_multitasking_on_secondary_processor(
|
||||
_Per_CPU_Get_by_index( cpu_index_self )
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
AArch64_start_set_vector_base();
|
||||
bsp_start_copy_sections();
|
||||
raspberrypi_4_setup_mmu_and_cache();
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -1,115 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Raspberrypi4
|
||||
*
|
||||
* @brief This source file contains the default MMU tables and setup.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Mohd Noor Aman
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
|
||||
BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
|
||||
raspberrypi_4_mmu_config_table[] = {
|
||||
AARCH64_MMU_DEFAULT_SECTIONS,
|
||||
|
||||
{ /* RPI peripheral address */
|
||||
.begin = (unsigned)RPI_PERIPHERAL_BASE,
|
||||
.end = (unsigned)RPI_PERIPHERAL_BASE + (unsigned)RPI_PERIPHERAL_SIZE,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
},
|
||||
|
||||
{ /* RPI ARM local registers */
|
||||
.begin = (unsigned)BCM2711_LOCAL_REGS_BASE,
|
||||
.end = (unsigned)BCM2711_LOCAL_REGS_BASE + (unsigned)BCM2711_LOCAL_REGS_SIZE,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
},
|
||||
|
||||
{ /* RPI firmware-owned addresses including spintables */
|
||||
.begin = (unsigned)0x0,
|
||||
.end = (unsigned)0x1000,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
},
|
||||
|
||||
{ /* RPI GIC Interface address */
|
||||
.begin = 0xFF800000U,
|
||||
.end = 0xFFA00000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
},
|
||||
|
||||
{ /* RPI genet address */
|
||||
.begin = (unsigned)0xFD580000,
|
||||
.end = (unsigned)0xFD580000 + (unsigned)0x10000,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}
|
||||
|
||||
};
|
||||
/*
|
||||
* Make weak and let the user override.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void
|
||||
raspberrypi_4_setup_mmu_and_cache( void ) __attribute__ ((weak));
|
||||
|
||||
BSP_START_TEXT_SECTION void
|
||||
raspberrypi_4_setup_mmu_and_cache( void )
|
||||
{
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
aarch64_mmu_setup();
|
||||
|
||||
aarch64_mmu_setup_translation_table(
|
||||
control,
|
||||
&raspberrypi_4_mmu_config_table[ 0 ],
|
||||
RTEMS_ARRAY_SIZE( raspberrypi_4_mmu_config_table )
|
||||
);
|
||||
|
||||
aarch64_mmu_enable( control );
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void )
|
||||
__attribute__ ( ( weak ) );
|
||||
|
||||
BSP_START_TEXT_SECTION void rpi_setup_secondary_cpu_mmu_and_cache( void )
|
||||
{
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
/* Perform basic MMU setup */
|
||||
aarch64_mmu_setup();
|
||||
|
||||
/* Use the existing root page table already configured by CPU0 */
|
||||
_AArch64_Write_ttbr0_el1( (uintptr_t) bsp_translation_table_base );
|
||||
|
||||
aarch64_mmu_enable( control );
|
||||
}
|
||||
@@ -1,73 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64RaspberryPi
|
||||
*
|
||||
* @brief Watchdog Driver
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Ning Yang
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/raspberrypi.h>
|
||||
#include <bsp/watchdog.h>
|
||||
|
||||
#define PM_WDOG BCM2835_REG(BCM2711_PM_WDOG)
|
||||
#define PM_RSTC BCM2835_REG(BCM2711_PM_RSTC)
|
||||
|
||||
uint32_t raspberrypi_watchdog_timeout;
|
||||
|
||||
void raspberrypi_watchdog_init()
|
||||
{
|
||||
raspberrypi_watchdog_timeout = 0;
|
||||
}
|
||||
|
||||
void raspberrypi_watchdog_start(uint32_t timeout_ms)
|
||||
{
|
||||
raspberrypi_watchdog_timeout = timeout_ms;
|
||||
|
||||
PM_WDOG = BCM2711_PM_PASSWD_MAGIC |
|
||||
((timeout_ms * 65536 / 1000) & BCM2711_PM_WDOG_MASK);
|
||||
|
||||
PM_RSTC &= BCM2711_PM_RSTC_WRCFG_CLR;
|
||||
PM_RSTC = (BCM2711_PM_PASSWD_MAGIC | BCM2711_PM_RSTC_WRCFG_FULL);
|
||||
}
|
||||
|
||||
void raspberrypi_watchdog_stop()
|
||||
{
|
||||
PM_RSTC = BCM2711_PM_PASSWD_MAGIC | BCM2711_PM_RSTC_RESET;
|
||||
}
|
||||
|
||||
void raspberrypi_watchdog_reload()
|
||||
{
|
||||
raspberrypi_watchdog_start(raspberrypi_watchdog_timeout);
|
||||
}
|
||||
|
||||
uint32_t raspberrypi_watchdog_get_remaining_time()
|
||||
{
|
||||
return (PM_WDOG & BCM2711_PM_WDOG_MASK)*1000/65536;
|
||||
}
|
||||
415
bsps/aarch64/shared/cache/cache.c
vendored
415
bsps/aarch64/shared/cache/cache.c
vendored
@@ -1,415 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief AArch64 cache defines and implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems.h>
|
||||
#include <bsp.h>
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
|
||||
#define CPU_DATA_CACHE_ALIGNMENT 64
|
||||
|
||||
#define CPU_INSTRUCTION_CACHE_ALIGNMENT 64
|
||||
|
||||
#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
|
||||
|
||||
#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
|
||||
|
||||
#define AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ( (size_t) 64 )
|
||||
#define AARCH64_CACHE_PREPARE_MVA(mva) (const void *) \
|
||||
RTEMS_ALIGN_DOWN ( (size_t) mva, AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT )
|
||||
|
||||
static inline
|
||||
void AArch64_data_cache_clean_and_invalidate_line(const void *d_addr)
|
||||
{
|
||||
d_addr = AARCH64_CACHE_PREPARE_MVA(d_addr);
|
||||
|
||||
__asm__ volatile (
|
||||
"dc civac, %[d_addr]"
|
||||
:
|
||||
: [d_addr] "r" (d_addr)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void
|
||||
_CPU_cache_flush_data_range(
|
||||
const void *d_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
if ( n_bytes != 0 ) {
|
||||
size_t adx = (size_t) AARCH64_CACHE_PREPARE_MVA ( d_addr );
|
||||
const size_t ADDR_LAST = (size_t) d_addr + n_bytes - 1;
|
||||
|
||||
for (; adx <= ADDR_LAST; adx += AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ) {
|
||||
/* Store and invalidate the Data cache line */
|
||||
AArch64_data_cache_clean_and_invalidate_line( (void*)adx );
|
||||
}
|
||||
/* Wait for L1 store to complete */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
}
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
}
|
||||
|
||||
static inline void AArch64_data_cache_invalidate_line(const void *d_addr)
|
||||
{
|
||||
d_addr = AARCH64_CACHE_PREPARE_MVA(d_addr);
|
||||
|
||||
__asm__ volatile (
|
||||
"dc ivac, %[d_addr]"
|
||||
:
|
||||
: [d_addr] "r" (d_addr)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void
|
||||
_CPU_cache_invalidate_data_range(
|
||||
const void *d_addr,
|
||||
size_t n_bytes
|
||||
)
|
||||
{
|
||||
if ( n_bytes != 0 ) {
|
||||
size_t adx = (size_t) AARCH64_CACHE_PREPARE_MVA ( d_addr );
|
||||
const size_t end = (size_t)d_addr + n_bytes -1;
|
||||
|
||||
/* Back starting address up to start of a line and invalidate until end */
|
||||
for (;
|
||||
adx <= end;
|
||||
adx += AARCH64_CACHE_L1_CPU_DATA_ALIGNMENT ) {
|
||||
/* Invalidate the Instruction cache line */
|
||||
AArch64_data_cache_invalidate_line( (void*)adx );
|
||||
}
|
||||
/* Wait for L1 invalidate to complete */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
}
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_freeze_data(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_unfreeze_data(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void AArch64_instruction_cache_invalidate_line(const void *i_addr)
|
||||
{
|
||||
/* __builtin___clear_cache is explicitly only for instruction cacche */
|
||||
__builtin___clear_cache((void *)i_addr, ((char *)i_addr) + sizeof(void*) - 1);
|
||||
}
|
||||
|
||||
static inline void
|
||||
_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
|
||||
{
|
||||
if ( n_bytes != 0 ) {
|
||||
__builtin___clear_cache((void *)i_addr, ((char *)i_addr) + n_bytes - 1);
|
||||
}
|
||||
_AARCH64_Instruction_synchronization_barrier();
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_freeze_instruction(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_unfreeze_instruction(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_get_ccsidr_for_level(
|
||||
uint64_t level, bool instruction
|
||||
)
|
||||
{
|
||||
uint64_t csselr = AARCH64_CSSELR_EL1_LEVEL(level - 1);
|
||||
|
||||
csselr |= instruction ? AARCH64_CSSELR_EL1_IND : 0;
|
||||
|
||||
_AArch64_Write_csselr_el1(csselr);
|
||||
_AARCH64_Instruction_synchronization_barrier();
|
||||
return _AArch64_Read_ccsidr_el1();
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
AArch64_ccsidr_get_line_power(uint64_t ccsidr)
|
||||
{
|
||||
return AARCH64_CCSIDR_EL1_LINESIZE_GET(ccsidr) + 4;
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
AArch64_ccsidr_get_associativity(uint64_t ccsidr)
|
||||
{
|
||||
return AARCH64_CCSIDR_EL1_ASSOCIATIVITY_GET_0(ccsidr) + 1;
|
||||
}
|
||||
|
||||
static inline uint64_t
|
||||
AArch64_ccsidr_get_num_sets(uint64_t ccsidr)
|
||||
{
|
||||
return AARCH64_CCSIDR_EL1_NUMSETS_GET_0(ccsidr) + 1;
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
AArch64_data_cache_clean_and_invalidate_level(uint64_t level)
|
||||
{
|
||||
uint64_t ccsidr;
|
||||
uint64_t line_power;
|
||||
uint64_t associativity;
|
||||
uint64_t way;
|
||||
uint64_t way_shift;
|
||||
|
||||
ccsidr = AArch64_get_ccsidr_for_level(level, false);
|
||||
|
||||
line_power = AArch64_ccsidr_get_line_power(ccsidr);
|
||||
associativity = AArch64_ccsidr_get_associativity(ccsidr);
|
||||
way_shift = __builtin_clz(associativity - 1);
|
||||
|
||||
for (way = 0; way < associativity; ++way) {
|
||||
uint64_t num_sets = AArch64_ccsidr_get_num_sets(ccsidr);
|
||||
uint64_t set;
|
||||
|
||||
for (set = 0; set < num_sets; ++set) {
|
||||
uint64_t set_and_way = (way << way_shift)
|
||||
| (set << line_power)
|
||||
| ((level - 1) << 1);
|
||||
|
||||
__asm__ volatile (
|
||||
"dc cisw, %[set_and_way]"
|
||||
:
|
||||
: [set_and_way] "r" (set_and_way)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline
|
||||
uint64_t AArch64_clidr_get_cache_type(uint64_t clidr, uint64_t level)
|
||||
{
|
||||
return (clidr >> (3 * level)) & 0x7;
|
||||
}
|
||||
|
||||
static inline uint64_t AArch64_clidr_get_level_of_coherency(uint64_t clidr)
|
||||
{
|
||||
return AARCH64_CLIDR_EL1_LOC_GET(clidr);
|
||||
}
|
||||
|
||||
static inline void AArch64_data_cache_clean_and_invalidate_all_levels(void)
|
||||
{
|
||||
uint64_t clidr = _AArch64_Read_clidr_el1();
|
||||
uint64_t loc = AArch64_clidr_get_level_of_coherency(clidr);
|
||||
uint64_t level = 0;
|
||||
|
||||
for (level = 1; level <= loc; ++level) {
|
||||
/* Assume that all levels have a data cache */
|
||||
AArch64_data_cache_clean_and_invalidate_level(level);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_flush_entire_data(void)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
AArch64_data_cache_clean_and_invalidate_all_levels();
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
}
|
||||
|
||||
static inline void AArch64_cache_invalidate_level(uint64_t level)
|
||||
{
|
||||
uint64_t ccsidr;
|
||||
uint64_t line_power;
|
||||
uint64_t associativity;
|
||||
uint64_t way;
|
||||
uint64_t way_shift;
|
||||
|
||||
ccsidr = AArch64_get_ccsidr_for_level(level, false);
|
||||
|
||||
line_power = AArch64_ccsidr_get_line_power(ccsidr);
|
||||
associativity = AArch64_ccsidr_get_associativity(ccsidr);
|
||||
way_shift = __builtin_clz(associativity - 1);
|
||||
|
||||
for (way = 0; way < associativity; ++way) {
|
||||
uint64_t num_sets = AArch64_ccsidr_get_num_sets(ccsidr);
|
||||
uint64_t set;
|
||||
|
||||
for (set = 0; set < num_sets; ++set) {
|
||||
uint64_t set_and_way = (way << way_shift)
|
||||
| (set << line_power)
|
||||
| ((level - 1) << 1);
|
||||
|
||||
__asm__ volatile (
|
||||
"dc isw, %[set_and_way]"
|
||||
:
|
||||
: [set_and_way] "r" (set_and_way)
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline void AArch64_data_cache_invalidate_all_levels(void)
|
||||
{
|
||||
uint64_t clidr = _AArch64_Read_clidr_el1();
|
||||
uint64_t loc = AArch64_clidr_get_level_of_coherency(clidr);
|
||||
uint64_t level = 0;
|
||||
|
||||
for (level = 1; level <= loc; ++level) {
|
||||
/* Assume that all levels have a data cache */
|
||||
AArch64_cache_invalidate_level(level);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_entire_data(void)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
AArch64_data_cache_invalidate_all_levels();
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_enable_data(void)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
uint64_t sctlr;
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
sctlr = _AArch64_Read_sctlr_el1();
|
||||
sctlr |= AARCH64_SCTLR_EL1_C;
|
||||
_AArch64_Write_sctlr_el1(sctlr);
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
}
|
||||
|
||||
static RTEMS_NO_RETURN inline void _CPU_cache_disable_data(void)
|
||||
{
|
||||
_Internal_error( INTERNAL_ERROR_CANNOT_DISABLE_DATA_CACHE );
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_invalidate_entire_instruction(void)
|
||||
{
|
||||
/*
|
||||
* There is no way to manage branch prediction in AArch64. See D4.4.12 in
|
||||
* the ARM Architecture Reference Manual, ARMv8, for ARMv8-A architecture
|
||||
* profile (ARM DDI 0487D.a).
|
||||
*/
|
||||
|
||||
__asm__ volatile (
|
||||
#ifdef RTEMS_SMP
|
||||
/*
|
||||
* Invalidate all instruction caches up to
|
||||
* Point of Unification, Inner Shareable.
|
||||
*/
|
||||
"ic ialluis\n"
|
||||
#else
|
||||
/* Invalidate all instruction caches up to Point of Unification */
|
||||
"ic iallu\n"
|
||||
#endif
|
||||
"isb"
|
||||
:
|
||||
:
|
||||
: "memory"
|
||||
);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_enable_instruction(void)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
uint64_t sctlr;
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
sctlr = _AArch64_Read_sctlr_el1();
|
||||
sctlr |= AARCH64_SCTLR_EL1_I;
|
||||
_AArch64_Write_sctlr_el1(sctlr);
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
}
|
||||
|
||||
static inline void _CPU_cache_disable_instruction(void)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
uint64_t sctlr;
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
sctlr = _AArch64_Read_sctlr_el1();
|
||||
sctlr &= ~AARCH64_SCTLR_EL1_I;
|
||||
_AArch64_Write_sctlr_el1(sctlr);
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
}
|
||||
|
||||
static inline size_t AArch64_get_cache_size(
|
||||
uint64_t level,
|
||||
bool instruction
|
||||
)
|
||||
{
|
||||
rtems_interrupt_level isr_level;
|
||||
uint64_t clidr;
|
||||
uint64_t loc;
|
||||
uint64_t ccsidr;
|
||||
|
||||
clidr = _AArch64_Read_clidr_el1();
|
||||
loc = AArch64_clidr_get_level_of_coherency(clidr);
|
||||
|
||||
if (level > loc) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
rtems_interrupt_local_disable(isr_level);
|
||||
ccsidr = AArch64_get_ccsidr_for_level(level, instruction);
|
||||
rtems_interrupt_local_enable(isr_level);
|
||||
|
||||
return (1U << (AArch64_ccsidr_get_line_power(ccsidr)+4))
|
||||
* AArch64_ccsidr_get_associativity(ccsidr)
|
||||
* AArch64_ccsidr_get_num_sets(ccsidr);
|
||||
}
|
||||
|
||||
static inline size_t _CPU_cache_get_data_cache_size(uint64_t level)
|
||||
{
|
||||
return AArch64_get_cache_size(level, false);
|
||||
}
|
||||
|
||||
static inline size_t _CPU_cache_get_instruction_cache_size(uint64_t level)
|
||||
{
|
||||
return AArch64_get_cache_size(level, true);
|
||||
}
|
||||
|
||||
#include "../../shared/cache/cacheimpl.h"
|
||||
@@ -1,116 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief AArch64-specific ARM GPT system register accessors.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dev/clock/arm-generic-timer.h>
|
||||
#include <bsp/irq.h>
|
||||
|
||||
uint64_t arm_gt_clock_get_compare_value(void)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile (
|
||||
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
|
||||
"mrs %[val], cntv_cval_el0"
|
||||
#elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
|
||||
"mrs %[val], cntps_cval_el1"
|
||||
#else
|
||||
"mrs %[val], cntp_cval_el0"
|
||||
#endif
|
||||
: [val] "=&r" (val)
|
||||
);
|
||||
return val;
|
||||
}
|
||||
|
||||
void arm_gt_clock_set_compare_value(uint64_t cval)
|
||||
{
|
||||
__asm__ volatile (
|
||||
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
|
||||
"msr cntv_cval_el0, %[cval]"
|
||||
#elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
|
||||
"msr cntps_cval_el1, %[cval]"
|
||||
#else
|
||||
"msr cntp_cval_el0, %[cval]"
|
||||
#endif
|
||||
:
|
||||
: [cval] "r" (cval)
|
||||
);
|
||||
}
|
||||
|
||||
uint64_t arm_gt_clock_get_count(void)
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile (
|
||||
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
|
||||
"mrs %[val], cntvct_el0"
|
||||
#else
|
||||
"mrs %[val], cntpct_el0"
|
||||
#endif
|
||||
: [val] "=&r" (val)
|
||||
);
|
||||
return val;
|
||||
}
|
||||
|
||||
void arm_gt_clock_set_control(uint32_t ctl)
|
||||
{
|
||||
__asm__ volatile (
|
||||
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
|
||||
"msr cntv_ctl_el0, %[ctl]"
|
||||
#elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
|
||||
"msr cntps_ctl_el1, %[ctl]"
|
||||
#else
|
||||
"msr cntp_ctl_el0, %[ctl]"
|
||||
#endif
|
||||
:
|
||||
: [ctl] "r" (ctl)
|
||||
);
|
||||
}
|
||||
|
||||
void arm_generic_timer_get_config( uint32_t *frequency, uint32_t *irq )
|
||||
{
|
||||
uint64_t val;
|
||||
__asm__ volatile (
|
||||
"mrs %[val], cntfrq_el0"
|
||||
: [val] "=&r" (val)
|
||||
);
|
||||
*frequency = val;
|
||||
|
||||
#ifdef AARCH64_GENERIC_TIMER_USE_VIRTUAL
|
||||
*irq = BSP_TIMER_VIRT_PPI;
|
||||
#elif defined(AARCH64_GENERIC_TIMER_USE_PHYSICAL_SECURE)
|
||||
*irq = BSP_TIMER_PHYS_S_PPI;
|
||||
#else
|
||||
*irq = BSP_TIMER_PHYS_NS_PPI;
|
||||
#endif
|
||||
}
|
||||
@@ -1,23 +0,0 @@
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSImplDoxygen
|
||||
*
|
||||
* @brief This header file defines BSP-specific groups.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTEMSBSPsAArch64 AArch64
|
||||
*
|
||||
* @ingroup RTEMSBSPs
|
||||
*
|
||||
* @brief This group contains AArch64 Board Support Packages.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup RTEMSBSPsAArch64Shared Shared
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @brief This group contains support shared by AArch64 Board Support Packages.
|
||||
*/
|
||||
@@ -1,319 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup aarch64_start
|
||||
*
|
||||
* @brief AArch64 MMU configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
|
||||
#include <bsp/fatal.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/start.h>
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
#include <rtems/score/assert.h>
|
||||
|
||||
aarch64_mmu_control aarch64_mmu_instance = {
|
||||
.ttb = (uint64_t *) bsp_translation_table_base,
|
||||
|
||||
/* One page table is used for the initial setup at the base */
|
||||
.used_page_tables = 1
|
||||
};
|
||||
|
||||
/* AArch64 uses levels 0, 1, 2, and 3 */
|
||||
#define MMU_MAX_SUBTABLE_PAGE_BITS ( 3 * MMU_BITS_PER_LEVEL + MMU_PAGE_BITS )
|
||||
|
||||
/* setup straight mapped block entries */
|
||||
BSP_START_TEXT_SECTION static inline void aarch64_mmu_page_table_set_blocks(
|
||||
uint64_t *page_table,
|
||||
uint64_t base,
|
||||
uint32_t bits_offset,
|
||||
uint64_t default_attr
|
||||
)
|
||||
{
|
||||
uint64_t page_flag = 0;
|
||||
|
||||
if ( bits_offset == MMU_PAGE_BITS ) {
|
||||
page_flag = MMU_DESC_TYPE_PAGE;
|
||||
}
|
||||
|
||||
for ( uint64_t i = 0; i < ( 1 << MMU_BITS_PER_LEVEL ); i++ ) {
|
||||
page_table[i] = base | ( i << bits_offset );
|
||||
page_table[i] |= default_attr | page_flag;
|
||||
}
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline uint64_t *
|
||||
aarch64_mmu_page_table_alloc( aarch64_mmu_control *control )
|
||||
{
|
||||
size_t used_page_tables = control->used_page_tables;
|
||||
|
||||
if ( used_page_tables >= AARCH64_MMU_TRANSLATION_TABLE_PAGES ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
control->used_page_tables = used_page_tables + 1;
|
||||
return (uint64_t *)
|
||||
( (uintptr_t) control->ttb + ( used_page_tables << MMU_PAGE_BITS ) );
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline uintptr_t aarch64_mmu_get_index(
|
||||
uintptr_t root_address,
|
||||
uintptr_t vaddr,
|
||||
uint32_t shift
|
||||
)
|
||||
{
|
||||
uintptr_t mask = ( 1 << ( MMU_BITS_PER_LEVEL + 1 ) ) - 1;
|
||||
|
||||
return ( ( vaddr - root_address ) >> shift ) & mask;
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static uint64_t *
|
||||
aarch64_mmu_get_sub_table(
|
||||
aarch64_mmu_control *control,
|
||||
uint64_t *page_table_entry,
|
||||
uintptr_t physical_root_address,
|
||||
uint32_t shift
|
||||
)
|
||||
{
|
||||
/* check if the index already has a page table */
|
||||
if ( ( *page_table_entry & MMU_DESC_TYPE_TABLE ) == MMU_DESC_TYPE_TABLE ) {
|
||||
/* extract page table address */
|
||||
uint64_t table_pointer = *page_table_entry & MMU_DESC_PAGE_TABLE_MASK;
|
||||
/* This cast should be safe since the address was inserted in this mode */
|
||||
return (uint64_t *) (uintptr_t) table_pointer;
|
||||
}
|
||||
|
||||
/* allocate new page table and set block */
|
||||
uint64_t *sub_table = aarch64_mmu_page_table_alloc( control );
|
||||
|
||||
if ( sub_table == NULL ) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
aarch64_mmu_page_table_set_blocks(
|
||||
sub_table,
|
||||
physical_root_address,
|
||||
shift - MMU_BITS_PER_LEVEL,
|
||||
*page_table_entry & ~MMU_DESC_PAGE_TABLE_MASK
|
||||
);
|
||||
*page_table_entry = (uintptr_t) sub_table;
|
||||
*page_table_entry |= MMU_DESC_TYPE_TABLE | MMU_DESC_VALID;
|
||||
|
||||
return sub_table;
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION static inline rtems_status_code aarch64_mmu_map_block(
|
||||
aarch64_mmu_control *control,
|
||||
uint64_t *page_table,
|
||||
uint64_t root_address,
|
||||
uint64_t addr,
|
||||
uint64_t size,
|
||||
int8_t level,
|
||||
uint64_t flags
|
||||
)
|
||||
{
|
||||
uint32_t shift = ( 2 - level ) * MMU_BITS_PER_LEVEL + MMU_PAGE_BITS;
|
||||
uint64_t granularity = 1LLU << shift;
|
||||
|
||||
do {
|
||||
uintptr_t index = aarch64_mmu_get_index( root_address, addr, shift );
|
||||
uint64_t block_bottom = RTEMS_ALIGN_DOWN( addr, granularity );
|
||||
uint64_t chunk_size = granularity;
|
||||
|
||||
/* check for perfect block match */
|
||||
if ( block_bottom == addr ) {
|
||||
if ( size >= chunk_size ) {
|
||||
/* level -1 can't contain block descriptors, fall through to subtable */
|
||||
if ( level != -1 ) {
|
||||
uint64_t page_flag = 0;
|
||||
|
||||
if ( level == 2 ) {
|
||||
page_flag = MMU_DESC_TYPE_PAGE;
|
||||
}
|
||||
|
||||
/* when page_flag is set the last level must be a page descriptor */
|
||||
if ( page_flag || ( page_table[index] & MMU_DESC_TYPE_TABLE ) != MMU_DESC_TYPE_TABLE ) {
|
||||
/* no sub-table, apply block properties */
|
||||
page_table[index] = addr | flags | page_flag;
|
||||
size -= chunk_size;
|
||||
addr += chunk_size;
|
||||
continue;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Block starts on a boundary, but is short.
|
||||
*
|
||||
* The size is >= MMU_PAGE_SIZE since
|
||||
* aarch64_mmu_set_translation_table_entries() aligns the memory region
|
||||
* to page boundaries. The minimum chunk_size is MMU_PAGE_SIZE.
|
||||
*/
|
||||
_Assert( level < 2 );
|
||||
chunk_size = size;
|
||||
}
|
||||
} else {
|
||||
uintptr_t block_top = RTEMS_ALIGN_UP( addr, granularity );
|
||||
chunk_size = block_top - addr;
|
||||
|
||||
if ( chunk_size > size ) {
|
||||
chunk_size = size;
|
||||
}
|
||||
}
|
||||
|
||||
/* Deal with any subtable modification */
|
||||
uint64_t new_root_address = root_address + index * granularity;
|
||||
rtems_status_code sc;
|
||||
|
||||
uint64_t *sub_table = aarch64_mmu_get_sub_table(
|
||||
control,
|
||||
&page_table[index],
|
||||
new_root_address,
|
||||
shift
|
||||
);
|
||||
|
||||
if ( sub_table == NULL ) {
|
||||
return RTEMS_TOO_MANY;
|
||||
}
|
||||
|
||||
sc = aarch64_mmu_map_block(
|
||||
control,
|
||||
sub_table,
|
||||
new_root_address,
|
||||
addr,
|
||||
chunk_size,
|
||||
level + 1,
|
||||
flags
|
||||
);
|
||||
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
size -= chunk_size;
|
||||
addr += chunk_size;
|
||||
} while ( size > 0 );
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
/* Get the maximum number of bits supported by this hardware */
|
||||
BSP_START_TEXT_SECTION static inline uint64_t
|
||||
aarch64_mmu_get_cpu_pa_bits( void )
|
||||
{
|
||||
#ifdef AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS
|
||||
return AARCH64_MMU_PHYSICAL_ADDRESS_RANGE_BITS;
|
||||
#else
|
||||
uint64_t id_reg = _AArch64_Read_id_aa64mmfr0_el1();
|
||||
|
||||
switch ( AARCH64_ID_AA64MMFR0_EL1_PARANGE_GET( id_reg ) ) {
|
||||
case 0:
|
||||
return 32;
|
||||
case 1:
|
||||
return 36;
|
||||
case 2:
|
||||
return 40;
|
||||
case 3:
|
||||
return 42;
|
||||
case 4:
|
||||
return 44;
|
||||
case 5:
|
||||
return 48;
|
||||
case 6:
|
||||
return 52;
|
||||
default:
|
||||
return 48;
|
||||
}
|
||||
return 48;
|
||||
#endif
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION rtems_status_code
|
||||
aarch64_mmu_set_translation_table_entries(
|
||||
aarch64_mmu_control *control,
|
||||
const aarch64_mmu_config_entry *config
|
||||
)
|
||||
{
|
||||
uint64_t max_mappable = 1LLU << aarch64_mmu_get_cpu_pa_bits();
|
||||
/* Align to page boundaries */
|
||||
uint64_t begin = RTEMS_ALIGN_DOWN( config->begin, MMU_PAGE_SIZE );
|
||||
uint64_t end = RTEMS_ALIGN_UP( (uint64_t) config->end, MMU_PAGE_SIZE );
|
||||
uint64_t size = end - begin;
|
||||
|
||||
if ( config->begin == config->end ) {
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
if ( begin >= max_mappable ) {
|
||||
return RTEMS_INVALID_ADDRESS;
|
||||
}
|
||||
|
||||
if ( size > max_mappable - begin ) {
|
||||
return RTEMS_INVALID_SIZE;
|
||||
}
|
||||
|
||||
return aarch64_mmu_map_block(
|
||||
control,
|
||||
control->ttb,
|
||||
0x0,
|
||||
begin,
|
||||
size,
|
||||
-1,
|
||||
config->flags
|
||||
);
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION void aarch64_mmu_setup_translation_table(
|
||||
aarch64_mmu_control *control,
|
||||
const aarch64_mmu_config_entry *config_table,
|
||||
size_t config_count
|
||||
)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
aarch64_mmu_page_table_set_blocks(
|
||||
control->ttb,
|
||||
(uintptr_t) NULL,
|
||||
MMU_MAX_SUBTABLE_PAGE_BITS,
|
||||
0
|
||||
);
|
||||
|
||||
/* Configure entries required for each memory section */
|
||||
for ( i = 0; i < config_count; ++i ) {
|
||||
rtems_status_code sc;
|
||||
|
||||
sc = aarch64_mmu_set_translation_table_entries( control, &config_table[i] );
|
||||
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
bsp_fatal( AARCH64_FATAL_MMU_CANNOT_MAP_BLOCK );
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,53 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief AArch64 MMU dummy implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
/*
|
||||
* This must have a non-header implementation because it is used by libdebugger.
|
||||
*/
|
||||
rtems_status_code aarch64_mmu_map(
|
||||
uintptr_t addr,
|
||||
uint64_t size,
|
||||
uint64_t flags
|
||||
)
|
||||
{
|
||||
(void) addr;
|
||||
(void) size;
|
||||
(void) flags;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,78 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief AArch64 MMU implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <rtems/score/cpu.h>
|
||||
|
||||
/*
|
||||
* This must have a non-header implementation because it is used by libdebugger.
|
||||
*/
|
||||
rtems_status_code aarch64_mmu_map(
|
||||
uintptr_t addr,
|
||||
uint64_t size,
|
||||
uint64_t flags
|
||||
)
|
||||
{
|
||||
aarch64_mmu_config_entry config = {
|
||||
.begin = addr,
|
||||
.end = addr + size,
|
||||
.flags = flags
|
||||
};
|
||||
rtems_status_code sc;
|
||||
ISR_Level level;
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
/*
|
||||
* Disable interrupts so they don't run while the MMU tables are being
|
||||
* modified.
|
||||
*/
|
||||
_ISR_Local_disable( level );
|
||||
|
||||
sc = aarch64_mmu_set_translation_table_entries(
|
||||
control,
|
||||
&config
|
||||
);
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
__asm__ volatile(
|
||||
"tlbi vmalle1\n"
|
||||
);
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
_AARCH64_Instruction_synchronization_barrier();
|
||||
|
||||
_ISR_Local_enable( level );
|
||||
|
||||
return sc;
|
||||
}
|
||||
@@ -1,91 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief SMP startup and interop code.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/score/smpimpl.h>
|
||||
|
||||
#include <bsp/irq.h>
|
||||
|
||||
static void bsp_inter_processor_interrupt( void *arg )
|
||||
{
|
||||
(void) arg;
|
||||
|
||||
_SMP_Inter_processor_interrupt_handler( _Per_CPU_Get() );
|
||||
}
|
||||
|
||||
uint32_t _CPU_SMP_Initialize( void )
|
||||
{
|
||||
return arm_gic_irq_processor_count();
|
||||
}
|
||||
|
||||
static rtems_interrupt_entry aarch64_ipi_entry;
|
||||
|
||||
void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
|
||||
{
|
||||
(void) cpu_count;
|
||||
|
||||
rtems_status_code sc;
|
||||
|
||||
rtems_interrupt_entry_initialize(
|
||||
&aarch64_ipi_entry,
|
||||
bsp_inter_processor_interrupt,
|
||||
NULL,
|
||||
"IPI"
|
||||
);
|
||||
sc = rtems_interrupt_entry_install(
|
||||
ARM_GIC_IRQ_SGI_0,
|
||||
RTEMS_INTERRUPT_UNIQUE,
|
||||
&aarch64_ipi_entry
|
||||
);
|
||||
_Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
|
||||
}
|
||||
|
||||
void _CPU_SMP_Prepare_start_multitasking( void )
|
||||
{
|
||||
/* Do nothing */
|
||||
}
|
||||
|
||||
void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
|
||||
{
|
||||
arm_gic_trigger_sgi(
|
||||
ARM_GIC_IRQ_SGI_0,
|
||||
1U << target_processor_index
|
||||
);
|
||||
}
|
||||
|
||||
uint32_t _CPU_SMP_Get_current_processor( void )
|
||||
{
|
||||
return _Per_CPU_Get_index( _CPU_Get_current_per_CPU_control() );
|
||||
}
|
||||
@@ -1,443 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup bsp_linker
|
||||
*
|
||||
* @brief Linker command base file.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
ENTRY (_start)
|
||||
STARTUP (start.o)
|
||||
|
||||
/*
|
||||
* Global symbols that may be defined externally
|
||||
*/
|
||||
|
||||
bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 16;
|
||||
|
||||
bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 0;
|
||||
bsp_stack_exception_size = ALIGN (bsp_stack_exception_size, bsp_stack_align);
|
||||
|
||||
bsp_vector_table_size = DEFINED (bsp_vector_table_size) ? bsp_vector_table_size : 64;
|
||||
|
||||
bsp_section_xbarrier_align = DEFINED (bsp_section_xbarrier_align) ? bsp_section_xbarrier_align : 1;
|
||||
bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1;
|
||||
bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1;
|
||||
|
||||
bsp_stack_hyp_size = DEFINED (bsp_stack_hyp_size) ? bsp_stack_hyp_size : 0;
|
||||
bsp_stack_hyp_size = ALIGN (bsp_stack_hyp_size, bsp_stack_align);
|
||||
|
||||
MEMORY {
|
||||
UNEXPECTED_SECTIONS : ORIGIN = 0xffffffffffffffff, LENGTH = 0
|
||||
}
|
||||
|
||||
SECTIONS {
|
||||
.start : ALIGN_WITH_INPUT {
|
||||
bsp_section_start_begin = .;
|
||||
KEEP (*(.bsp_start_text))
|
||||
KEEP (*(.bsp_start_data))
|
||||
bsp_section_start_end = .;
|
||||
} > REGION_START AT > REGION_START
|
||||
bsp_section_start_size = bsp_section_start_end - bsp_section_start_begin;
|
||||
|
||||
.xbarrier : ALIGN_WITH_INPUT {
|
||||
. = ALIGN (bsp_section_xbarrier_align);
|
||||
} > REGION_VECTOR AT > REGION_VECTOR
|
||||
|
||||
.text : ALIGN_WITH_INPUT {
|
||||
bsp_section_text_begin = .;
|
||||
*(.text.unlikely .text.*_unlikely)
|
||||
*(.text .stub .text.* .gnu.linkonce.t.*)
|
||||
/* .gnu.warning sections are handled specially by elf32.em. */
|
||||
*(.gnu.warning)
|
||||
*(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx)
|
||||
} > REGION_TEXT AT > REGION_TEXT_LOAD
|
||||
.init : ALIGN_WITH_INPUT {
|
||||
KEEP (*(.init))
|
||||
} > REGION_TEXT AT > REGION_TEXT_LOAD
|
||||
.fini : ALIGN_WITH_INPUT {
|
||||
KEEP (*(.fini))
|
||||
bsp_section_text_end = .;
|
||||
} > REGION_TEXT AT > REGION_TEXT_LOAD
|
||||
bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin;
|
||||
bsp_section_text_load_begin = LOADADDR (.text);
|
||||
bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size;
|
||||
|
||||
.robarrier : ALIGN_WITH_INPUT {
|
||||
. = ALIGN (bsp_section_robarrier_align);
|
||||
} > REGION_RODATA AT > REGION_RODATA
|
||||
|
||||
.rodata : ALIGN_WITH_INPUT {
|
||||
bsp_section_rodata_begin = .;
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rodata1 : ALIGN_WITH_INPUT {
|
||||
*(.rodata1)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.ARM.extab : ALIGN_WITH_INPUT {
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.ARM.exidx : ALIGN_WITH_INPUT {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.eh_frame : ALIGN_WITH_INPUT {
|
||||
KEEP (*(.eh_frame))
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.gcc_except_table : ALIGN_WITH_INPUT {
|
||||
*(.gcc_except_table .gcc_except_table.*)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.tdata : ALIGN_WITH_INPUT {
|
||||
_TLS_Data_begin = .;
|
||||
*(.tdata .tdata.* .gnu.linkonce.td.*)
|
||||
_TLS_Data_end = .;
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.tbss : ALIGN_WITH_INPUT {
|
||||
_TLS_BSS_begin = .;
|
||||
*(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
|
||||
_TLS_BSS_end = .;
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
_TLS_Data_size = _TLS_Data_end - _TLS_Data_begin;
|
||||
_TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin;
|
||||
_TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin;
|
||||
_TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin;
|
||||
_TLS_Size = _TLS_BSS_end - _TLS_Data_begin;
|
||||
_TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
|
||||
.preinit_array : ALIGN_WITH_INPUT {
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.init_array : ALIGN_WITH_INPUT {
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.fini_array : ALIGN_WITH_INPUT {
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.data.rel.ro : ALIGN_WITH_INPUT {
|
||||
*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*)
|
||||
*(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.jcr : ALIGN_WITH_INPUT {
|
||||
KEEP (*(.jcr))
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.interp : ALIGN_WITH_INPUT {
|
||||
*(.interp)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.note.gnu.build-id : ALIGN_WITH_INPUT {
|
||||
*(.note.gnu.build-id)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.hash : ALIGN_WITH_INPUT {
|
||||
*(.hash)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.gnu.hash : ALIGN_WITH_INPUT {
|
||||
*(.gnu.hash)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.dynsym : ALIGN_WITH_INPUT {
|
||||
*(.dynsym)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.dynstr : ALIGN_WITH_INPUT {
|
||||
*(.dynstr)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.gnu.version : ALIGN_WITH_INPUT {
|
||||
*(.gnu.version)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.gnu.version_d : ALIGN_WITH_INPUT {
|
||||
*(.gnu.version_d)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.gnu.version_r : ALIGN_WITH_INPUT {
|
||||
*(.gnu.version_r)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rel.dyn : ALIGN_WITH_INPUT {
|
||||
*(.rel.init)
|
||||
*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
|
||||
*(.rel.fini)
|
||||
*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
|
||||
*(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*)
|
||||
*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
|
||||
*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
|
||||
*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
|
||||
*(.rel.ctors)
|
||||
*(.rel.dtors)
|
||||
*(.rel.got)
|
||||
*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
|
||||
PROVIDE_HIDDEN (__rel_iplt_start = .);
|
||||
*(.rel.iplt)
|
||||
PROVIDE_HIDDEN (__rel_iplt_end = .);
|
||||
PROVIDE_HIDDEN (__rela_iplt_start = .);
|
||||
PROVIDE_HIDDEN (__rela_iplt_end = .);
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rela.dyn : ALIGN_WITH_INPUT {
|
||||
*(.rela.init)
|
||||
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
|
||||
*(.rela.fini)
|
||||
*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
|
||||
*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
|
||||
*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
|
||||
*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
|
||||
*(.rela.ctors)
|
||||
*(.rela.dtors)
|
||||
*(.rela.got)
|
||||
*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
|
||||
*(.rela.rtemsroset*)
|
||||
*(.rela.rtemsrwset*)
|
||||
PROVIDE_HIDDEN (__rel_iplt_start = .);
|
||||
PROVIDE_HIDDEN (__rel_iplt_end = .);
|
||||
PROVIDE_HIDDEN (__rela_iplt_start = .);
|
||||
*(.rela.iplt)
|
||||
PROVIDE_HIDDEN (__rela_iplt_end = .);
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rel.plt : ALIGN_WITH_INPUT {
|
||||
*(.rel.plt)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rela.plt : ALIGN_WITH_INPUT {
|
||||
*(.rela.plt)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.plt : ALIGN_WITH_INPUT {
|
||||
*(.plt)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.iplt : ALIGN_WITH_INPUT {
|
||||
*(.iplt)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.dynamic : ALIGN_WITH_INPUT {
|
||||
*(.dynamic)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.tm_clone_table : ALIGN_WITH_INPUT {
|
||||
*(.tm_clone_table)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.got : ALIGN_WITH_INPUT {
|
||||
*(.got.plt) *(.igot.plt) *(.got) *(.igot)
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
.rtemsroset : ALIGN_WITH_INPUT {
|
||||
/* Special FreeBSD linker set sections */
|
||||
__start_set_sysctl_set = .;
|
||||
*(set_sysctl_*);
|
||||
__stop_set_sysctl_set = .;
|
||||
*(set_domain_*);
|
||||
*(set_pseudo_*);
|
||||
|
||||
KEEP (*(SORT(.rtemsroset.*)))
|
||||
bsp_section_rodata_end = .;
|
||||
} > REGION_RODATA AT > REGION_RODATA_LOAD
|
||||
bsp_section_rodata_size = bsp_section_rodata_end - bsp_section_rodata_begin;
|
||||
bsp_section_rodata_load_begin = LOADADDR (.rodata);
|
||||
bsp_section_rodata_load_end = bsp_section_rodata_load_begin + bsp_section_rodata_size;
|
||||
|
||||
.rwbarrier : ALIGN_WITH_INPUT {
|
||||
. = ALIGN (bsp_section_rwbarrier_align);
|
||||
} > REGION_DATA AT > REGION_DATA
|
||||
|
||||
.vector : ALIGN_WITH_INPUT {
|
||||
bsp_section_vector_begin = .;
|
||||
. = . + DEFINED (bsp_vector_table_in_start_section) ? 0 : bsp_vector_table_size;
|
||||
bsp_section_vector_end = .;
|
||||
} > REGION_VECTOR AT > REGION_VECTOR
|
||||
bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_begin;
|
||||
bsp_vector_table_begin = DEFINED (bsp_vector_table_in_start_section) ? bsp_section_start_begin : bsp_section_vector_begin;
|
||||
bsp_vector_table_end = bsp_vector_table_begin + bsp_vector_table_size;
|
||||
|
||||
.fast_text : ALIGN_WITH_INPUT {
|
||||
bsp_section_fast_text_begin = .;
|
||||
*(.bsp_fast_text)
|
||||
bsp_section_fast_text_end = .;
|
||||
} > REGION_FAST_TEXT AT > REGION_FAST_TEXT_LOAD
|
||||
bsp_section_fast_text_size = bsp_section_fast_text_end - bsp_section_fast_text_begin;
|
||||
bsp_section_fast_text_load_begin = LOADADDR (.fast_text);
|
||||
bsp_section_fast_text_load_end = bsp_section_fast_text_load_begin + bsp_section_fast_text_size;
|
||||
|
||||
.fast_data : ALIGN_WITH_INPUT {
|
||||
bsp_section_fast_data_begin = .;
|
||||
*(.bsp_fast_data)
|
||||
bsp_section_fast_data_end = .;
|
||||
} > REGION_FAST_DATA AT > REGION_FAST_DATA_LOAD
|
||||
bsp_section_fast_data_size = bsp_section_fast_data_end - bsp_section_fast_data_begin;
|
||||
bsp_section_fast_data_load_begin = LOADADDR (.fast_data);
|
||||
bsp_section_fast_data_load_end = bsp_section_fast_data_load_begin + bsp_section_fast_data_size;
|
||||
|
||||
.data : ALIGN_WITH_INPUT {
|
||||
bsp_section_data_begin = .;
|
||||
*(.data .data.* .gnu.linkonce.d.*)
|
||||
SORT(CONSTRUCTORS)
|
||||
} > REGION_DATA AT > REGION_DATA_LOAD
|
||||
.data1 : ALIGN_WITH_INPUT {
|
||||
*(.data1)
|
||||
} > REGION_DATA AT > REGION_DATA_LOAD
|
||||
.rtemsrwset : ALIGN_WITH_INPUT {
|
||||
KEEP (*(SORT(.rtemsrwset.*)))
|
||||
bsp_section_data_end = .;
|
||||
} > REGION_DATA AT > REGION_DATA_LOAD
|
||||
bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin;
|
||||
bsp_section_data_load_begin = LOADADDR (.data);
|
||||
bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size;
|
||||
|
||||
.bss : ALIGN_WITH_INPUT {
|
||||
bsp_section_bss_begin = .;
|
||||
*(.dynbss)
|
||||
*(.bss .bss.* .gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
bsp_section_bss_end = .;
|
||||
} > REGION_BSS AT > REGION_BSS
|
||||
bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin;
|
||||
|
||||
.rtemsstack (NOLOAD) : ALIGN_WITH_INPUT {
|
||||
bsp_section_rtemsstack_begin = .;
|
||||
*(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*)))
|
||||
bsp_section_rtemsstack_end = .;
|
||||
} > REGION_WORK AT > REGION_WORK
|
||||
bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin;
|
||||
|
||||
.noinit (NOLOAD) : ALIGN_WITH_INPUT {
|
||||
bsp_section_noinit_begin = .;
|
||||
*(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*)))
|
||||
bsp_section_noinit_end = .;
|
||||
} > REGION_WORK AT > REGION_WORK
|
||||
bsp_section_noinit_size = bsp_section_noinit_end - bsp_section_noinit_begin;
|
||||
|
||||
.work : ALIGN_WITH_INPUT {
|
||||
/*
|
||||
* The work section will occupy the remaining REGION_WORK region and
|
||||
* contains the RTEMS work space and heap.
|
||||
*/
|
||||
bsp_section_work_begin = .;
|
||||
. += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.);
|
||||
bsp_section_work_end = .;
|
||||
} > REGION_WORK AT > REGION_WORK
|
||||
bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin;
|
||||
|
||||
.stack : ALIGN_WITH_INPUT {
|
||||
/*
|
||||
* The stack section will occupy the remaining REGION_STACK region and may
|
||||
* contain the task stacks. Depending on the region distribution this
|
||||
* section may be of zero size.
|
||||
*/
|
||||
bsp_section_stack_begin = .;
|
||||
. += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE (.);
|
||||
bsp_section_stack_end = .;
|
||||
} > REGION_STACK AT > REGION_STACK
|
||||
bsp_section_stack_size = bsp_section_stack_end - bsp_section_stack_begin;
|
||||
|
||||
.nocache : ALIGN_WITH_INPUT {
|
||||
bsp_section_nocache_begin = .;
|
||||
*(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_nocache*)))
|
||||
bsp_section_nocache_end = .;
|
||||
} > REGION_NOCACHE AT > REGION_NOCACHE_LOAD
|
||||
bsp_section_nocache_size = bsp_section_nocache_end - bsp_section_nocache_begin;
|
||||
bsp_section_nocache_load_begin = LOADADDR (.nocache);
|
||||
bsp_section_nocache_load_end = bsp_section_nocache_load_begin + bsp_section_nocache_size;
|
||||
|
||||
.nocachenoload (NOLOAD) : ALIGN_WITH_INPUT {
|
||||
bsp_section_nocachenoload_begin = .;
|
||||
*(SORT_BY_ALIGNMENT (SORT_BY_NAME (.bsp_noload_nocache*)))
|
||||
bsp_section_nocacheheap_begin = .;
|
||||
. += ORIGIN (REGION_NOCACHE) + LENGTH (REGION_NOCACHE) - ABSOLUTE (.);
|
||||
bsp_section_nocacheheap_end = .;
|
||||
bsp_section_nocachenoload_end = .;
|
||||
} > REGION_NOCACHE AT > REGION_NOCACHE
|
||||
bsp_section_nocacheheap_size = bsp_section_nocacheheap_end - bsp_section_nocacheheap_begin;
|
||||
bsp_section_nocachenoload_size = bsp_section_nocachenoload_end - bsp_section_nocachenoload_begin;
|
||||
|
||||
/* FIXME */
|
||||
RamBase = ORIGIN (REGION_WORK);
|
||||
RamSize = LENGTH (REGION_WORK);
|
||||
RamEnd = RamBase + RamSize;
|
||||
WorkAreaBase = bsp_section_work_begin;
|
||||
HeapSize = 0;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
Symbols in the DWARF debugging sections are relative to the beginning
|
||||
of the section so we begin them at 0. */
|
||||
/* DWARF 1. */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions. */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2. */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2. */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions. */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
/* DWARF 3. */
|
||||
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
||||
.debug_ranges 0 : { *(.debug_ranges) }
|
||||
/* DWARF 5. */
|
||||
.debug_addr 0 : { *(.debug_addr) }
|
||||
.debug_line_str 0 : { *(.debug_line_str) }
|
||||
.debug_loclists 0 : { *(.debug_loclists) }
|
||||
.debug_macro 0 : { *(.debug_macro) }
|
||||
.debug_names 0 : { *(.debug_names) }
|
||||
.debug_rnglists 0 : { *(.debug_rnglists) }
|
||||
.debug_str_offsets 0 : { *(.debug_str_offsets) }
|
||||
.debug_sup 0 : { *(.debug_sup) }
|
||||
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) KEEP (*(.gnu.attributes)) }
|
||||
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
|
||||
|
||||
/* Addition to let linker know about custom section for GDB pretty-printing support. */
|
||||
.debug_gdb_scripts 0 : { *(.debug_gdb_scripts) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
|
||||
|
||||
/*
|
||||
* This is a RTEMS specific section to catch all unexpected input
|
||||
* sections. In case you get an error like
|
||||
* "section `.unexpected_sections' will not fit in region
|
||||
* `UNEXPECTED_SECTIONS'"
|
||||
* you have to figure out the offending input section and add it to the
|
||||
* appropriate output section definition above.
|
||||
*/
|
||||
.unexpected_sections : { *(*) } > UNEXPECTED_SECTIONS
|
||||
}
|
||||
@@ -1,47 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief This source file contains the
|
||||
* _AArch64_Get_current_processor_for_system_start() default implementation
|
||||
* using the MPIDR_EL1.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 embedded brains GmbH & Co. KG
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/asm.h>
|
||||
|
||||
FUNCTION_ENTRY(_AArch64_Get_current_processor_for_system_start)
|
||||
|
||||
/* Return the affinity level 0 reported by the MPIDR_EL1 */
|
||||
mrs x0, mpidr_el1
|
||||
and x0, x0, #0xff
|
||||
ret
|
||||
|
||||
FUNCTION_END(_AArch64_Get_current_processor_for_system_start)
|
||||
@@ -1,369 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Shared
|
||||
*
|
||||
* @brief Boot and system start code.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/asm.h>
|
||||
#include <rtems/score/percpu.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bspopts.h>
|
||||
|
||||
/* Global symbols */
|
||||
.globl _start
|
||||
.section ".bsp_start_text", "ax"
|
||||
|
||||
#ifdef BSP_START_IMAGE_HEADER
|
||||
/*
|
||||
* This format is defined by:
|
||||
* https://www.kernel.org/doc/Documentation/arm64/booting.txt
|
||||
*/
|
||||
mov x0, x0
|
||||
b _start
|
||||
/*
|
||||
* This must be defined by the BSP as different environments may not treat it
|
||||
* the same. Xen treats it as an offset from 0x40000000 while QEMU treats it
|
||||
* as an absolute offset (RAM origin + load offset).
|
||||
*/
|
||||
.dword BSP_START_IMAGE_HEADER_LOAD_OFFSET
|
||||
.dword 0 /* image size */
|
||||
.dword 0 /* kernel flags, LE, page size unspecified, place near RAM start */
|
||||
.dword 0 /* reserved 2 */
|
||||
.dword 0 /* reserved 3 */
|
||||
.dword 0 /* reserved 4 */
|
||||
.word 0x644d5241 /* magic, ascii ['A', 'R', 'M', 64] LE */
|
||||
.word 0 /* reserved 5, PE COFF offset */
|
||||
#endif /* BSP_START_IMAGE_HEADER */
|
||||
|
||||
/* Start entry */
|
||||
|
||||
_start:
|
||||
|
||||
/*
|
||||
* We do not save the context since we do not return to the boot
|
||||
* loader but preserve x1 and x2 to allow access to bootloader parameters
|
||||
*/
|
||||
#ifndef BSP_START_NEEDS_REGISTER_INITIALIZATION
|
||||
mov x5, x1 /* machine type number or ~0 for DT boot */
|
||||
mov x6, x2 /* physical address of ATAGs or DTB */
|
||||
#else /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
|
||||
/*
|
||||
* This block is dead code. No aarch64 targets require this. It might be
|
||||
* needed for hardware simulations or in future processor variants with
|
||||
* lock-step cores.
|
||||
*/
|
||||
mov x0, XZR
|
||||
mov x1, XZR
|
||||
mov x2, XZR
|
||||
mov x3, XZR
|
||||
mov x4, XZR
|
||||
mov x5, XZR
|
||||
mov x6, XZR
|
||||
mov x7, XZR
|
||||
mov x8, XZR
|
||||
mov x9, XZR
|
||||
mov x10, XZR
|
||||
mov x11, XZR
|
||||
mov x12, XZR
|
||||
mov x13, XZR
|
||||
mov x14, XZR
|
||||
mov x15, XZR
|
||||
mov x16, XZR
|
||||
mov x17, XZR
|
||||
mov x18, XZR
|
||||
mov x19, XZR
|
||||
mov x20, XZR
|
||||
mov x21, XZR
|
||||
mov x22, XZR
|
||||
mov x23, XZR
|
||||
mov x24, XZR
|
||||
mov x25, XZR
|
||||
mov x26, XZR
|
||||
mov x27, XZR
|
||||
mov x28, XZR
|
||||
mov x29, XZR
|
||||
mov x30, XZR
|
||||
#ifdef AARCH64_MULTILIB_VFP
|
||||
mov CPTR_EL3, XZR
|
||||
mov CPTR_EL2, XZR
|
||||
mov d0, XZR
|
||||
mov d1, XZR
|
||||
mov d2, XZR
|
||||
mov d3, XZR
|
||||
mov d4, XZR
|
||||
mov d5, XZR
|
||||
mov d6, XZR
|
||||
mov d7, XZR
|
||||
mov d8, XZR
|
||||
mov d9, XZR
|
||||
mov d10, XZR
|
||||
mov d11, XZR
|
||||
mov d12, XZR
|
||||
mov d13, XZR
|
||||
mov d14, XZR
|
||||
mov d15, XZR
|
||||
mov d16, XZR
|
||||
mov d17, XZR
|
||||
mov d18, XZR
|
||||
mov d19, XZR
|
||||
mov d20, XZR
|
||||
mov d21, XZR
|
||||
mov d22, XZR
|
||||
mov d23, XZR
|
||||
mov d24, XZR
|
||||
mov d25, XZR
|
||||
mov d26, XZR
|
||||
mov d27, XZR
|
||||
mov d28, XZR
|
||||
mov d29, XZR
|
||||
mov d30, XZR
|
||||
mov d31, XZR
|
||||
#endif /* AARCH64_MULTILIB_VFP */
|
||||
#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
|
||||
|
||||
/* Initialize SCTLR_EL1 */
|
||||
mov x0, XZR
|
||||
#if defined(RTEMS_DEBUG)
|
||||
/* Enable Stack alignment checking */
|
||||
orr x0, x0, #(1<<3)
|
||||
#endif
|
||||
msr SCTLR_EL1, x0
|
||||
|
||||
#if defined(BSP_START_ENABLE_EL2_START_SUPPORT) || \
|
||||
defined(BSP_START_ENABLE_EL3_START_SUPPORT)
|
||||
mrs x0, CurrentEL
|
||||
cmp x0, #(1<<2)
|
||||
b.eq .L_el1_start
|
||||
#endif
|
||||
|
||||
#if defined(BSP_START_ENABLE_EL3_START_SUPPORT)
|
||||
cmp x0, #(2<<2)
|
||||
b.eq .L_el2_start
|
||||
|
||||
.L_el3_start:
|
||||
/*
|
||||
* Before leaving the Secure World, we need to initialize the GIC. We
|
||||
* do that here in an early stack context in EL3. This will NOT work
|
||||
* on secondary core boot! We assume only the primary boot core will
|
||||
* start in EL3 if any. Usually on real hardware, we should be running
|
||||
* on top of trusted firmware and will not boot in EL3. Qemu fakes it
|
||||
* for us and will start the primary core in EL3 and secondary cores
|
||||
* will be brought up in EL1NS as expected.
|
||||
*/
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w1, =_ISR_Stack_size
|
||||
ldr w2, =_ISR_Stack_area_begin
|
||||
#else
|
||||
ldr x1, =_ISR_Stack_size
|
||||
ldr x2, =_ISR_Stack_area_begin
|
||||
#endif
|
||||
add x3, x1, x2
|
||||
/* using SP0 for the early init stack context at EL3 */
|
||||
msr spsel, #0
|
||||
mov sp, x3
|
||||
|
||||
/*
|
||||
* Invoke the start hook 0.
|
||||
* We don't set up exception handling, so this hook better behave.
|
||||
*/
|
||||
bl bsp_start_hook_0
|
||||
|
||||
/* Drop from EL3 to EL2 */
|
||||
|
||||
/* Initialize HCR_EL2 and SCTLR_EL2 */
|
||||
msr HCR_EL2, XZR
|
||||
msr SCTLR_EL2, XZR
|
||||
/* Set EL2 Execution state via SCR_EL3 */
|
||||
mrs x0, SCR_EL3
|
||||
/* Set EL2 to AArch64 */
|
||||
orr x0, x0, #(1<<10)
|
||||
/* Set EL1 to NS */
|
||||
orr x0, x0, #1
|
||||
msr SCR_EL3, x0
|
||||
|
||||
/* set EL2h mode for eret */
|
||||
mov x0, #0b01001
|
||||
msr SPSR_EL3, x0
|
||||
|
||||
/* Set EL2 entry point */
|
||||
adr x0, .L_el2_start
|
||||
msr ELR_EL3, x0
|
||||
eret
|
||||
#endif
|
||||
|
||||
#if defined(BSP_START_ENABLE_EL2_START_SUPPORT) || \
|
||||
defined(BSP_START_ENABLE_EL3_START_SUPPORT)
|
||||
.L_el2_start:
|
||||
/* Drop from EL2 to EL1 */
|
||||
|
||||
/* Configure HCR_EL2 */
|
||||
mrs x0, HCR_EL2
|
||||
/* Set EL1 Execution state to AArch64 */
|
||||
orr x0, x0, #(1<<31)
|
||||
/* Disable ID traps */
|
||||
bic x0, x0, #(1<<15)
|
||||
bic x0, x0, #(1<<16)
|
||||
bic x0, x0, #(1<<17)
|
||||
bic x0, x0, #(1<<18)
|
||||
msr HCR_EL2, x0
|
||||
|
||||
/* Set to EL1h mode for eret */
|
||||
mov x0, #0b00101
|
||||
msr SPSR_EL2, x0
|
||||
|
||||
/* Set EL1 entry point */
|
||||
adr x0, .L_el1_start
|
||||
msr ELR_EL2, x0
|
||||
eret
|
||||
|
||||
.L_el1_start:
|
||||
#endif
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
bl _AArch64_Get_current_processor_for_system_start
|
||||
|
||||
/*
|
||||
* Check that this is a configured processor. If not, then there is
|
||||
* not much that can be done since we do not have a stack available for
|
||||
* this processor. Just loop forever in this case.
|
||||
*/
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w1, =_SMP_Processor_configured_maximum
|
||||
#else
|
||||
ldr x1, =_SMP_Processor_configured_maximum
|
||||
#endif
|
||||
ldr w1, [x1]
|
||||
cmp x1, x0
|
||||
bgt .Lconfigured_processor
|
||||
.Linvalid_processor_wait_for_ever:
|
||||
wfe
|
||||
b .Linvalid_processor_wait_for_ever
|
||||
.Lconfigured_processor:
|
||||
|
||||
/*
|
||||
* Get current per-CPU control and store it in PL1 only Thread ID
|
||||
* Register (TPIDR_EL1).
|
||||
*/
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w1, =_Per_CPU_Information
|
||||
#else
|
||||
ldr x1, =_Per_CPU_Information
|
||||
#endif
|
||||
add x1, x1, x0, lsl #PER_CPU_CONTROL_SIZE_LOG2
|
||||
msr TPIDR_EL1, x1
|
||||
|
||||
#endif
|
||||
|
||||
/* Calculate interrupt stack area end for current processor */
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w1, =_ISR_Stack_size
|
||||
#else
|
||||
ldr x1, =_ISR_Stack_size
|
||||
#endif
|
||||
#ifdef RTEMS_SMP
|
||||
add x3, x0, #1
|
||||
mul x1, x1, x3
|
||||
#endif
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w2, =_ISR_Stack_area_begin
|
||||
#else
|
||||
ldr x2, =_ISR_Stack_area_begin
|
||||
#endif
|
||||
add x3, x1, x2
|
||||
|
||||
/* Disable interrupts and debug */
|
||||
msr DAIFSet, #0xa
|
||||
|
||||
#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
|
||||
mov x8, XZR
|
||||
mov x9, XZR
|
||||
mov x10, XZR
|
||||
mov x11, XZR
|
||||
mov x12, XZR
|
||||
mov x13, XZR
|
||||
mov x14, XZR
|
||||
mov x15, XZR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SPx: the stack pointer corresponding to the current exception level
|
||||
* Normal operation for RTEMS on AArch64 uses SPx and runs on EL1
|
||||
* Exception operation (synchronous errors, IRQ, FIQ, System Errors) uses SP0
|
||||
*/
|
||||
#ifdef AARCH64_MULTILIB_ARCH_V8_ILP32
|
||||
ldr w1, =bsp_stack_exception_size
|
||||
#else
|
||||
ldr x1, =bsp_stack_exception_size
|
||||
#endif
|
||||
/* Switch to SP0 and set exception stack */
|
||||
msr spsel, #0
|
||||
mov sp, x3
|
||||
/* Switch back to SPx for normal operation */
|
||||
msr spsel, #1
|
||||
sub x3, x3, x1
|
||||
|
||||
/* Set SP1 stack used for normal operation */
|
||||
mov sp, x3
|
||||
|
||||
/* Stay in EL1 mode */
|
||||
|
||||
#ifdef AARCH64_MULTILIB_VFP
|
||||
#ifdef AARCH64_MULTILIB_HAS_CPACR
|
||||
/* Read CPACR */
|
||||
mrs x0, CPACR_EL1
|
||||
|
||||
/* Enable EL1 access permissions for CP10 */
|
||||
orr x0, x0, #(1 << 20)
|
||||
|
||||
/* Write CPACR */
|
||||
msr CPACR_EL1, x0
|
||||
isb
|
||||
#endif
|
||||
|
||||
/* FPU does not need to be enabled on AArch64 */
|
||||
|
||||
/* Ensure FPU traps are disabled by default */
|
||||
mrs x0, FPCR
|
||||
bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12))
|
||||
bic x0, x0, #(1 << 15)
|
||||
msr FPCR, x0
|
||||
|
||||
#endif /* AARCH64_MULTILIB_VFP */
|
||||
|
||||
/* Branch to start hook 1 */
|
||||
bl bsp_start_hook_1
|
||||
|
||||
/* Branch to boot card */
|
||||
mov x0, #0
|
||||
bl boot_card
|
||||
@@ -1,72 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the console configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/bspIo.h>
|
||||
|
||||
#include <bsp.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <bsp/console-termios.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
arm_pl011_context xen_vpl011_context = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
|
||||
.regs = (arm_pl011_uart *) BSP_XEN_VPL011_BASE,
|
||||
.irq = BSP_XEN_VPL011_SPI,
|
||||
.initial_baud = 115200,
|
||||
.clock = 24000000
|
||||
};
|
||||
|
||||
const console_device console_device_table[] = {
|
||||
{
|
||||
.device_file = "/dev/ttyS0",
|
||||
.probe = console_device_probe_default,
|
||||
.handler = &arm_pl011_fns,
|
||||
.context = &xen_vpl011_context.base
|
||||
}
|
||||
};
|
||||
|
||||
const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
|
||||
|
||||
static void output_char( char c )
|
||||
{
|
||||
arm_pl011_write_polled(&xen_vpl011_context.base, c);
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = output_char;
|
||||
|
||||
BSP_polling_getchar_function_type BSP_poll_char = NULL;
|
||||
@@ -1,90 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the base BSP definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XEN_BSP_H
|
||||
#define LIBBSP_AARCH64_XEN_BSP_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsARM
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#define BSP_FEATURE_IRQ_EXTENSION
|
||||
|
||||
#define BSP_START_IMAGE_HEADER_LOAD_OFFSET BSP_XEN_LOAD_OFFSET
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0x03002000
|
||||
#define BSP_ARM_GIC_CPUIF_LENGTH 0x2000
|
||||
|
||||
#define BSP_ARM_GIC_DIST_BASE 0x03001000
|
||||
#define BSP_ARM_GIC_DIST_LENGTH 0x1000
|
||||
|
||||
#define BSP_XEN_VPL011_BASE 0x22000000
|
||||
#define BSP_XEN_VPL011_LENGTH 0x1000
|
||||
|
||||
BSP_START_TEXT_SECTION void xen_setup_mmu_and_cache( void );
|
||||
|
||||
/**
|
||||
* @brief Xen-specific set up of the MMU for non-primary
|
||||
* cores.
|
||||
*
|
||||
* Provide in the application to override the defaults in the BSP.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void xen_setup_secondary_cpu_mmu_and_cache( void );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XEN_BSP_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the BSP IRQ definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XEN_IRQ_H
|
||||
#define LIBBSP_AARCH64_XEN_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT 1019
|
||||
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_S_PPI 29
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define BSP_XEN_EVTCHN_PPI 31
|
||||
#define BSP_XEN_VPL011_SPI 32
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XEN_IRQ_H */
|
||||
@@ -1,46 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the TM27 test definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <dev/irq/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -1,52 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the implementation of start hooks.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <dev/clock/arm-generic-timer.h>
|
||||
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
rtems_cache_coherent_add_area(
|
||||
bsp_section_nocacheheap_begin,
|
||||
(uintptr_t) bsp_section_nocacheheap_size
|
||||
);
|
||||
}
|
||||
@@ -1,70 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the implementation of start hooks.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
#include <rtems/score/smpimpl.h>
|
||||
|
||||
#include <bsp/irq-generic.h>
|
||||
#endif
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1( void )
|
||||
{
|
||||
AArch64_start_set_vector_base();
|
||||
|
||||
#ifdef RTEMS_SMP
|
||||
uint32_t cpu_index_self;
|
||||
|
||||
cpu_index_self = _SMP_Get_current_processor();
|
||||
|
||||
if ( cpu_index_self != 0 ) {
|
||||
xen_setup_secondary_cpu_mmu_and_cache();
|
||||
arm_gic_irq_initialize_secondary_cpu();
|
||||
|
||||
bsp_interrupt_vector_enable( ARM_GIC_IRQ_SGI_0 );
|
||||
_SMP_Start_multitasking_on_secondary_processor(
|
||||
_Per_CPU_Get_by_index( cpu_index_self )
|
||||
);
|
||||
/* Unreached */
|
||||
}
|
||||
#endif /* RTEMS_SMP */
|
||||
|
||||
xen_setup_mmu_and_cache();
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -1,67 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the default MMU tables and setup.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
#include <rtems/malloc.h>
|
||||
#include <rtems/sysinit.h>
|
||||
|
||||
BSP_START_TEXT_SECTION void
|
||||
xen_setup_mmu_and_cache( void )
|
||||
{
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
aarch64_mmu_setup();
|
||||
|
||||
aarch64_mmu_setup_translation_table(
|
||||
control,
|
||||
&aarch64_mmu_config_table[ 0 ],
|
||||
aarch64_mmu_config_table_size
|
||||
);
|
||||
|
||||
aarch64_mmu_enable( control );
|
||||
}
|
||||
|
||||
BSP_START_TEXT_SECTION void xen_setup_secondary_cpu_mmu_and_cache( void )
|
||||
{
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
/* Perform basic MMU setup */
|
||||
aarch64_mmu_setup();
|
||||
aarch64_mmu_enable( control );
|
||||
}
|
||||
@@ -1,70 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64Xen
|
||||
*
|
||||
* @brief This source file contains the definition of ::aarch64_mmu_config_table
|
||||
* and ::aarch64_mmu_config_table_size.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <bsp/start.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
BSP_START_DATA_SECTION const aarch64_mmu_config_entry
|
||||
aarch64_mmu_config_table[] = {
|
||||
AARCH64_MMU_DEFAULT_SECTIONS,
|
||||
{
|
||||
.begin = 0xf9000000U,
|
||||
.end = 0xf9100000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, {
|
||||
.begin = 0xfd000000U,
|
||||
.end = 0xffc00000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, {
|
||||
.begin = BSP_XEN_VPL011_BASE,
|
||||
.end = BSP_XEN_VPL011_BASE + BSP_XEN_VPL011_LENGTH,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, {
|
||||
.begin = BSP_ARM_GIC_CPUIF_BASE,
|
||||
.end = BSP_ARM_GIC_CPUIF_BASE + BSP_ARM_GIC_CPUIF_LENGTH,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, {
|
||||
.begin = BSP_ARM_GIC_DIST_BASE,
|
||||
.end = BSP_ARM_GIC_DIST_BASE + BSP_ARM_GIC_DIST_LENGTH,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}
|
||||
};
|
||||
|
||||
BSP_START_DATA_SECTION const size_t aarch64_mmu_config_table_size =
|
||||
RTEMS_ARRAY_SIZE(aarch64_mmu_config_table);
|
||||
@@ -1,149 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This source file contains this BSP's console configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/bspIo.h>
|
||||
#include <rtems/sysinit.h>
|
||||
|
||||
#include <bsp/irq.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <dev/serial/versal-uart.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
static versal_pl011_context versal_uart_instances[2] = {
|
||||
{
|
||||
.pl011_ctx = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Versal UART 0"),
|
||||
.regs = (arm_pl011_uart *) 0xff000000,
|
||||
.irq = VERSAL_IRQ_UART_0,
|
||||
.clock = VERSAL_CLOCK_UART,
|
||||
.initial_baud = VERSAL_UART_DEFAULT_BAUD
|
||||
}
|
||||
}, {
|
||||
.pl011_ctx = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Versal UART 1"),
|
||||
.regs = (arm_pl011_uart *) 0xff010000,
|
||||
.irq = VERSAL_IRQ_UART_1,
|
||||
.clock = VERSAL_CLOCK_UART,
|
||||
.initial_baud = VERSAL_UART_DEFAULT_BAUD
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
rtems_status_code console_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
(void) major;
|
||||
(void) minor;
|
||||
(void) arg;
|
||||
|
||||
size_t i;
|
||||
|
||||
rtems_termios_initialize();
|
||||
|
||||
for (i = 0; i < RTEMS_ARRAY_SIZE(versal_uart_instances); ++i) {
|
||||
char uart[] = "/dev/ttySX";
|
||||
|
||||
uart[sizeof(uart) - 2] = (char) ('0' + i);
|
||||
rtems_termios_device_install(
|
||||
&uart[0],
|
||||
&versal_uart_handler,
|
||||
NULL,
|
||||
&versal_uart_instances[i].pl011_ctx.base
|
||||
);
|
||||
|
||||
if (i == BSP_CONSOLE_MINOR) {
|
||||
link(&uart[0], CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
}
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void versal_debug_console_flush(void)
|
||||
{
|
||||
versal_uart_reset_tx_flush(
|
||||
&versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base
|
||||
);
|
||||
}
|
||||
|
||||
static void versal_debug_console_out(char c)
|
||||
{
|
||||
rtems_termios_device_context *base =
|
||||
&versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
|
||||
|
||||
arm_pl011_write_polled(base, c);
|
||||
}
|
||||
|
||||
static void versal_debug_console_init(void)
|
||||
{
|
||||
rtems_termios_device_context *base =
|
||||
&versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
|
||||
|
||||
(void) versal_uart_initialize(base);
|
||||
BSP_output_char = versal_debug_console_out;
|
||||
}
|
||||
|
||||
static void versal_debug_console_early_init(char c)
|
||||
{
|
||||
rtems_termios_device_context *base =
|
||||
&versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
|
||||
|
||||
(void) versal_uart_initialize(base);
|
||||
BSP_output_char = versal_debug_console_out;
|
||||
versal_debug_console_out(c);
|
||||
}
|
||||
|
||||
static int versal_debug_console_in(void)
|
||||
{
|
||||
rtems_termios_device_context *base =
|
||||
&versal_uart_instances[BSP_CONSOLE_MINOR].pl011_ctx.base;
|
||||
|
||||
return arm_pl011_read_polled(base);
|
||||
}
|
||||
|
||||
BSP_output_char_function_type BSP_output_char = versal_debug_console_early_init;
|
||||
|
||||
BSP_polling_getchar_function_type BSP_poll_char = versal_debug_console_in;
|
||||
|
||||
RTEMS_SYSINIT_ITEM(
|
||||
versal_debug_console_init,
|
||||
RTEMS_SYSINIT_BSP_START,
|
||||
RTEMS_SYSINIT_ORDER_LAST_BUT_5
|
||||
);
|
||||
@@ -1,383 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Chris Johns <chris@contemporary.software>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dev/serial/versal-uart.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <bsp/irq.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
static uint32_t versal_uart_intr_all(void)
|
||||
{
|
||||
return PL011_UARTI_OEI |
|
||||
PL011_UARTI_BEI |
|
||||
PL011_UARTI_PEI |
|
||||
PL011_UARTI_FEI |
|
||||
PL011_UARTI_RTI |
|
||||
PL011_UARTI_TXI |
|
||||
PL011_UARTI_RXI |
|
||||
PL011_UARTI_DSRMI |
|
||||
PL011_UARTI_DCDMI |
|
||||
PL011_UARTI_CTSMI |
|
||||
PL011_UARTI_RIMI;
|
||||
}
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
static void versal_uart_intr_clear(volatile arm_pl011_uart *regs, uint32_t ints)
|
||||
{
|
||||
regs->base.uarticr = ints;
|
||||
}
|
||||
|
||||
static void versal_uart_intr_clearall(volatile arm_pl011_uart *regs)
|
||||
{
|
||||
versal_uart_intr_clear(regs, versal_uart_intr_all());
|
||||
}
|
||||
|
||||
static void versal_uart_intr_enable(volatile arm_pl011_uart *regs, uint32_t ints)
|
||||
{
|
||||
regs->base.uartimsc |= ints;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void versal_uart_intr_disable(volatile arm_pl011_uart *regs, uint32_t ints)
|
||||
{
|
||||
regs->base.uartimsc &= ~ints;
|
||||
}
|
||||
|
||||
static void versal_uart_intr_disableall(volatile arm_pl011_uart *regs)
|
||||
{
|
||||
versal_uart_intr_disable(regs, versal_uart_intr_all());
|
||||
}
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
static bool versal_uart_flags_clear(volatile arm_pl011_uart *regs, uint32_t flags)
|
||||
{
|
||||
return (regs->base.uartfr & flags) == 0;
|
||||
}
|
||||
|
||||
static void versal_uart_interrupt(void *arg)
|
||||
{
|
||||
rtems_termios_tty *tty = arg;
|
||||
versal_pl011_context *ctx = rtems_termios_get_device_context(tty);
|
||||
volatile arm_pl011_uart *regs = (volatile arm_pl011_uart *) ctx->pl011_ctx.regs;
|
||||
uint32_t uartmis = regs->base.uartmis;
|
||||
|
||||
versal_uart_intr_clear(regs, uartmis);
|
||||
|
||||
if ((uartmis & (PL011_UARTI_RTI | PL011_UARTI_RXI)) != 0) {
|
||||
char buf[32];
|
||||
int c = 0;
|
||||
while (c < sizeof(buf) &&
|
||||
versal_uart_flags_clear(regs, PL011_UARTFR_RXFE)) {
|
||||
buf[c++] = (char) PL011_UARTDR_DATA_GET(regs->base.uartdr);
|
||||
}
|
||||
rtems_termios_enqueue_raw_characters(tty, buf, c);
|
||||
}
|
||||
|
||||
if (ctx->transmitting) {
|
||||
int sent = ctx->pl011_ctx.tx_queued_chars;
|
||||
ctx->transmitting = false;
|
||||
ctx->pl011_ctx.tx_queued_chars = 0;
|
||||
versal_uart_intr_disable(regs, PL011_UARTI_TXI);
|
||||
rtems_termios_dequeue_characters(tty, sent);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void versal_uart_reset_tx_flush(rtems_termios_device_context *base)
|
||||
{
|
||||
volatile arm_pl011_uart *regs = (volatile arm_pl011_uart *) arm_pl011_get_regs(base);
|
||||
int c = 4;
|
||||
|
||||
while (c-- > 0) {
|
||||
arm_pl011_write_polled(base, '\r');
|
||||
}
|
||||
|
||||
while ((regs->base.uartfr & PL011_UARTFR_TXFE) == 0) {
|
||||
/* Wait for empty */
|
||||
}
|
||||
while ((regs->base.uartfr & PL011_UARTFR_BUSY) != 0) {
|
||||
/* Wait for empty */
|
||||
}
|
||||
}
|
||||
|
||||
int versal_uart_initialize(rtems_termios_device_context *base)
|
||||
{
|
||||
volatile pl011_base *regs = (volatile pl011_base *)arm_pl011_get_regs(base);
|
||||
arm_pl011_context *ctx = (arm_pl011_context *) base;
|
||||
uint32_t maxerr = 3;
|
||||
uint32_t ibauddiv = 0;
|
||||
uint32_t fbauddiv = 0;
|
||||
int rv;
|
||||
|
||||
versal_uart_reset_tx_flush(base);
|
||||
|
||||
rv = arm_pl011_compute_baudrate_params(
|
||||
&ibauddiv,
|
||||
&fbauddiv,
|
||||
VERSAL_UART_DEFAULT_BAUD,
|
||||
ctx->clock,
|
||||
maxerr
|
||||
);
|
||||
if (rv != 0) {
|
||||
return rv;
|
||||
}
|
||||
|
||||
/* Line control: 8-bit word length, no parity, no FIFO, 1 stop bit */
|
||||
regs->uartlcr_h = PL011_UARTLCR_H_WLEN( PL011_UARTLCR_H_WLEN_8 )
|
||||
| PL011_UARTLCR_H_FEN;
|
||||
|
||||
/* Control: receive, transmit, uart enable, no CTS, no RTS, no loopback */
|
||||
regs->uartcr = PL011_UARTCR_RXE
|
||||
| PL011_UARTCR_TXE
|
||||
| PL011_UARTCR_UARTEN;
|
||||
|
||||
regs->uartibrd = ibauddiv;
|
||||
regs->uartfbrd = fbauddiv;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool versal_uart_first_open(
|
||||
rtems_termios_tty *tty,
|
||||
rtems_termios_device_context *base,
|
||||
struct termios *term,
|
||||
rtems_libio_open_close_args_t *args
|
||||
)
|
||||
{
|
||||
(void) term;
|
||||
(void) args;
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
versal_pl011_context *ctx = (versal_pl011_context *) base;
|
||||
volatile arm_pl011_uart *regs = (volatile arm_pl011_uart *) ctx->pl011_ctx.regs;
|
||||
rtems_status_code sc;
|
||||
|
||||
ctx->transmitting = false;
|
||||
ctx->pl011_ctx.tx_queued_chars = 0;
|
||||
ctx->pl011_ctx.needs_sw_triggered_tx_irq = true;
|
||||
#endif
|
||||
|
||||
rtems_termios_set_initial_baud(tty, VERSAL_UART_DEFAULT_BAUD);
|
||||
versal_uart_initialize(base);
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
regs->base.uartifls = PL011_UARTIFLS_RXIFLSEL(2) | PL011_UARTIFLS_TXIFLSEL(2);
|
||||
regs->base.uartlcr_h |= PL011_UARTLCR_H_FEN;
|
||||
versal_uart_intr_disableall(regs);
|
||||
sc = rtems_interrupt_handler_install(
|
||||
ctx->pl011_ctx.irq,
|
||||
"UART",
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
versal_uart_interrupt,
|
||||
tty
|
||||
);
|
||||
if (sc != RTEMS_SUCCESSFUL) {
|
||||
return false;
|
||||
}
|
||||
versal_uart_intr_clearall(regs);
|
||||
versal_uart_intr_enable(regs, PL011_UARTI_RTI | PL011_UARTI_RXI);
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
static void versal_uart_last_close(
|
||||
rtems_termios_tty *tty,
|
||||
rtems_termios_device_context *base,
|
||||
rtems_libio_open_close_args_t *args
|
||||
)
|
||||
{
|
||||
(void) args;
|
||||
|
||||
versal_pl011_context *ctx = (versal_pl011_context *) base;
|
||||
rtems_interrupt_handler_remove(ctx->pl011_ctx.irq, versal_uart_interrupt, tty);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void versal_uart_write_support(
|
||||
rtems_termios_device_context *base,
|
||||
const char *buf,
|
||||
size_t len
|
||||
)
|
||||
{
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
versal_pl011_context *ctx = (versal_pl011_context *) base;
|
||||
volatile arm_pl011_uart *regs = (volatile arm_pl011_uart *) ctx->pl011_ctx.regs;
|
||||
|
||||
if (len > 0) {
|
||||
size_t len_remaining = len;
|
||||
const char *p = &buf[0];
|
||||
versal_uart_intr_enable(regs, PL011_UARTI_TXI);
|
||||
/*
|
||||
* The PL011 IP in the Versal needs preloading the TX FIFO with
|
||||
* exactly 17 characters for the first TX interrupt to be
|
||||
* generated.
|
||||
*/
|
||||
if (ctx->pl011_ctx.needs_sw_triggered_tx_irq) {
|
||||
ctx->pl011_ctx.needs_sw_triggered_tx_irq = false;
|
||||
for (int i = 0; i < 17; ++i) {
|
||||
regs->base.uartdr = PL011_UARTDR_DATA('\r');
|
||||
}
|
||||
}
|
||||
while (versal_uart_flags_clear(regs, PL011_UARTFR_TXFF) &&
|
||||
len_remaining > 0) {
|
||||
regs->base.uartdr = PL011_UARTDR_DATA(*p++);
|
||||
--len_remaining;
|
||||
}
|
||||
ctx->pl011_ctx.tx_queued_chars = len - len_remaining;
|
||||
ctx->transmitting = true;
|
||||
}
|
||||
#else
|
||||
ssize_t i;
|
||||
for (i = 0; i < len; ++i) {
|
||||
arm_pl011_write_polled(base, buf[i]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static bool versal_uart_set_attributes(
|
||||
rtems_termios_device_context *context,
|
||||
const struct termios *term
|
||||
)
|
||||
{
|
||||
versal_pl011_context *ctx = (versal_pl011_context *) context;
|
||||
volatile arm_pl011_uart *regs = (volatile arm_pl011_uart *) ctx->pl011_ctx.regs;
|
||||
int32_t baud;
|
||||
uint32_t ibauddiv = 0;
|
||||
uint32_t fbauddiv = 0;
|
||||
uint32_t mode = 0;
|
||||
int rc;
|
||||
|
||||
/*
|
||||
* Determine the baud rate
|
||||
*/
|
||||
baud = rtems_termios_baud_to_number(term->c_ospeed);
|
||||
|
||||
if (baud > 0) {
|
||||
uint32_t maxerr = 3;
|
||||
|
||||
rc = arm_pl011_compute_baudrate_params(
|
||||
&ibauddiv,
|
||||
&fbauddiv,
|
||||
baud,
|
||||
ctx->pl011_ctx.clock,
|
||||
maxerr
|
||||
);
|
||||
if (rc != 0) {
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure the mode register
|
||||
*/
|
||||
mode = regs->base.uartlcr_h & PL011_UARTLCR_H_FEN;
|
||||
|
||||
/*
|
||||
* Parity
|
||||
*/
|
||||
if ((term->c_cflag & PARENB) != 0) {
|
||||
mode |= PL011_UARTLCR_H_PEN;
|
||||
if ((term->c_cflag & PARODD) == 0) {
|
||||
mode |= PL011_UARTLCR_H_EPS;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Character Size
|
||||
*/
|
||||
switch (term->c_cflag & CSIZE)
|
||||
{
|
||||
case CS5:
|
||||
mode = PL011_UARTLCR_H_WLEN_SET(mode, PL011_UARTLCR_H_WLEN_5);
|
||||
break;
|
||||
case CS6:
|
||||
mode = PL011_UARTLCR_H_WLEN_SET(mode, PL011_UARTLCR_H_WLEN_6);
|
||||
break;
|
||||
case CS7:
|
||||
mode = PL011_UARTLCR_H_WLEN_SET(mode, PL011_UARTLCR_H_WLEN_7);
|
||||
break;
|
||||
case CS8:
|
||||
default:
|
||||
mode = PL011_UARTLCR_H_WLEN_SET(mode, PL011_UARTLCR_H_WLEN_8);
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Stop Bits
|
||||
*/
|
||||
if (term->c_cflag & CSTOPB) {
|
||||
/* 2 stop bits */
|
||||
mode |= PL011_UARTLCR_H_STP2;
|
||||
}
|
||||
|
||||
versal_uart_intr_disableall(regs);
|
||||
|
||||
/*
|
||||
* Wait for any data in the TXFIFO to be sent then wait while the
|
||||
* transmiter is active.
|
||||
*/
|
||||
while ((regs->base.uartfr & PL011_UARTFR_TXFE) == 0 ||
|
||||
(regs->base.uartfr & PL011_UARTFR_BUSY) != 0) {
|
||||
/* Wait */
|
||||
}
|
||||
|
||||
regs->base.uartcr = PL011_UARTCR_UARTEN;
|
||||
/* Ignore baud rate of B0. There are no modem control lines to de-assert */
|
||||
if (baud > 0) {
|
||||
regs->base.uartibrd = ibauddiv;
|
||||
regs->base.uartfbrd = fbauddiv;
|
||||
}
|
||||
regs->base.uartlcr_h = mode;
|
||||
|
||||
/* Control: receive, transmit, uart enable, no CTS, no RTS, no loopback */
|
||||
regs->base.uartcr = PL011_UARTCR_RXE
|
||||
| PL011_UARTCR_TXE
|
||||
| PL011_UARTCR_UARTEN;
|
||||
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
versal_uart_intr_clearall(regs);
|
||||
versal_uart_intr_enable(regs, PL011_UARTI_RTI | PL011_UARTI_RXI);
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
const rtems_termios_device_handler versal_uart_handler = {
|
||||
.first_open = versal_uart_first_open,
|
||||
.set_attributes = versal_uart_set_attributes,
|
||||
.write = versal_uart_write_support,
|
||||
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
||||
.last_close = versal_uart_last_close,
|
||||
.mode = TERMIOS_IRQ_DRIVEN
|
||||
#else
|
||||
.poll_read = arm_pl011_read_polled,
|
||||
.mode = TERMIOS_POLLED
|
||||
#endif
|
||||
};
|
||||
@@ -1,94 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This header file provides the core BSP definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_VERSAL_BSP_H
|
||||
#define LIBBSP_AARCH64_XILINX_VERSAL_BSP_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#define BSP_RESET_SMC
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0xf9040000
|
||||
#define BSP_ARM_GIC_DIST_BASE 0xf9000000
|
||||
#define BSP_ARM_GIC_REDIST_BASE 0xf9080000
|
||||
|
||||
/*
|
||||
* DDRMC mapping
|
||||
*/
|
||||
LINKER_SYMBOL(bsp_r0_ram_base)
|
||||
LINKER_SYMBOL(bsp_r0_ram_end)
|
||||
LINKER_SYMBOL(bsp_r1_ram_base)
|
||||
LINKER_SYMBOL(bsp_r1_ram_end)
|
||||
|
||||
/**
|
||||
* @brief Versal specific set up of the MMU.
|
||||
*
|
||||
* Provide in the application to override the defaults in the BSP.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void versal_setup_mmu_and_cache(void);
|
||||
|
||||
void versal_debug_console_flush(void);
|
||||
|
||||
uint32_t versal_clock_i2c0(void);
|
||||
|
||||
uint32_t versal_clock_i2c1(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_VERSAL_BSP_H */
|
||||
@@ -1,64 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 Chris Johns <chris@contemporary.software>
|
||||
* Copyright (C) 2014 embedded brains GmbH & Co. KG
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_VERSAL_I2C_H
|
||||
#define LIBBSP_ARM_XILINX_VERSAL_I2C_H
|
||||
|
||||
#include <dev/i2c/cadence-i2c.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
static inline int versal_register_i2c_0(void)
|
||||
{
|
||||
return i2c_bus_register_cadence(
|
||||
"/dev/i2c-0",
|
||||
0x00FF020000,
|
||||
versal_clock_i2c0(),
|
||||
VERSAL_IRQ_I2C_0
|
||||
);
|
||||
}
|
||||
|
||||
static inline int versal_register_i2c_1(void)
|
||||
{
|
||||
return i2c_bus_register_cadence(
|
||||
"/dev/i2c-1",
|
||||
0x00FF030000,
|
||||
versal_clock_i2c1(),
|
||||
VERSAL_IRQ_I2C_1
|
||||
);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_VERSAL_I2C_H */
|
||||
@@ -1,74 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This header file provides the BSP's IRQ definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_VERSAL_IRQ_H
|
||||
#define LIBBSP_AARCH64_XILINX_VERSAL_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems/irq.h>
|
||||
#include <rtems/irq-extension.h>
|
||||
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT 1020
|
||||
|
||||
/* Interrupts vectors */
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_S_PPI 29
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define VERSAL_IRQ_I2C_0 46
|
||||
#define VERSAL_IRQ_I2C_1 47
|
||||
#define VERSAL_IRQ_UART_0 50
|
||||
#define VERSAL_IRQ_UART_1 51
|
||||
#define VERSAL_IRQ_ETHERNET_0 88
|
||||
#define VERSAL_IRQ_ETHERNET_0_WAKEUP 89
|
||||
#define VERSAL_IRQ_ETHERNET_1 90
|
||||
#define VERSAL_IRQ_ETHERNET_1_WAKEUP 91
|
||||
#define VERSAL_IRQ_QSPI 157
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_VERSAL_IRQ_H */
|
||||
@@ -1,41 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsArmXilinxVersal
|
||||
*
|
||||
* @brief This header file provides BSP-specific interfaces.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_XIL_COMPAT_H
|
||||
#define LIBBSP_ARM_XILINX_ZYNQMP_RPU_BSP_XIL_COMPAT_H
|
||||
|
||||
#include <bsp/xil-compat-common.h>
|
||||
|
||||
#endif
|
||||
@@ -1,73 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup versal_uart
|
||||
*
|
||||
* @brief Xilinx Versal UART support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_VERSAL_UART_H
|
||||
#define LIBBSP_ARM_XILINX_VERSAL_UART_H
|
||||
|
||||
#include <rtems/termiostypes.h>
|
||||
#include <dev/serial/arm-pl011.h>
|
||||
#include <dev/serial/arm-pl011-regs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @defgroup versal_uart Xilinx Versal UART Support
|
||||
* @ingroup RTEMSBSPsARMVersal
|
||||
* @brief UART Support
|
||||
*
|
||||
* This driver operates an instance of the Xilinx UART present in the
|
||||
* family of Xilinx Versal SoCs.
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
arm_pl011_context pl011_ctx;
|
||||
volatile bool transmitting;
|
||||
} versal_pl011_context;
|
||||
|
||||
extern const rtems_termios_device_handler versal_uart_handler;
|
||||
|
||||
#define VERSAL_UART_DEFAULT_BAUD 115200
|
||||
|
||||
int versal_uart_initialize(rtems_termios_device_context *base);
|
||||
|
||||
void versal_uart_reset_tx_flush(rtems_termios_device_context *base);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_VERSAL_UART_H */
|
||||
@@ -1,45 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This header file provides functionality for the tm27 test.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RTEMS_TMTEST27
|
||||
#error "This is an RTEMS internal file you must not include directly."
|
||||
#endif
|
||||
|
||||
#ifndef __tm27_h
|
||||
#define __tm27_h
|
||||
|
||||
#include <dev/irq/arm-gic-tm27.h>
|
||||
|
||||
#endif /* __tm27_h */
|
||||
@@ -1,60 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This source file contains the implementation of bsp_start().
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/bootcard.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/linker-symbols.h>
|
||||
|
||||
#include <rtems/score/basedefs.h>
|
||||
|
||||
RTEMS_WEAK uint32_t versal_clock_i2c0(void)
|
||||
{
|
||||
return VERSAL_CLOCK_I2C0;
|
||||
}
|
||||
|
||||
RTEMS_WEAK uint32_t versal_clock_i2c1(void)
|
||||
{
|
||||
return VERSAL_CLOCK_I2C1;
|
||||
}
|
||||
|
||||
void bsp_start( void )
|
||||
{
|
||||
bsp_interrupt_initialize();
|
||||
rtems_cache_coherent_add_area(
|
||||
bsp_section_nocacheheap_begin,
|
||||
(uintptr_t) bsp_section_nocacheheap_size
|
||||
);
|
||||
}
|
||||
@@ -1,54 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This source file contains the implementation of this BSP's startup
|
||||
* hooks.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/irq-generic.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#ifdef BSP_START_ENABLE_EL3_START_SUPPORT
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
|
||||
{
|
||||
bsp_interrupt_facility_initialize();
|
||||
}
|
||||
#endif
|
||||
|
||||
BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
|
||||
{
|
||||
AArch64_start_set_vector_base();
|
||||
bsp_start_copy_sections();
|
||||
versal_setup_mmu_and_cache();
|
||||
bsp_start_clear_bss();
|
||||
}
|
||||
@@ -1,136 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxVersal
|
||||
*
|
||||
* @brief This source file contains the default MMU tables and setup.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 Gedare Bloom <gedare@rtems.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/start.h>
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
#include <rtems/malloc.h>
|
||||
#include <rtems/sysinit.h>
|
||||
|
||||
BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
|
||||
versal_mmu_config_table[] = {
|
||||
AARCH64_MMU_DEFAULT_SECTIONS,
|
||||
{ /* Devices */
|
||||
.begin = 0xf1000000U,
|
||||
.end = 0xf2000000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, { /* APU GIC */
|
||||
.begin = 0xf9000000U,
|
||||
.end = 0xf90c0000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, { /* FPD CSRs */
|
||||
.begin = 0xfd000000U,
|
||||
.end = 0xfe000000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, { /* LPD CSRs */
|
||||
.begin = 0xfe000000U,
|
||||
.end = 0xfe800000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, { /* LPD IOP CSRs and LPD peripherals */
|
||||
.begin = 0xff000000U,
|
||||
.end = 0xffc00000U,
|
||||
.flags = AARCH64_MMU_DEVICE
|
||||
}, { /* DDRMC0_region1_mem, if not used size is 0 and ignored */
|
||||
.begin = (uintptr_t) bsp_r1_ram_base,
|
||||
.end = (uintptr_t) bsp_r1_ram_end,
|
||||
.flags = AARCH64_MMU_DATA_RW_CACHED
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
* Create an MMU table to get the R1 base and end. This avoids
|
||||
* relocation errors as the R1 addresses are in the upper A64 address
|
||||
* space.
|
||||
*
|
||||
* The versal_mmu_config_table table cannot be used because the regions
|
||||
* in that table have no identifiers to indicate which region is the
|
||||
* the DDRMC0_region1_mem region.
|
||||
*/
|
||||
static const struct mem_region {
|
||||
uintptr_t begin;
|
||||
uintptr_t end;
|
||||
} bsp_r1_region[] = {
|
||||
{ /* DDRMC0_region1_mem, if not used size is 0 and ignored */
|
||||
.begin = (uintptr_t) bsp_r1_ram_base,
|
||||
.end = (uintptr_t) bsp_r1_ram_end,
|
||||
}
|
||||
};
|
||||
|
||||
/*
|
||||
* Make weak and let the user override.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void
|
||||
versal_setup_mmu_and_cache( void ) __attribute__ ((weak));
|
||||
|
||||
BSP_START_TEXT_SECTION void
|
||||
versal_setup_mmu_and_cache( void )
|
||||
{
|
||||
aarch64_mmu_control *control = &aarch64_mmu_instance;
|
||||
|
||||
aarch64_mmu_setup();
|
||||
|
||||
aarch64_mmu_setup_translation_table(
|
||||
control,
|
||||
&versal_mmu_config_table[ 0 ],
|
||||
RTEMS_ARRAY_SIZE( versal_mmu_config_table )
|
||||
);
|
||||
|
||||
aarch64_mmu_enable( control );
|
||||
}
|
||||
|
||||
void bsp_r1_heap_extend(void);
|
||||
void bsp_r1_heap_extend(void)
|
||||
{
|
||||
const struct mem_region* r1 = &bsp_r1_region[0];
|
||||
if (r1->begin != r1->end) {
|
||||
rtems_status_code sc =
|
||||
rtems_heap_extend((void*) r1->begin, r1->end - r1->begin);
|
||||
if (sc != RTEMS_SUCCESSFUL) {
|
||||
bsp_fatal(BSP_FATAL_HEAP_EXTEND_ERROR);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise after the IDLE thread exists so the protected heap
|
||||
* extend call has a valid context.
|
||||
*/
|
||||
RTEMS_SYSINIT_ITEM(
|
||||
bsp_r1_heap_extend,
|
||||
RTEMS_SYSINIT_IDLE_THREADS,
|
||||
RTEMS_SYSINIT_ORDER_LAST
|
||||
);
|
||||
@@ -1,105 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains this BSP's console configuration.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <rtems/console.h>
|
||||
#include <rtems/endian.h>
|
||||
#include <rtems/sysinit.h>
|
||||
#include <rtems/termiostypes.h>
|
||||
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <bsp/fdt.h>
|
||||
#include <bsp/irq.h>
|
||||
|
||||
#include <dev/serial/zynq-uart.h>
|
||||
#include <dev/serial/zynq-uart-regs.h>
|
||||
|
||||
#include <bspopts.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
#include <libchip/ns16550.h>
|
||||
|
||||
static zynq_uart_context zynqmp_uart_instances[2] = {
|
||||
{
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
|
||||
.regs = (volatile zynq_uart *) ZYNQ_UART_0_BASE_ADDR,
|
||||
.irq = ZYNQMP_IRQ_UART_0
|
||||
}, {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
|
||||
.regs = (volatile zynq_uart *) ZYNQ_UART_1_BASE_ADDR,
|
||||
.irq = ZYNQMP_IRQ_UART_1
|
||||
}
|
||||
};
|
||||
|
||||
rtems_status_code console_initialize(
|
||||
rtems_device_major_number major,
|
||||
rtems_device_minor_number minor,
|
||||
void *arg
|
||||
)
|
||||
{
|
||||
(void) major;
|
||||
(void) minor;
|
||||
(void) arg;
|
||||
|
||||
size_t i;
|
||||
|
||||
rtems_termios_initialize();
|
||||
|
||||
for (i = 0; i < RTEMS_ARRAY_SIZE(zynqmp_uart_instances); ++i) {
|
||||
zynq_uart_context *ctx = &zynqmp_uart_instances[i];
|
||||
char uart[] = "/dev/ttySX";
|
||||
|
||||
uart[sizeof(uart) - 2] = (char) ('0' + i);
|
||||
rtems_termios_device_install(
|
||||
&uart[0],
|
||||
&zynq_uart_handler,
|
||||
NULL,
|
||||
&ctx->base
|
||||
);
|
||||
|
||||
if (ctx->regs == (zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR) {
|
||||
link(&uart[0], CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
}
|
||||
|
||||
zynqmp_management_console_termios_init();
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
void zynqmp_debug_console_flush(void)
|
||||
{
|
||||
zynq_uart_reset_tx_flush((zynq_uart *) ZYNQ_UART_KERNEL_IO_BASE_ADDR);
|
||||
}
|
||||
@@ -1,41 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the management console implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
|
||||
void zynqmp_management_console_termios_init(void)
|
||||
{
|
||||
}
|
||||
@@ -1,190 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the management console implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp/aarch64-mmu.h>
|
||||
#include <bsp/fdt.h>
|
||||
|
||||
#include <libchip/ns16550.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
#include <rtems/endian.h>
|
||||
#include <rtems/sysinit.h>
|
||||
|
||||
uint32_t mgmt_uart_reg_shift = 0;
|
||||
|
||||
static uint8_t get_register(uintptr_t addr, uint8_t i)
|
||||
{
|
||||
volatile uint8_t *reg = (uint8_t *) addr;
|
||||
|
||||
i <<= mgmt_uart_reg_shift;
|
||||
return reg [i];
|
||||
}
|
||||
|
||||
static void set_register(uintptr_t addr, uint8_t i, uint8_t val)
|
||||
{
|
||||
volatile uint8_t *reg = (uint8_t *) addr;
|
||||
|
||||
i <<= mgmt_uart_reg_shift;
|
||||
reg [i] = val;
|
||||
}
|
||||
|
||||
static ns16550_context zynqmp_mgmt_uart_context = {
|
||||
.base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Management UART 0"),
|
||||
.get_reg = get_register,
|
||||
.set_reg = set_register,
|
||||
.port = 0,
|
||||
.irq = 0,
|
||||
.clock = 0,
|
||||
.initial_baud = 0,
|
||||
};
|
||||
|
||||
__attribute__ ((weak)) void zynqmp_configure_management_console(rtems_termios_device_context *base)
|
||||
{
|
||||
/* This SLIP-encoded watchdog command sets timeouts to 0xFFFFFFFF seconds. */
|
||||
const char mgmt_watchdog_cmd[] =
|
||||
"\xc0\xda\x00\x00\xff\xff\xff\xff\xff\x00\xff\xff\xff\xffM#\xc0";
|
||||
|
||||
/* Send the system watchdog configuration command */
|
||||
for (int i = 0; i < sizeof(mgmt_watchdog_cmd); i++) {
|
||||
ns16550_polled_putchar(base, mgmt_watchdog_cmd[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static void zynqmp_management_console_init(void)
|
||||
{
|
||||
/* Find the management console in the device tree */
|
||||
const void *fdt = bsp_fdt_get();
|
||||
const uint32_t *prop;
|
||||
uint32_t outprop[4];
|
||||
int proplen;
|
||||
int node;
|
||||
|
||||
const char *alias = fdt_get_alias(fdt, "mgmtport");
|
||||
if (alias == NULL) {
|
||||
return;
|
||||
}
|
||||
node = fdt_path_offset(fdt, alias);
|
||||
|
||||
prop = fdt_getprop(fdt, node, "clock-frequency", &proplen);
|
||||
if ( prop == NULL || proplen != 4 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
zynqmp_mgmt_uart_context.clock = outprop[0];
|
||||
|
||||
prop = fdt_getprop(fdt, node, "current-speed", &proplen);
|
||||
if ( prop == NULL || proplen != 4 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
zynqmp_mgmt_uart_context.initial_baud = outprop[0];
|
||||
|
||||
prop = fdt_getprop(fdt, node, "interrupts", &proplen);
|
||||
if ( prop == NULL || proplen != 12 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
outprop[1] = rtems_uint32_from_big_endian((const uint8_t *) &prop[1]);
|
||||
outprop[2] = rtems_uint32_from_big_endian((const uint8_t *) &prop[2]);
|
||||
/* proplen is in bytes, interrupt mapping expects a length in 32-bit cells */
|
||||
zynqmp_mgmt_uart_context.irq = bsp_fdt_map_intr(outprop, proplen / 4);
|
||||
if ( zynqmp_mgmt_uart_context.irq == 0 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
prop = fdt_getprop(fdt, node, "reg", &proplen);
|
||||
if ( prop == NULL || proplen != 16 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
outprop[1] = rtems_uint32_from_big_endian((const uint8_t *) &prop[1]);
|
||||
outprop[2] = rtems_uint32_from_big_endian((const uint8_t *) &prop[2]);
|
||||
outprop[3] = rtems_uint32_from_big_endian((const uint8_t *) &prop[3]);
|
||||
zynqmp_mgmt_uart_context.port = ( ( (uint64_t) outprop[0] ) << 32 ) | outprop[1];
|
||||
uintptr_t uart_base = zynqmp_mgmt_uart_context.port;
|
||||
size_t uart_size = ( ( (uint64_t) outprop[2] ) << 32 ) | outprop[3];
|
||||
|
||||
rtems_status_code sc = aarch64_mmu_map( uart_base,
|
||||
uart_size,
|
||||
AARCH64_MMU_DEVICE);
|
||||
if ( sc != RTEMS_SUCCESSFUL ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
prop = fdt_getprop(fdt, node, "reg-offset", &proplen);
|
||||
if ( prop == NULL || proplen != 4 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
zynqmp_mgmt_uart_context.port += outprop[0];
|
||||
|
||||
prop = fdt_getprop(fdt, node, "reg-shift", &proplen);
|
||||
if ( prop == NULL || proplen != 4 ) {
|
||||
zynqmp_mgmt_uart_context.port = 0;
|
||||
return;
|
||||
}
|
||||
outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
|
||||
mgmt_uart_reg_shift = outprop[0];
|
||||
|
||||
ns16550_probe(&zynqmp_mgmt_uart_context.base);
|
||||
|
||||
zynqmp_configure_management_console(&zynqmp_mgmt_uart_context.base);
|
||||
}
|
||||
|
||||
RTEMS_SYSINIT_ITEM(
|
||||
zynqmp_management_console_init,
|
||||
RTEMS_SYSINIT_BSP_START,
|
||||
RTEMS_SYSINIT_ORDER_FIRST
|
||||
);
|
||||
|
||||
void zynqmp_management_console_termios_init(void)
|
||||
{
|
||||
if ( zynqmp_mgmt_uart_context.port != 0 ) {
|
||||
rtems_termios_device_install(
|
||||
"/dev/ttyMGMT0",
|
||||
&ns16550_handler_interrupt,
|
||||
NULL,
|
||||
&zynqmp_mgmt_uart_context.base
|
||||
);
|
||||
}
|
||||
}
|
||||
@@ -1,129 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the implementation of zynqmp_ecc_init().
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/ecc_priv.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <rtems/score/aarch64-system-registers.h>
|
||||
|
||||
static Cache_Error_RAM_ID get_l1_ramid(uint64_t ramid)
|
||||
{
|
||||
switch (ramid) {
|
||||
case 0x0:
|
||||
return RAM_ID_L1I_TAG;
|
||||
case 0x1:
|
||||
return RAM_ID_L1I_DATA;
|
||||
case 0x8:
|
||||
return RAM_ID_L1D_TAG;
|
||||
case 0x9:
|
||||
return RAM_ID_L1D_DATA;
|
||||
case 0xa:
|
||||
return RAM_ID_L1D_DIRTY;
|
||||
case 0x18:
|
||||
return RAM_ID_TLB;
|
||||
default:
|
||||
return RAM_ID_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
static Cache_Error_RAM_ID get_l2_ramid(uint64_t ramid)
|
||||
{
|
||||
switch (ramid) {
|
||||
case 0x10:
|
||||
return RAM_ID_L2_TAG;
|
||||
case 0x11:
|
||||
return RAM_ID_L2_DATA;
|
||||
case 0x12:
|
||||
return RAM_ID_SCU;
|
||||
default:
|
||||
return RAM_ID_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
static void cache_handler(void *arg)
|
||||
{
|
||||
uint64_t l1val = _AArch64_Read_cpumerrsr_el1();
|
||||
_AArch64_Write_cpumerrsr_el1(l1val);
|
||||
uint64_t l2val = _AArch64_Read_l2merrsr_el1();
|
||||
_AArch64_Write_l2merrsr_el1(l2val);
|
||||
|
||||
(void) arg;
|
||||
|
||||
if (l1val & AARCH64_CPUMERRSR_EL1_VALID) {
|
||||
/* parse L1 data */
|
||||
Cache_Error_Info cerr = {0, };
|
||||
cerr.abort = l1val & AARCH64_CPUMERRSR_EL1_FATAL;
|
||||
cerr.repeats = AARCH64_CPUMERRSR_EL1_REPEATERR_GET(l1val);
|
||||
cerr.other_errors = AARCH64_CPUMERRSR_EL1_OTHERERR_GET(l1val);
|
||||
cerr.ramid = get_l1_ramid(AARCH64_CPUMERRSR_EL1_RAMID_GET(l1val));
|
||||
cerr.segment = AARCH64_CPUMERRSR_EL1_CPUIDWAY_GET(l1val);
|
||||
cerr.address = AARCH64_CPUMERRSR_EL1_ADDR_GET(l1val);
|
||||
|
||||
zynqmp_invoke_ecc_handler(L1_CACHE, &cerr);
|
||||
}
|
||||
|
||||
if (l2val & AARCH64_L2MERRSR_EL1_VALID) {
|
||||
/* parse L2 data */
|
||||
Cache_Error_Info cerr = {0, };
|
||||
cerr.abort = l2val & AARCH64_L2MERRSR_EL1_FATAL;
|
||||
cerr.repeats = AARCH64_L2MERRSR_EL1_REPEATERR_GET(l2val);
|
||||
cerr.other_errors = AARCH64_L2MERRSR_EL1_OTHERERR_GET(l2val);
|
||||
cerr.ramid = get_l2_ramid(AARCH64_L2MERRSR_EL1_RAMID_GET(l2val));
|
||||
cerr.segment = AARCH64_L2MERRSR_EL1_CPUIDWAY_GET(l2val);
|
||||
cerr.address = AARCH64_L2MERRSR_EL1_ADDR_GET(l2val);
|
||||
|
||||
zynqmp_invoke_ecc_handler(L2_CACHE, &cerr);
|
||||
}
|
||||
}
|
||||
|
||||
static rtems_interrupt_entry zynqmp_cache_ecc_entry;
|
||||
|
||||
rtems_status_code zynqmp_configure_cache_ecc( void )
|
||||
{
|
||||
rtems_interrupt_entry_initialize(
|
||||
&zynqmp_cache_ecc_entry,
|
||||
cache_handler,
|
||||
NULL,
|
||||
"L1/L2 Cache Errors"
|
||||
);
|
||||
|
||||
return rtems_interrupt_entry_install(
|
||||
ZYNQMP_IRQ_CACHE,
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
&zynqmp_cache_ecc_entry
|
||||
);
|
||||
}
|
||||
@@ -1,906 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the implementation of DDR ECC support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/ecc_priv.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <rtems/rtems/intr.h>
|
||||
|
||||
static uintptr_t ddrc_base = 0xFD070000;
|
||||
|
||||
/*
|
||||
* The upper value expressable by the bits in a field is sometimes used to
|
||||
* indicate different things
|
||||
*/
|
||||
#define DDRC_ADDRMAP_4BIT_SPECIAL 15
|
||||
#define DDRC_ADDRMAP_5BIT_SPECIAL 31
|
||||
|
||||
#define DDRC_MSTR_OFFSET 0x0
|
||||
#define DDRC_MSTR_BURST_RDWR(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_MSTR_BURST_RDWR_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_MSTR_BURST_RDWR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_MSTR_BURST_RDWR_4 0x2
|
||||
#define DDRC_MSTR_BURST_RDWR_8 0x4
|
||||
#define DDRC_MSTR_BURST_RDWR_16 0x8
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH(val) BSP_FLD32(val, 12, 13)
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH_GET(reg) BSP_FLD32GET(reg, 12, 13)
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13)
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH_FULL 0x0
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH_HALF 0x1
|
||||
#define DDRC_MSTR_DATA_BUS_WIDTH_QUARTER 0x2
|
||||
#define DDRC_MSTR_LPDDR4 BSP_BIT32(5)
|
||||
#define DDRC_MSTR_DDR4 BSP_BIT32(4)
|
||||
#define DDRC_MSTR_LPDDR3 BSP_BIT32(3)
|
||||
#define DDRC_MSTR_DDR3 BSP_BIT32(0)
|
||||
|
||||
/* Address map definitions, DDR4 variant with full bus width expected */
|
||||
#define DDRC_ADDRMAP0_OFFSET 0x200
|
||||
#define DDRC_ADDRMAP0_RANK_B0_BASE 6
|
||||
#define DDRC_ADDRMAP0_RANK_B0_TARGET_BIT(bw, lp3) 0
|
||||
#define DDRC_ADDRMAP0_RANK_B0_TARGET rank
|
||||
#define DDRC_ADDRMAP0_RANK_B0_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP0_RANK_B0(val) BSP_FLD32(val, 0, 4)
|
||||
#define DDRC_ADDRMAP0_RANK_B0_GET(reg) BSP_FLD32GET(reg, 0, 4)
|
||||
#define DDRC_ADDRMAP0_RANK_B0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
|
||||
|
||||
#define DDRC_ADDRMAP1_OFFSET 0x204
|
||||
#define DDRC_ADDRMAP1_BANK_B2_BASE 4
|
||||
#define DDRC_ADDRMAP1_BANK_B2_TARGET_BIT(bw, lp3) 2
|
||||
#define DDRC_ADDRMAP1_BANK_B2_TARGET bank
|
||||
#define DDRC_ADDRMAP1_BANK_B2_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP1_BANK_B2(val) BSP_FLD32(val, 16, 20)
|
||||
#define DDRC_ADDRMAP1_BANK_B2_GET(reg) BSP_FLD32GET(reg, 16, 20)
|
||||
#define DDRC_ADDRMAP1_BANK_B2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
|
||||
#define DDRC_ADDRMAP1_BANK_B1_BASE 3
|
||||
#define DDRC_ADDRMAP1_BANK_B1_TARGET_BIT(bw, lp3) 1
|
||||
#define DDRC_ADDRMAP1_BANK_B1_TARGET bank
|
||||
#define DDRC_ADDRMAP1_BANK_B1_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP1_BANK_B1(val) BSP_FLD32(val, 8, 12)
|
||||
#define DDRC_ADDRMAP1_BANK_B1_GET(reg) BSP_FLD32GET(reg, 8, 12)
|
||||
#define DDRC_ADDRMAP1_BANK_B1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
|
||||
#define DDRC_ADDRMAP1_BANK_B0_BASE 2
|
||||
#define DDRC_ADDRMAP1_BANK_B0_TARGET_BIT(bw, lp3) 0
|
||||
#define DDRC_ADDRMAP1_BANK_B0_TARGET bank
|
||||
#define DDRC_ADDRMAP1_BANK_B0_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP1_BANK_B0(val) BSP_FLD32(val, 0, 4)
|
||||
#define DDRC_ADDRMAP1_BANK_B0_GET(reg) BSP_FLD32GET(reg, 0, 4)
|
||||
#define DDRC_ADDRMAP1_BANK_B0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
|
||||
|
||||
#define DDRC_ADDRMAP2_OFFSET 0x208
|
||||
#define DDRC_ADDRMAP2_COL_B5_BASE 5
|
||||
#define DDRC_ADDRMAP2_COL_B5_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
5 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 6 : 7))
|
||||
#define DDRC_ADDRMAP2_COL_B5_TARGET column
|
||||
#define DDRC_ADDRMAP2_COL_B5_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP2_COL_B5(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP2_COL_B5_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP2_COL_B5_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
#define DDRC_ADDRMAP2_COL_B4_BASE 4
|
||||
#define DDRC_ADDRMAP2_COL_B4_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
4 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 5 : 6))
|
||||
#define DDRC_ADDRMAP2_COL_B4_TARGET column
|
||||
#define DDRC_ADDRMAP2_COL_B4_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP2_COL_B4(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP2_COL_B4_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP2_COL_B4_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP2_COL_B3_BASE 3
|
||||
#define DDRC_ADDRMAP2_COL_B3_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
3 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 4 : 5 ))
|
||||
#define DDRC_ADDRMAP2_COL_B3_TARGET column
|
||||
#define DDRC_ADDRMAP2_COL_B3_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP2_COL_B3(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP2_COL_B3_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP2_COL_B3_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP2_COL_B2_BASE 2
|
||||
#define DDRC_ADDRMAP2_COL_B2_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
2 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 3 : 4))
|
||||
#define DDRC_ADDRMAP2_COL_B2_TARGET column
|
||||
#define DDRC_ADDRMAP2_COL_B2_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP2_COL_B2(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP2_COL_B2_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP2_COL_B2_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP3_OFFSET 0x20c
|
||||
#define DDRC_ADDRMAP3_COL_B9_BASE 9
|
||||
static uint32_t map3_col_b9_target_bit(uint32_t bw, bool lp3)
|
||||
{
|
||||
if (bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) {
|
||||
return 9;
|
||||
}
|
||||
|
||||
if (bw == DDRC_MSTR_DATA_BUS_WIDTH_QUARTER) {
|
||||
return 13;
|
||||
}
|
||||
|
||||
if (lp3) {
|
||||
return 10;
|
||||
}
|
||||
|
||||
return 11;
|
||||
}
|
||||
#define DDRC_ADDRMAP3_COL_B9_TARGET_BIT(bw, lp3) \
|
||||
map3_col_b9_target_bit(bw, lp3)
|
||||
#define DDRC_ADDRMAP3_COL_B9_TARGET column
|
||||
#define DDRC_ADDRMAP3_COL_B9_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP3_COL_B9(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP3_COL_B9_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP3_COL_B9_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
#define DDRC_ADDRMAP3_COL_B8_BASE 8
|
||||
#define DDRC_ADDRMAP3_COL_B8_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
8 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 9 : 11))
|
||||
#define DDRC_ADDRMAP3_COL_B8_TARGET column
|
||||
#define DDRC_ADDRMAP3_COL_B8_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP3_COL_B8(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP3_COL_B8_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP3_COL_B8_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP3_COL_B7_BASE 7
|
||||
#define DDRC_ADDRMAP3_COL_B7_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
7 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 8 : 9))
|
||||
#define DDRC_ADDRMAP3_COL_B7_TARGET column
|
||||
#define DDRC_ADDRMAP3_COL_B7_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP3_COL_B7(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP3_COL_B7_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP3_COL_B7_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP3_COL_B6_BASE 6
|
||||
#define DDRC_ADDRMAP3_COL_B6_TARGET_BIT(bw, lp3) \
|
||||
((bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) ? \
|
||||
6 : ((bw == DDRC_MSTR_DATA_BUS_WIDTH_HALF) ? 7 : 8))
|
||||
#define DDRC_ADDRMAP3_COL_B6_TARGET column
|
||||
#define DDRC_ADDRMAP3_COL_B6_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP3_COL_B6(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP3_COL_B6_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP3_COL_B6_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP4_OFFSET 0x210
|
||||
#define DDRC_ADDRMAP4_COL_B11_BASE 11
|
||||
#define DDRC_ADDRMAP4_COL_B11_TARGET_BIT(bw, lp3) \
|
||||
(lp3?11:13)
|
||||
#define DDRC_ADDRMAP4_COL_B11_TARGET column
|
||||
#define DDRC_ADDRMAP4_COL_B11_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP4_COL_B11(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP4_COL_B11_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP4_COL_B11_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP4_COL_B10_BASE 10
|
||||
static uint32_t map4_col_b10_target_bit(uint32_t bw, bool lp3)
|
||||
{
|
||||
if (bw == DDRC_MSTR_DATA_BUS_WIDTH_FULL) {
|
||||
if (lp3) {
|
||||
return 10;
|
||||
}
|
||||
return 11;
|
||||
}
|
||||
|
||||
/* QUARTER bus mode not valid */
|
||||
if (lp3) {
|
||||
return 11;
|
||||
}
|
||||
|
||||
return 13;
|
||||
}
|
||||
#define DDRC_ADDRMAP4_COL_B10_TARGET_BIT(bw, lp3) \
|
||||
map4_col_b10_target_bit(bw, lp3)
|
||||
#define DDRC_ADDRMAP4_COL_B10_TARGET column
|
||||
#define DDRC_ADDRMAP4_COL_B10_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP4_COL_B10(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP4_COL_B10_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP4_COL_B10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP5_OFFSET 0x214
|
||||
#define DDRC_ADDRMAP5_ROW_B11_BASE 17
|
||||
#define DDRC_ADDRMAP5_ROW_B11_TARGET_BIT(bw, lp3) 11
|
||||
#define DDRC_ADDRMAP5_ROW_B11_TARGET row
|
||||
#define DDRC_ADDRMAP5_ROW_B11_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP5_ROW_B11(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP5_ROW_B11_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP5_ROW_B11_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
/* This gets mapped into ADDRMAP[9,10,11] */
|
||||
#define DDRC_ADDRMAP5_ROW_B2_10(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP5_ROW_B2_10_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP5_ROW_B2_10_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP5_ROW_B1_BASE 7
|
||||
#define DDRC_ADDRMAP5_ROW_B1_TARGET_BIT(bw, lp3) 1
|
||||
#define DDRC_ADDRMAP5_ROW_B1_TARGET row
|
||||
#define DDRC_ADDRMAP5_ROW_B1_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP5_ROW_B1(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP5_ROW_B1_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP5_ROW_B1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP5_ROW_B0_BASE 6
|
||||
#define DDRC_ADDRMAP5_ROW_B0_TARGET_BIT(bw, lp3) 0
|
||||
#define DDRC_ADDRMAP5_ROW_B0_TARGET row
|
||||
#define DDRC_ADDRMAP5_ROW_B0_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP5_ROW_B0(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP5_ROW_B0_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP5_ROW_B0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP6_OFFSET 0x218
|
||||
#define DDRC_ADDRMAP6_LPDDR3_6_12 BSP_BIT(bw, lp3)32(31)
|
||||
#define DDRC_ADDRMAP6_ROW_B15_BASE 21
|
||||
#define DDRC_ADDRMAP6_ROW_B15_TARGET_BIT(bw, lp3) 15
|
||||
#define DDRC_ADDRMAP6_ROW_B15_TARGET row
|
||||
#define DDRC_ADDRMAP6_ROW_B15_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP6_ROW_B15(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP6_ROW_B15_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP6_ROW_B15_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
#define DDRC_ADDRMAP6_ROW_B14_BASE 20
|
||||
#define DDRC_ADDRMAP6_ROW_B14_TARGET_BIT(bw, lp3) 14
|
||||
#define DDRC_ADDRMAP6_ROW_B14_TARGET row
|
||||
#define DDRC_ADDRMAP6_ROW_B14_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP6_ROW_B14(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP6_ROW_B14_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP6_ROW_B14_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP6_ROW_B13_BASE 19
|
||||
#define DDRC_ADDRMAP6_ROW_B13_TARGET_BIT(bw, lp3) 13
|
||||
#define DDRC_ADDRMAP6_ROW_B13_TARGET row
|
||||
#define DDRC_ADDRMAP6_ROW_B13_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP6_ROW_B13(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP6_ROW_B13_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP6_ROW_B13_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP6_ROW_B12_BASE 18
|
||||
#define DDRC_ADDRMAP6_ROW_B12_TARGET_BIT(bw, lp3) 12
|
||||
#define DDRC_ADDRMAP6_ROW_B12_TARGET row
|
||||
#define DDRC_ADDRMAP6_ROW_B12_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP6_ROW_B12(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP6_ROW_B12_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP6_ROW_B12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP7_OFFSET 0x21c
|
||||
#define DDRC_ADDRMAP7_ROW_B17_BASE 23
|
||||
#define DDRC_ADDRMAP7_ROW_B17_TARGET_BIT(bw, lp3) 17
|
||||
#define DDRC_ADDRMAP7_ROW_B17_TARGET row
|
||||
#define DDRC_ADDRMAP7_ROW_B17_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP7_ROW_B17(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP7_ROW_B17_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP7_ROW_B17_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP7_ROW_B16_BASE 22
|
||||
#define DDRC_ADDRMAP7_ROW_B16_TARGET_BIT(bw, lp3) 16
|
||||
#define DDRC_ADDRMAP7_ROW_B16_TARGET row
|
||||
#define DDRC_ADDRMAP7_ROW_B16_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP7_ROW_B16(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP7_ROW_B16_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP7_ROW_B16_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP8_OFFSET 0x220
|
||||
#define DDRC_ADDRMAP8_BG_B1_BASE 3
|
||||
#define DDRC_ADDRMAP8_BG_B1_TARGET_BIT(bw, lp3) 1
|
||||
#define DDRC_ADDRMAP8_BG_B1_TARGET bank_group
|
||||
#define DDRC_ADDRMAP8_BG_B1_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP8_BG_B1(val) BSP_FLD32(val, 8, 12)
|
||||
#define DDRC_ADDRMAP8_BG_B1_GET(reg) BSP_FLD32GET(reg, 8, 12)
|
||||
#define DDRC_ADDRMAP8_BG_B1_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
|
||||
#define DDRC_ADDRMAP8_BG_B0_BASE 2
|
||||
#define DDRC_ADDRMAP8_BG_B0_TARGET_BIT(bw, lp3) 0
|
||||
#define DDRC_ADDRMAP8_BG_B0_TARGET bank_group
|
||||
#define DDRC_ADDRMAP8_BG_B0_SPECIAL DDRC_ADDRMAP_5BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP8_BG_B0(val) BSP_FLD32(val, 0, 4)
|
||||
#define DDRC_ADDRMAP8_BG_B0_GET(reg) BSP_FLD32GET(reg, 0, 4)
|
||||
#define DDRC_ADDRMAP8_BG_B0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
|
||||
|
||||
#define DDRC_ADDRMAP9_OFFSET 0x224
|
||||
#define DDRC_ADDRMAP9_ROW_B5_BASE 11
|
||||
#define DDRC_ADDRMAP9_ROW_B5_TARGET_BIT(bw, lp3) 5
|
||||
#define DDRC_ADDRMAP9_ROW_B5_TARGET row
|
||||
#define DDRC_ADDRMAP9_ROW_B5_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP9_ROW_B5(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP9_ROW_B5_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP9_ROW_B5_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
#define DDRC_ADDRMAP9_ROW_B4_BASE 10
|
||||
#define DDRC_ADDRMAP9_ROW_B4_TARGET_BIT(bw, lp3) 4
|
||||
#define DDRC_ADDRMAP9_ROW_B4_TARGET row
|
||||
#define DDRC_ADDRMAP9_ROW_B4_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP9_ROW_B4(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP9_ROW_B4_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP9_ROW_B4_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP9_ROW_B3_BASE 9
|
||||
#define DDRC_ADDRMAP9_ROW_B3_TARGET_BIT(bw, lp3) 3
|
||||
#define DDRC_ADDRMAP9_ROW_B3_TARGET row
|
||||
#define DDRC_ADDRMAP9_ROW_B3_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP9_ROW_B3(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP9_ROW_B3_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP9_ROW_B3_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP9_ROW_B2_BASE 8
|
||||
#define DDRC_ADDRMAP9_ROW_B2_TARGET_BIT(bw, lp3) 2
|
||||
#define DDRC_ADDRMAP9_ROW_B2_TARGET row
|
||||
#define DDRC_ADDRMAP9_ROW_B2_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP9_ROW_B2(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP9_ROW_B2_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP9_ROW_B2_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP10_OFFSET 0x228
|
||||
#define DDRC_ADDRMAP10_ROW_B9_BASE 15
|
||||
#define DDRC_ADDRMAP10_ROW_B9_TARGET_BIT(bw, lp3) 9
|
||||
#define DDRC_ADDRMAP10_ROW_B9_TARGET row
|
||||
#define DDRC_ADDRMAP10_ROW_B9_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP10_ROW_B9(val) BSP_FLD32(val, 24, 27)
|
||||
#define DDRC_ADDRMAP10_ROW_B9_GET(reg) BSP_FLD32GET(reg, 24, 27)
|
||||
#define DDRC_ADDRMAP10_ROW_B9_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
|
||||
#define DDRC_ADDRMAP10_ROW_B8_BASE 14
|
||||
#define DDRC_ADDRMAP10_ROW_B8_TARGET_BIT(bw, lp3) 8
|
||||
#define DDRC_ADDRMAP10_ROW_B8_TARGET row
|
||||
#define DDRC_ADDRMAP10_ROW_B8_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP10_ROW_B8(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ADDRMAP10_ROW_B8_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ADDRMAP10_ROW_B8_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ADDRMAP10_ROW_B7_BASE 13
|
||||
#define DDRC_ADDRMAP10_ROW_B7_TARGET_BIT(bw, lp3) 7
|
||||
#define DDRC_ADDRMAP10_ROW_B7_TARGET row
|
||||
#define DDRC_ADDRMAP10_ROW_B7_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP10_ROW_B7(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ADDRMAP10_ROW_B7_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ADDRMAP10_ROW_B7_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ADDRMAP10_ROW_B6_BASE 12
|
||||
#define DDRC_ADDRMAP10_ROW_B6_TARGET_BIT(bw, lp3) 6
|
||||
#define DDRC_ADDRMAP10_ROW_B6_TARGET row
|
||||
#define DDRC_ADDRMAP10_ROW_B6_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP10_ROW_B6(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP10_ROW_B6_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP10_ROW_B6_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ADDRMAP11_OFFSET 0x22c
|
||||
#define DDRC_ADDRMAP11_ROW_B10_BASE 16
|
||||
#define DDRC_ADDRMAP11_ROW_B10_TARGET_BIT(bw, lp3) 10
|
||||
#define DDRC_ADDRMAP11_ROW_B10_TARGET row
|
||||
#define DDRC_ADDRMAP11_ROW_B10_SPECIAL DDRC_ADDRMAP_4BIT_SPECIAL
|
||||
#define DDRC_ADDRMAP11_ROW_B10(val) BSP_FLD32(val, 0, 3)
|
||||
#define DDRC_ADDRMAP11_ROW_B10_GET(reg) BSP_FLD32GET(reg, 0, 3)
|
||||
#define DDRC_ADDRMAP11_ROW_B10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
|
||||
|
||||
#define DDRC_ECCPOISONADDR0_OFFSET 0xB8
|
||||
#define DDRC_ECCPOISONADDR0_RANK BSP_BIT32(24)
|
||||
#define DDRC_ECCPOISONADDR0_COL(val) BSP_FLD32(val, 0, 11)
|
||||
#define DDRC_ECCPOISONADDR0_COL_GET(reg) BSP_FLD32GET(reg, 0, 11)
|
||||
#define DDRC_ECCPOISONADDR0_COL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
|
||||
|
||||
#define DDRC_ECCPOISONADDR1_OFFSET 0xBC
|
||||
#define DDRC_ECCPOISONADDR1_BG(val) BSP_FLD32(val, 28, 29)
|
||||
#define DDRC_ECCPOISONADDR1_BG_GET(reg) BSP_FLD32GET(reg, 28, 29)
|
||||
#define DDRC_ECCPOISONADDR1_BG_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29)
|
||||
#define DDRC_ECCPOISONADDR1_BANK(val) BSP_FLD32(val, 24, 26)
|
||||
#define DDRC_ECCPOISONADDR1_BANK_GET(reg) BSP_FLD32GET(reg, 24, 26)
|
||||
#define DDRC_ECCPOISONADDR1_BANK_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
|
||||
#define DDRC_ECCPOISONADDR1_ROW(val) BSP_FLD32(val, 0, 17)
|
||||
#define DDRC_ECCPOISONADDR1_ROW_GET(reg) BSP_FLD32GET(reg, 0, 17)
|
||||
#define DDRC_ECCPOISONADDR1_ROW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
|
||||
|
||||
static void homogenize_row(
|
||||
uint32_t *addrmap5,
|
||||
uint32_t *addrmap9,
|
||||
uint32_t *addrmap10,
|
||||
uint32_t *addrmap11
|
||||
)
|
||||
{
|
||||
uint32_t b2_10 = DDRC_ADDRMAP5_ROW_B2_10_GET(*addrmap5);
|
||||
if (b2_10 == DDRC_ADDRMAP_4BIT_SPECIAL) {
|
||||
/* ADDRMAP[9,10,11] already define row[2:10] correctly */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Translate b2_10 to ADDRMAP[9,10,11] to simplify future code */
|
||||
*addrmap9 = DDRC_ADDRMAP9_ROW_B5_SET(*addrmap9, b2_10);
|
||||
*addrmap9 = DDRC_ADDRMAP9_ROW_B4_SET(*addrmap9, b2_10);
|
||||
*addrmap9 = DDRC_ADDRMAP9_ROW_B3_SET(*addrmap9, b2_10);
|
||||
*addrmap9 = DDRC_ADDRMAP9_ROW_B2_SET(*addrmap9, b2_10);
|
||||
|
||||
*addrmap10 = DDRC_ADDRMAP10_ROW_B9_SET(*addrmap10, b2_10);
|
||||
*addrmap10 = DDRC_ADDRMAP10_ROW_B8_SET(*addrmap10, b2_10);
|
||||
*addrmap10 = DDRC_ADDRMAP10_ROW_B7_SET(*addrmap10, b2_10);
|
||||
*addrmap10 = DDRC_ADDRMAP10_ROW_B6_SET(*addrmap10, b2_10);
|
||||
|
||||
*addrmap11 = DDRC_ADDRMAP11_ROW_B10_SET(*addrmap11, b2_10);
|
||||
}
|
||||
|
||||
#define DDRC_READ(offset) (*(uint32_t *)(ddrc_base + offset))
|
||||
|
||||
#define DDRC_MAP_BIT(value, source, target) ((value >> source) & 0x1) << target
|
||||
|
||||
#define DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, BIT_ID, info, addrmap) \
|
||||
({ \
|
||||
uint32_t mapbit = DDRC_ ## BIT_ID ## _GET(addrmap); \
|
||||
uint32_t target_bit = DDRC_ ## BIT_ID ## _TARGET_BIT(bus_width, lpddr3); \
|
||||
if (mapbit != DDRC_ ## BIT_ID ## _SPECIAL) { \
|
||||
mapbit += DDRC_ ## BIT_ID ## _BASE; \
|
||||
/* account for AXI -> HIF shift */ \
|
||||
mapbit += 3; \
|
||||
info->address |= \
|
||||
DDRC_MAP_BIT(info-> DDRC_ ## BIT_ID ## _TARGET, target_bit, mapbit); \
|
||||
} \
|
||||
})
|
||||
|
||||
/*
|
||||
* Steps in mapping an address:
|
||||
* system address -> DDRC -> AXI byte address:
|
||||
* disjoint memory regions are mapped into a monolithic block representing
|
||||
* total available RAM based on configured offsets
|
||||
* AXI byte address -> XPI -> HIF word address:
|
||||
* word-sized shift of 3 bits for 8 byte (word) alignment
|
||||
* HIF word address -> DDRC -> SDRAM address:
|
||||
* addresses are mapped into SDRAM terms by the flexible address mapper using
|
||||
* the ADDRMAP* registers
|
||||
*/
|
||||
static int compose_address(DDR_Error_Info *info)
|
||||
{
|
||||
uint32_t addrmap0 = DDRC_READ(DDRC_ADDRMAP0_OFFSET);
|
||||
uint32_t addrmap1 = DDRC_READ(DDRC_ADDRMAP1_OFFSET);
|
||||
uint32_t addrmap2 = DDRC_READ(DDRC_ADDRMAP2_OFFSET);
|
||||
uint32_t addrmap3 = DDRC_READ(DDRC_ADDRMAP3_OFFSET);
|
||||
uint32_t addrmap4 = DDRC_READ(DDRC_ADDRMAP4_OFFSET);
|
||||
uint32_t addrmap5 = DDRC_READ(DDRC_ADDRMAP5_OFFSET);
|
||||
uint32_t addrmap6 = DDRC_READ(DDRC_ADDRMAP6_OFFSET);
|
||||
uint32_t addrmap7 = DDRC_READ(DDRC_ADDRMAP7_OFFSET);
|
||||
uint32_t addrmap8 = DDRC_READ(DDRC_ADDRMAP8_OFFSET);
|
||||
uint32_t addrmap9 = DDRC_READ(DDRC_ADDRMAP9_OFFSET);
|
||||
uint32_t addrmap10 = DDRC_READ(DDRC_ADDRMAP10_OFFSET);
|
||||
uint32_t addrmap11 = DDRC_READ(DDRC_ADDRMAP11_OFFSET);
|
||||
uint32_t mstr = DDRC_READ(DDRC_MSTR_OFFSET);
|
||||
uint32_t bus_width = DDRC_MSTR_DATA_BUS_WIDTH_GET(mstr);
|
||||
bool lpddr3 = mstr & DDRC_MSTR_LPDDR3;
|
||||
|
||||
homogenize_row(&addrmap5, &addrmap9, &addrmap10, &addrmap11);
|
||||
|
||||
/* Clear items that will be written to */
|
||||
info->address = 0;
|
||||
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP0_RANK_B0, info, addrmap0);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP1_BANK_B2, info, addrmap1);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP1_BANK_B1, info, addrmap1);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP1_BANK_B0, info, addrmap1);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP2_COL_B5, info, addrmap2);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP2_COL_B4, info, addrmap2);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP2_COL_B3, info, addrmap2);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP2_COL_B2, info, addrmap2);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP3_COL_B9, info, addrmap3);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP3_COL_B8, info, addrmap3);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP3_COL_B7, info, addrmap3);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP3_COL_B6, info, addrmap3);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP4_COL_B11, info, addrmap4);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP4_COL_B10, info, addrmap4);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP5_ROW_B11, info, addrmap5);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP5_ROW_B1, info, addrmap5);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP5_ROW_B0, info, addrmap5);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP6_ROW_B15, info, addrmap6);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP6_ROW_B14, info, addrmap6);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP6_ROW_B13, info, addrmap6);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP6_ROW_B12, info, addrmap6);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP7_ROW_B17, info, addrmap7);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP7_ROW_B16, info, addrmap7);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP8_BG_B1, info, addrmap8);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP8_BG_B0, info, addrmap8);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP9_ROW_B5, info, addrmap9);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP9_ROW_B4, info, addrmap9);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP9_ROW_B3, info, addrmap9);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP9_ROW_B2, info, addrmap9);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP10_ROW_B9, info, addrmap10);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP10_ROW_B8, info, addrmap10);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP10_ROW_B7, info, addrmap10);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP10_ROW_B6, info, addrmap10);
|
||||
DDRC_CHECK_AND_UNMAP(bus_width, lpddr3, ADDRMAP11_ROW_B10, info, addrmap11);
|
||||
|
||||
/* Column[0:1] are always statically mapped to HIF[0:1] */
|
||||
info->address |= (info->column & 0x3) << 3;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uintptr_t ddr_qos_ctrl_base = 0xFD090000;
|
||||
/* DDR QoS CTRL QoS IRQ Status */
|
||||
#define DDR_QIS_OFFSET 0x200
|
||||
#define DDR_QIE_OFFSET 0x208
|
||||
#define DDR_QID_OFFSET 0x20c
|
||||
#define DDR_QI_UNCRERR BSP_BIT32(2)
|
||||
#define DDR_QI_CORERR BSP_BIT32(1)
|
||||
|
||||
#define DDRC_ECCSTAT_OFFSET 0x78
|
||||
#define DDRC_ECCSTAT_UNCR_ERR(val) BSP_FLD32(val, 16, 19)
|
||||
#define DDRC_ECCSTAT_UNCR_ERR_GET(reg) BSP_FLD32GET(reg, 16, 19)
|
||||
#define DDRC_ECCSTAT_UNCR_ERR_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
|
||||
#define DDRC_ECCSTAT_CORR_ERR(val) BSP_FLD32(val, 8, 11)
|
||||
#define DDRC_ECCSTAT_CORR_ERR_GET(reg) BSP_FLD32GET(reg, 8, 11)
|
||||
#define DDRC_ECCSTAT_CORR_ERR_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
|
||||
#define DDRC_ECCSTAT_CORR_BIT(val) BSP_FLD32(val, 0, 6)
|
||||
#define DDRC_ECCSTAT_CORR_BIT_GET(reg) BSP_FLD32GET(reg, 0, 6)
|
||||
#define DDRC_ECCSTAT_CORR_BIT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
|
||||
|
||||
/* Correctable and uncorrectable error address registers share encodings */
|
||||
#define DDRC_ECCCADDR0_OFFSET 0x84
|
||||
#define DDRC_ECCUADDR0_OFFSET 0xA4
|
||||
#define DDRC_ECCXADDR0_RANK BSP_BIT32(24)
|
||||
#define DDRC_ECCXADDR0_ROW(val) BSP_FLD32(val, 0, 17)
|
||||
#define DDRC_ECCXADDR0_ROW_GET(reg) BSP_FLD32GET(reg, 0, 17)
|
||||
#define DDRC_ECCXADDR0_ROW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
|
||||
|
||||
#define DDRC_ECCCADDR1_OFFSET 0x88
|
||||
#define DDRC_ECCUADDR1_OFFSET 0xA8
|
||||
#define DDRC_ECCXADDR1_BG(val) BSP_FLD32(val, 24, 25)
|
||||
#define DDRC_ECCXADDR1_BG_GET(reg) BSP_FLD32GET(reg, 24, 25)
|
||||
#define DDRC_ECCXADDR1_BG_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
|
||||
#define DDRC_ECCXADDR1_BANK(val) BSP_FLD32(val, 16, 18)
|
||||
#define DDRC_ECCXADDR1_BANK_GET(reg) BSP_FLD32GET(reg, 16, 18)
|
||||
#define DDRC_ECCXADDR1_BANK_SET(reg, val) BSP_FLD32SET(reg, val, 16, 18)
|
||||
#define DDRC_ECCXADDR1_COL(val) BSP_FLD32(val, 0, 11)
|
||||
#define DDRC_ECCXADDR1_COL_GET(reg) BSP_FLD32GET(reg, 0, 11)
|
||||
#define DDRC_ECCXADDR1_COL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
|
||||
|
||||
static void extract_ddr_info(
|
||||
DDR_Error_Info *info,
|
||||
uint32_t addr0_val,
|
||||
uint32_t addr1_val
|
||||
)
|
||||
{
|
||||
info->rank = (addr0_val & DDRC_ECCXADDR0_RANK) >> 24;
|
||||
info->bank_group = DDRC_ECCXADDR1_BG_GET(addr1_val);
|
||||
info->bank = DDRC_ECCXADDR1_BANK_GET(addr1_val);
|
||||
info->row = DDRC_ECCXADDR0_ROW_GET(addr0_val);
|
||||
info->column = DDRC_ECCXADDR1_COL_GET(addr1_val);
|
||||
compose_address(info);
|
||||
}
|
||||
|
||||
|
||||
static void ddr_handler(void *arg)
|
||||
{
|
||||
(void) arg;
|
||||
|
||||
volatile uint32_t *qis = (uint32_t *)(ddr_qos_ctrl_base + DDR_QIS_OFFSET);
|
||||
uint32_t qis_value = *qis;
|
||||
DDR_Error_Info info;
|
||||
volatile uint32_t *addr0 = (uint32_t *)(ddrc_base + DDRC_ECCCADDR0_OFFSET);
|
||||
volatile uint32_t *addr1 = (uint32_t *)(ddrc_base + DDRC_ECCCADDR1_OFFSET);
|
||||
|
||||
/* specific data is captured in DDRC.ECCSTAT[corrected_bit_num] */
|
||||
if ((qis_value & DDR_QI_CORERR) != 0) {
|
||||
/* Clear status flag */
|
||||
*qis = DDR_QI_CORERR;
|
||||
|
||||
info.type = DDR_CORRECTABLE;
|
||||
extract_ddr_info(&info, *addr0, *addr1);
|
||||
zynqmp_invoke_ecc_handler(DDR_RAM, &info);
|
||||
}
|
||||
if ((qis_value & DDR_QI_UNCRERR) != 0) {
|
||||
/* Clear status flag */
|
||||
*qis = DDR_QI_UNCRERR;
|
||||
|
||||
info.type = DDR_UNCORRECTABLE;
|
||||
extract_ddr_info(&info, *addr0, *addr1);
|
||||
zynqmp_invoke_ecc_handler(DDR_RAM, &info);
|
||||
}
|
||||
}
|
||||
|
||||
static rtems_interrupt_entry zynqmp_ddr_ecc_entry;
|
||||
|
||||
rtems_status_code zynqmp_configure_ddr_ecc( void )
|
||||
{
|
||||
volatile uint32_t *qie = (uint32_t *)(ddr_qos_ctrl_base + DDR_QIE_OFFSET);
|
||||
rtems_status_code sc;
|
||||
|
||||
rtems_interrupt_entry_initialize(
|
||||
&zynqmp_ddr_ecc_entry,
|
||||
ddr_handler,
|
||||
NULL,
|
||||
"DDR RAM ECC"
|
||||
);
|
||||
|
||||
sc = rtems_interrupt_entry_install(
|
||||
ZYNQMP_IRQ_DDR,
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
&zynqmp_ddr_ecc_entry
|
||||
);
|
||||
|
||||
if (sc != RTEMS_SUCCESSFUL) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
/* enable interrupts for ECC in QOS_IRQ_ENABLE */
|
||||
*qie |= DDR_QI_UNCRERR | DDR_QI_CORERR;
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
#if RUNNING_FROM_OCM_IS_NOT_CURRENTLY_POSSIBLE
|
||||
/*
|
||||
* Injecting DDR ECC faults requires RTEMS to run from OCM since the DDR will be
|
||||
* partially disabled and re-enabled during the process. RTEMS is too large to
|
||||
* run out of OCM in its current configuration and doing so would require
|
||||
* operation without MMU along with other changes to reduce the memory footprint
|
||||
* to below 256KB. It must be the whole RTEMS executable since stack accesses
|
||||
* would also present a problem.
|
||||
*/
|
||||
|
||||
#define DDRC_PRINT_MAP(BIT_ID, addrmap) \
|
||||
({ \
|
||||
uint32_t mapbit = DDRC_ ## BIT_ID ## _GET(addrmap); \
|
||||
if (mapbit != DDRC_ ## BIT_ID ## _SPECIAL) { \
|
||||
mapbit += DDRC_ ## BIT_ID ## _BASE; \
|
||||
} \
|
||||
})
|
||||
|
||||
static void print_addr_maps( void )
|
||||
{
|
||||
uint32_t addrmap0 = DDRC_READ(DDRC_ADDRMAP0_OFFSET);
|
||||
uint32_t addrmap1 = DDRC_READ(DDRC_ADDRMAP1_OFFSET);
|
||||
uint32_t addrmap2 = DDRC_READ(DDRC_ADDRMAP2_OFFSET);
|
||||
uint32_t addrmap3 = DDRC_READ(DDRC_ADDRMAP3_OFFSET);
|
||||
uint32_t addrmap4 = DDRC_READ(DDRC_ADDRMAP4_OFFSET);
|
||||
uint32_t addrmap5 = DDRC_READ(DDRC_ADDRMAP5_OFFSET);
|
||||
uint32_t addrmap6 = DDRC_READ(DDRC_ADDRMAP6_OFFSET);
|
||||
uint32_t addrmap7 = DDRC_READ(DDRC_ADDRMAP7_OFFSET);
|
||||
uint32_t addrmap8 = DDRC_READ(DDRC_ADDRMAP8_OFFSET);
|
||||
uint32_t addrmap9 = DDRC_READ(DDRC_ADDRMAP9_OFFSET);
|
||||
uint32_t addrmap10 = DDRC_READ(DDRC_ADDRMAP10_OFFSET);
|
||||
uint32_t addrmap11 = DDRC_READ(DDRC_ADDRMAP11_OFFSET);
|
||||
|
||||
homogenize_row(&addrmap5, &addrmap9, &addrmap10, &addrmap11);
|
||||
|
||||
DDRC_PRINT_MAP(ADDRMAP0_RANK_B0, addrmap0);
|
||||
DDRC_PRINT_MAP(ADDRMAP1_BANK_B2, addrmap1);
|
||||
DDRC_PRINT_MAP(ADDRMAP1_BANK_B1, addrmap1);
|
||||
DDRC_PRINT_MAP(ADDRMAP1_BANK_B0, addrmap1);
|
||||
DDRC_PRINT_MAP(ADDRMAP2_COL_B5, addrmap2);
|
||||
DDRC_PRINT_MAP(ADDRMAP2_COL_B4, addrmap2);
|
||||
DDRC_PRINT_MAP(ADDRMAP2_COL_B3, addrmap2);
|
||||
DDRC_PRINT_MAP(ADDRMAP2_COL_B2, addrmap2);
|
||||
DDRC_PRINT_MAP(ADDRMAP3_COL_B9, addrmap3);
|
||||
DDRC_PRINT_MAP(ADDRMAP3_COL_B8, addrmap3);
|
||||
DDRC_PRINT_MAP(ADDRMAP3_COL_B7, addrmap3);
|
||||
DDRC_PRINT_MAP(ADDRMAP3_COL_B6, addrmap3);
|
||||
DDRC_PRINT_MAP(ADDRMAP4_COL_B11, addrmap4);
|
||||
DDRC_PRINT_MAP(ADDRMAP4_COL_B10, addrmap4);
|
||||
DDRC_PRINT_MAP(ADDRMAP5_ROW_B11, addrmap5);
|
||||
DDRC_PRINT_MAP(ADDRMAP5_ROW_B1, addrmap5);
|
||||
DDRC_PRINT_MAP(ADDRMAP5_ROW_B0, addrmap5);
|
||||
DDRC_PRINT_MAP(ADDRMAP6_ROW_B15, addrmap6);
|
||||
DDRC_PRINT_MAP(ADDRMAP6_ROW_B14, addrmap6);
|
||||
DDRC_PRINT_MAP(ADDRMAP6_ROW_B13, addrmap6);
|
||||
DDRC_PRINT_MAP(ADDRMAP6_ROW_B12, addrmap6);
|
||||
DDRC_PRINT_MAP(ADDRMAP7_ROW_B17, addrmap7);
|
||||
DDRC_PRINT_MAP(ADDRMAP7_ROW_B16, addrmap7);
|
||||
DDRC_PRINT_MAP(ADDRMAP8_BG_B1, addrmap8);
|
||||
DDRC_PRINT_MAP(ADDRMAP8_BG_B0, addrmap8);
|
||||
DDRC_PRINT_MAP(ADDRMAP9_ROW_B5, addrmap9);
|
||||
DDRC_PRINT_MAP(ADDRMAP9_ROW_B4, addrmap9);
|
||||
DDRC_PRINT_MAP(ADDRMAP9_ROW_B3, addrmap9);
|
||||
DDRC_PRINT_MAP(ADDRMAP9_ROW_B2, addrmap9);
|
||||
DDRC_PRINT_MAP(ADDRMAP10_ROW_B9, addrmap10);
|
||||
DDRC_PRINT_MAP(ADDRMAP10_ROW_B8, addrmap10);
|
||||
DDRC_PRINT_MAP(ADDRMAP10_ROW_B7, addrmap10);
|
||||
DDRC_PRINT_MAP(ADDRMAP10_ROW_B6, addrmap10);
|
||||
DDRC_PRINT_MAP(ADDRMAP11_ROW_B10, addrmap11);
|
||||
}
|
||||
|
||||
/* Ignore the bitmap if it's the flag value, otherwise map it */
|
||||
#define DDRC_CHECK_AND_MAP(bus_width, lpddr3, BIT_ID, info, addrmap) \
|
||||
({ \
|
||||
uint32_t mapbit = DDRC_ ## BIT_ID ## _GET(addrmap); \
|
||||
uint32_t target_bit = DDRC_ ## BIT_ID ## _TARGET_BIT(bus_width, lpddr3); \
|
||||
if (mapbit != DDRC_ ## BIT_ID ## _SPECIAL) { \
|
||||
mapbit += DDRC_ ## BIT_ID ## _BASE; \
|
||||
/* account for AXI -> HIF shift */ \
|
||||
mapbit += 3; \
|
||||
info-> DDRC_ ## BIT_ID ## _TARGET |= \
|
||||
DDRC_MAP_BIT(info->address, mapbit, target_bit); \
|
||||
} \
|
||||
})
|
||||
|
||||
static int decompose_address(DDR_Error_Info *info)
|
||||
{
|
||||
uint32_t addrmap0 = DDRC_READ(DDRC_ADDRMAP0_OFFSET);
|
||||
uint32_t addrmap1 = DDRC_READ(DDRC_ADDRMAP1_OFFSET);
|
||||
uint32_t addrmap2 = DDRC_READ(DDRC_ADDRMAP2_OFFSET);
|
||||
uint32_t addrmap3 = DDRC_READ(DDRC_ADDRMAP3_OFFSET);
|
||||
uint32_t addrmap4 = DDRC_READ(DDRC_ADDRMAP4_OFFSET);
|
||||
uint32_t addrmap5 = DDRC_READ(DDRC_ADDRMAP5_OFFSET);
|
||||
uint32_t addrmap6 = DDRC_READ(DDRC_ADDRMAP6_OFFSET);
|
||||
uint32_t addrmap7 = DDRC_READ(DDRC_ADDRMAP7_OFFSET);
|
||||
uint32_t addrmap8 = DDRC_READ(DDRC_ADDRMAP8_OFFSET);
|
||||
uint32_t addrmap9 = DDRC_READ(DDRC_ADDRMAP9_OFFSET);
|
||||
uint32_t addrmap10 = DDRC_READ(DDRC_ADDRMAP10_OFFSET);
|
||||
uint32_t addrmap11 = DDRC_READ(DDRC_ADDRMAP11_OFFSET);
|
||||
uint32_t mstr = DDRC_READ(DDRC_MSTR_OFFSET);
|
||||
uint32_t bus_width = DDRC_MSTR_DATA_BUS_WIDTH_GET(mstr);
|
||||
bool lpddr3 = mstr & DDRC_MSTR_LPDDR3;
|
||||
|
||||
homogenize_row(&addrmap5, &addrmap9, &addrmap10, &addrmap11);
|
||||
|
||||
/* Clear items that will be written to */
|
||||
info->rank = 0;
|
||||
info->bank_group = 0;
|
||||
info->bank = 0;
|
||||
info->row = 0;
|
||||
info->column = 0;
|
||||
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP0_RANK_B0, info, addrmap0);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP1_BANK_B2, info, addrmap1);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP1_BANK_B1, info, addrmap1);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP1_BANK_B0, info, addrmap1);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP2_COL_B5, info, addrmap2);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP2_COL_B4, info, addrmap2);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP2_COL_B3, info, addrmap2);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP2_COL_B2, info, addrmap2);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP3_COL_B9, info, addrmap3);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP3_COL_B8, info, addrmap3);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP3_COL_B7, info, addrmap3);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP3_COL_B6, info, addrmap3);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP4_COL_B11, info, addrmap4);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP4_COL_B10, info, addrmap4);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP5_ROW_B11, info, addrmap5);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP5_ROW_B1, info, addrmap5);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP5_ROW_B0, info, addrmap5);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP6_ROW_B15, info, addrmap6);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP6_ROW_B14, info, addrmap6);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP6_ROW_B13, info, addrmap6);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP6_ROW_B12, info, addrmap6);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP7_ROW_B17, info, addrmap7);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP7_ROW_B16, info, addrmap7);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP8_BG_B1, info, addrmap8);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP8_BG_B0, info, addrmap8);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP9_ROW_B5, info, addrmap9);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP9_ROW_B4, info, addrmap9);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP9_ROW_B3, info, addrmap9);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP9_ROW_B2, info, addrmap9);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP10_ROW_B9, info, addrmap10);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP10_ROW_B8, info, addrmap10);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP10_ROW_B7, info, addrmap10);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP10_ROW_B6, info, addrmap10);
|
||||
DDRC_CHECK_AND_MAP(bus_width, lpddr3, ADDRMAP11_ROW_B10, info, addrmap11);
|
||||
|
||||
/* Column[0:1] are always statically mapped to HIF[0:1] */
|
||||
info->column |= (info->address >> 3) & 0x3;
|
||||
|
||||
/* select target address */
|
||||
uint32_t paddr0_val = DDRC_ECCPOISONADDR0_COL_SET(0, info->column);
|
||||
if (info->rank) {
|
||||
paddr0_val |= DDRC_ECCPOISONADDR0_RANK;
|
||||
}
|
||||
|
||||
uint32_t paddr1_val = DDRC_ECCPOISONADDR1_BG_SET(0, info->bank_group);
|
||||
paddr1_val = DDRC_ECCPOISONADDR1_BANK_SET(paddr1_val, info->bank);
|
||||
paddr1_val = DDRC_ECCPOISONADDR1_ROW_SET(paddr1_val, info->row);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* DDR Controller (DDRC) ECC Config Register 1 */
|
||||
#define DDRC_ECCCFG1_OFFSET 0x74
|
||||
#define DDRC_ECCCFG1_POISON_SINGLE BSP_BIT32(1)
|
||||
#define DDRC_ECCCFG1_POISON_EN BSP_BIT32(0)
|
||||
|
||||
#define DDRC_SWCTL_OFFSET 0x74
|
||||
#define DDRC_SWSTAT_OFFSET 0x324
|
||||
|
||||
#define DDRC_DBGCAM_OFFSET 0x308
|
||||
#define DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY BSP_BIT32(28)
|
||||
#define DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY BSP_BIT32(27)
|
||||
#define DDRC_DBGCAM_DBG_WR_Q_EMPTY BSP_BIT32(26)
|
||||
#define DDRC_DBGCAM_DBG_RD_Q_EMPTY BSP_BIT32(25)
|
||||
|
||||
#define DDRC_DBG1_OFFSET 0x304
|
||||
#define DDRC_DBG1_DIS_DQ BSP_BIT32(0)
|
||||
|
||||
static void set_ecccfg1(volatile uint32_t *ecccfg1, uint32_t ecccfg1_val)
|
||||
{
|
||||
uint32_t dbgcam_mask = DDRC_DBGCAM_WR_DATA_PIPELINE_EMPTY |
|
||||
DDRC_DBGCAM_RD_DATA_PIPELINE_EMPTY | DDRC_DBGCAM_DBG_WR_Q_EMPTY |
|
||||
DDRC_DBGCAM_DBG_RD_Q_EMPTY;
|
||||
volatile uint32_t *dbgcam = (uint32_t *)(ddrc_base + DDRC_DBGCAM_OFFSET);
|
||||
volatile uint32_t *dbg1 = (uint32_t *)(ddrc_base + DDRC_DBG1_OFFSET);
|
||||
|
||||
/* disable dequeueing */
|
||||
*dbg1 |= DDRC_DBG1_DIS_DQ;
|
||||
/* poll for DDRC empty state */
|
||||
while((*dbgcam & dbgcam_mask) != dbgcam_mask);
|
||||
*ecccfg1 = ecccfg1_val;
|
||||
/* enable dequeueing */
|
||||
*dbg1 &= ~DDRC_DBG1_DIS_DQ;
|
||||
}
|
||||
|
||||
void zynqmp_ddr_inject_fault( bool correctable )
|
||||
{
|
||||
uint64_t poison_var;
|
||||
uint64_t read_var;
|
||||
volatile uint64_t *poison_addr = &poison_var;
|
||||
volatile uint32_t *ecccfg1 = (uint32_t *)(ddrc_base + DDRC_ECCCFG1_OFFSET);
|
||||
uint32_t ecccfg1_val = 0;
|
||||
volatile uint32_t *swctl = (uint32_t *)(ddrc_base + DDRC_SWCTL_OFFSET);
|
||||
volatile uint32_t *swstat = (uint32_t *)(ddrc_base + DDRC_SWSTAT_OFFSET);
|
||||
volatile uint32_t *poisonaddr0;
|
||||
uint32_t paddr0_val;
|
||||
volatile uint32_t *poisonaddr1;
|
||||
uint32_t paddr1_val;
|
||||
DDR_Error_Info info;
|
||||
poisonaddr0 = (uint32_t *)(ddrc_base + DDRC_ECCPOISONADDR0_OFFSET);
|
||||
poisonaddr1 = (uint32_t *)(ddrc_base + DDRC_ECCPOISONADDR1_OFFSET);
|
||||
|
||||
info.address = (uint64_t)(uintptr_t)poison_addr;
|
||||
/* convert address to SDRAM address components */
|
||||
decompose_address(&info);
|
||||
|
||||
/* select correctable/uncorrectable */
|
||||
ecccfg1_val &= ~DDRC_ECCCFG1_POISON_SINGLE;
|
||||
if (correctable) {
|
||||
ecccfg1_val |= DDRC_ECCCFG1_POISON_SINGLE;
|
||||
}
|
||||
|
||||
/* enable poisoning */
|
||||
ecccfg1_val |= DDRC_ECCCFG1_POISON_EN;
|
||||
|
||||
uint32_t isr_cookie;
|
||||
rtems_interrupt_local_disable(isr_cookie);
|
||||
/* swctl must be unset to allow modification of ecccfg1 */
|
||||
*swctl = 0;
|
||||
set_ecccfg1(ecccfg1, ecccfg1_val);
|
||||
*swctl = 1;
|
||||
rtems_interrupt_local_enable(isr_cookie);
|
||||
|
||||
/* Wait for swctl propagation to swstat */
|
||||
while ((*swstat & 0x1) == 0);
|
||||
|
||||
/* select target address */
|
||||
paddr0_val = DDRC_ECCPOISONADDR0_COL_SET(0, info.column);
|
||||
if (info.rank) {
|
||||
paddr0_val |= DDRC_ECCPOISONADDR0_RANK;
|
||||
}
|
||||
*poisonaddr0 = paddr0_val;
|
||||
|
||||
paddr1_val = DDRC_ECCPOISONADDR1_BG_SET(0, info.bank_group);
|
||||
paddr1_val = DDRC_ECCPOISONADDR1_BANK_SET(paddr1_val, info.bank);
|
||||
paddr1_val = DDRC_ECCPOISONADDR1_ROW_SET(paddr1_val, info.row);
|
||||
*poisonaddr1 = paddr1_val;
|
||||
|
||||
/* write to poison address */
|
||||
*poison_addr = 0x5555555555555555UL;
|
||||
|
||||
/* flush cache to force write */
|
||||
rtems_cache_flush_multiple_data_lines(poison_addr, sizeof(*poison_addr));
|
||||
|
||||
/* invalidate cache to force read */
|
||||
rtems_cache_invalidate_multiple_data_lines(poison_addr, sizeof(*poison_addr));
|
||||
|
||||
/* Force a data sync barrier */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
|
||||
/* read from poison address to generate event */
|
||||
read_var = *poison_addr;
|
||||
read_var++;
|
||||
|
||||
volatile uint32_t *qis = (uint32_t *)(ddr_qos_ctrl_base + DDR_QIS_OFFSET);
|
||||
|
||||
/* disable poisoning */
|
||||
*swctl = 0;
|
||||
*ecccfg1 = 0;
|
||||
*swctl = 1;
|
||||
}
|
||||
#endif
|
||||
@@ -1,300 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the implementation of OCM ECC support.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/ecc_priv.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp/utility.h>
|
||||
#include <libcpu/mmu-vmsav8-64.h>
|
||||
|
||||
static uintptr_t ocm_base = 0xFF960000;
|
||||
|
||||
/* ECC Control */
|
||||
#define OCM_ECC_CTRL 0x14
|
||||
/* 0 -> single error, 1 -> continuous errors */
|
||||
#define OCM_ECC_CTRL_FI_MODE BSP_BIT32(2)
|
||||
/* When bit is set, detection occurs without correction */
|
||||
#define OCM_ECC_CTRL_DET_ONLY BSP_BIT32(1)
|
||||
/* Enable ECC, should only be modified at system boot */
|
||||
#define OCM_ECC_CTRL_ECC_ON_OFF BSP_BIT32(0)
|
||||
|
||||
/* Interrupt Enable */
|
||||
#define OCM_IE 0xc
|
||||
#define OCM_IE_UE_RMW BSP_BIT32(10)
|
||||
#define OCM_IE_UE BSP_BIT32(7)
|
||||
#define OCM_IE_CE BSP_BIT32(6)
|
||||
|
||||
/* Error Response Control */
|
||||
#define OCM_ERR_CTRL 0x0
|
||||
#define OCM_ERR_CTRL_UE_RES BSP_BIT32(3)
|
||||
|
||||
/*
|
||||
* Fault Injection Data, four registers comprising 16 bytes of a data word
|
||||
*
|
||||
* Bits set to 1 toggle the corresponding bits of the next written word during a
|
||||
* fault injection.
|
||||
*/
|
||||
#define OCM_FI_D0 0x4c
|
||||
#define OCM_FI_D1 0x50
|
||||
#define OCM_FI_D2 0x54
|
||||
#define OCM_FI_D3 0x58
|
||||
|
||||
/* Fault Injection Syndrome */
|
||||
#define OCM_FI_SY 0x5c
|
||||
#define OCM_FI_SY_DATA(val) BSP_FLD32(val, 0, 15)
|
||||
#define OCM_FI_SY_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define OCM_FI_SY_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
|
||||
/* Fault Injection Counter */
|
||||
#define OCM_FI_CNTR 0x74
|
||||
#define OCM_FI_CNTR_COUNT(val) BSP_FLD32(val, 0, 23)
|
||||
#define OCM_FI_CNTR_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 23)
|
||||
#define OCM_FI_CNTR_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 23)
|
||||
|
||||
/* Interrupt Status */
|
||||
#define OCM_IS 0x4
|
||||
#define OCM_IS_UE_RMW BSP_BIT32(10)
|
||||
#define OCM_IS_UE BSP_BIT32(7)
|
||||
#define OCM_IS_CE BSP_BIT32(6)
|
||||
|
||||
/* Interrupt Mask */
|
||||
#define OCM_IM 0x8
|
||||
#define OCM_IM_UE_RMW BSP_BIT32(10)
|
||||
#define OCM_IM_UE BSP_BIT32(7)
|
||||
#define OCM_IM_CE BSP_BIT32(6)
|
||||
|
||||
void zynqmp_ocm_inject_fault( void )
|
||||
{
|
||||
volatile uint32_t *fi_d0 = (uint32_t*)(ocm_base + OCM_FI_D0);
|
||||
volatile uint32_t *fi_cnt = (uint32_t*)(ocm_base + OCM_FI_CNTR);
|
||||
volatile uint64_t *ocm_top = (uint64_t*)0xFFFFFFF0U;
|
||||
volatile uint32_t *ecc_ctrl = (uint32_t*)(ocm_base + OCM_ECC_CTRL);
|
||||
uint64_t ocm_tmp = *ocm_top;
|
||||
|
||||
/* Configure OCM to throw constant errors */
|
||||
*ecc_ctrl |= OCM_ECC_CTRL_FI_MODE;
|
||||
|
||||
/* Inject a single bit error */
|
||||
*fi_d0 = 1;
|
||||
|
||||
/* Configure the clock count after which errors will begin */
|
||||
*fi_cnt = 0;
|
||||
|
||||
/* Insert a memory barrier to ensure that fault injection is active */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
|
||||
/* trigger fault with a write of data that was already at the given address */
|
||||
*ocm_top = 0;
|
||||
|
||||
/* Insert a memory barrier to prevent optimization */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
|
||||
/* Perform read to force reporting of the error */
|
||||
*ocm_top;
|
||||
|
||||
/* Disable constant fault mode */
|
||||
*ecc_ctrl &= ~(OCM_ECC_CTRL_FI_MODE);
|
||||
|
||||
/* Insert a memory barrier to ensure the mode has changed */
|
||||
_AARCH64_Data_synchronization_barrier();
|
||||
|
||||
/* Reset to original value now that constant errors are disabled */
|
||||
*ocm_top = ocm_tmp;
|
||||
}
|
||||
|
||||
/* Correctable Error First Failing Address */
|
||||
#define OCM_CE_FFA 0x1c
|
||||
#define OCM_CE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
|
||||
#define OCM_CE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
|
||||
#define OCM_CE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
|
||||
|
||||
/* Correctable Error First Failing Data, four registers comprising 16 bytes */
|
||||
#define OCM_CE_FFD0 0x20
|
||||
#define OCM_CE_FFD1 0x24
|
||||
#define OCM_CE_FFD2 0x28
|
||||
#define OCM_CE_FFD3 0x2c
|
||||
|
||||
/* Correctable Error First Failing ECC */
|
||||
#define OCM_CE_FFE 0x1c
|
||||
#define OCM_CE_FFE_SYNDROME(val) BSP_FLD32(val, 0, 15)
|
||||
#define OCM_CE_FFE_SYNDROME_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define OCM_CE_FFE_SYNDROME_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
|
||||
/* Uncorrectable Error First Failing Address */
|
||||
#define OCM_UE_FFA 0x34
|
||||
#define OCM_UE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
|
||||
#define OCM_UE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
|
||||
#define OCM_UE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
|
||||
|
||||
/* Uncorrectable Error First Failing Data, four registers comprising 16 bytes */
|
||||
#define OCM_UE_FFD0 0x38
|
||||
#define OCM_UE_FFD1 0x3c
|
||||
#define OCM_UE_FFD2 0x40
|
||||
#define OCM_UE_FFD3 0x44
|
||||
|
||||
/* Uncorrectable Error First Failing ECC */
|
||||
#define OCM_UE_FFE 0x48
|
||||
#define OCM_UE_FFE_SYNDROME(val) BSP_FLD32(val, 0, 15)
|
||||
#define OCM_UE_FFE_SYNDROME_GET(reg) BSP_FLD32GET(reg, 0, 15)
|
||||
#define OCM_UE_FFE_SYNDROME_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
|
||||
|
||||
/* Read/Modify/Write Uncorrectable Error First Failing Address */
|
||||
#define OCM_RMW_UE_FFA 0x70
|
||||
#define OCM_RMW_UE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
|
||||
#define OCM_RMW_UE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
|
||||
#define OCM_RMW_UE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
|
||||
|
||||
static void ocm_handle_rmw( void )
|
||||
{
|
||||
volatile uint32_t *rmw_ffa = (uint32_t*)(ocm_base + OCM_RMW_UE_FFA);
|
||||
OCM_Error_Info info;
|
||||
|
||||
info.type = OCM_UNCORRECTABLE_RMW;
|
||||
info.offset = OCM_RMW_UE_FFA_ADDR_GET(*rmw_ffa);
|
||||
zynqmp_invoke_ecc_handler(OCM_RAM, &info);
|
||||
}
|
||||
|
||||
static void ocm_handle_ce( void )
|
||||
{
|
||||
volatile uint32_t *ce_ffa = (uint32_t*)(ocm_base + OCM_CE_FFA);
|
||||
volatile uint32_t *ce_ffe = (uint32_t*)(ocm_base + OCM_CE_FFA);
|
||||
volatile uint32_t *ce_ffd0 = (uint32_t*)(ocm_base + OCM_CE_FFD0);
|
||||
volatile uint32_t *ce_ffd1 = (uint32_t*)(ocm_base + OCM_CE_FFD1);
|
||||
volatile uint32_t *ce_ffd2 = (uint32_t*)(ocm_base + OCM_CE_FFD2);
|
||||
volatile uint32_t *ce_ffd3 = (uint32_t*)(ocm_base + OCM_CE_FFD3);
|
||||
OCM_Error_Info info;
|
||||
|
||||
info.type = OCM_CORRECTABLE;
|
||||
info.offset = OCM_CE_FFA_ADDR_GET(*ce_ffa);
|
||||
info.data0 = *ce_ffd0;
|
||||
info.data1 = *ce_ffd1;
|
||||
info.data2 = *ce_ffd2;
|
||||
info.data3 = *ce_ffd3;
|
||||
info.syndrome = OCM_CE_FFE_SYNDROME_GET(*ce_ffe);
|
||||
zynqmp_invoke_ecc_handler(OCM_RAM, &info);
|
||||
}
|
||||
|
||||
static void ocm_handle_ue( void )
|
||||
{
|
||||
volatile uint32_t *ue_ffa = (uint32_t*)(ocm_base + OCM_UE_FFA);
|
||||
volatile uint32_t *ue_ffe = (uint32_t*)(ocm_base + OCM_UE_FFA);
|
||||
volatile uint32_t *ue_ffd0 = (uint32_t*)(ocm_base + OCM_UE_FFD0);
|
||||
volatile uint32_t *ue_ffd1 = (uint32_t*)(ocm_base + OCM_UE_FFD1);
|
||||
volatile uint32_t *ue_ffd2 = (uint32_t*)(ocm_base + OCM_UE_FFD2);
|
||||
volatile uint32_t *ue_ffd3 = (uint32_t*)(ocm_base + OCM_UE_FFD3);
|
||||
OCM_Error_Info info;
|
||||
|
||||
info.type = OCM_UNCORRECTABLE;
|
||||
info.offset = OCM_UE_FFA_ADDR_GET(*ue_ffa);
|
||||
info.data0 = *ue_ffd0;
|
||||
info.data1 = *ue_ffd1;
|
||||
info.data2 = *ue_ffd2;
|
||||
info.data3 = *ue_ffd3;
|
||||
info.syndrome = OCM_UE_FFE_SYNDROME_GET(*ue_ffe);
|
||||
zynqmp_invoke_ecc_handler(OCM_RAM, &info);
|
||||
}
|
||||
|
||||
static void ocm_handler(void *arg)
|
||||
{
|
||||
volatile uint32_t *ocm_is = (uint32_t*)(ocm_base + OCM_IS);
|
||||
uint32_t ocm_is_value = *ocm_is;
|
||||
(void) arg;
|
||||
|
||||
/* Check and clear each error type after handling */
|
||||
if ((ocm_is_value & OCM_IS_UE_RMW) != 0) {
|
||||
ocm_handle_rmw();
|
||||
*ocm_is = OCM_IS_UE_RMW;
|
||||
}
|
||||
|
||||
if ((ocm_is_value & OCM_IS_CE) != 0) {
|
||||
ocm_handle_ce();
|
||||
*ocm_is = OCM_IS_CE;
|
||||
}
|
||||
|
||||
if ((ocm_is_value & OCM_IS_UE) != 0) {
|
||||
ocm_handle_ue();
|
||||
*ocm_is = OCM_IS_UE;
|
||||
}
|
||||
}
|
||||
|
||||
static rtems_interrupt_entry zynqmp_ocm_ecc_entry;
|
||||
|
||||
rtems_status_code zynqmp_configure_ocm_ecc( void )
|
||||
{
|
||||
volatile uint32_t *err_ctrl = (uint32_t*)(ocm_base + OCM_ERR_CTRL);
|
||||
volatile uint32_t *ecc_ctrl = (uint32_t*)(ocm_base + OCM_ECC_CTRL);
|
||||
volatile uint32_t *int_enable = (uint32_t*)(ocm_base + OCM_IE);
|
||||
rtems_status_code sc;
|
||||
|
||||
rtems_interrupt_entry_initialize(
|
||||
&zynqmp_ocm_ecc_entry,
|
||||
ocm_handler,
|
||||
NULL,
|
||||
"OCM RAM ECC"
|
||||
);
|
||||
|
||||
sc = rtems_interrupt_entry_install(
|
||||
ZYNQMP_IRQ_OCM,
|
||||
RTEMS_INTERRUPT_SHARED,
|
||||
&zynqmp_ocm_ecc_entry
|
||||
);
|
||||
|
||||
if (sc != RTEMS_SUCCESSFUL) {
|
||||
return sc;
|
||||
}
|
||||
|
||||
if ((*ecc_ctrl & OCM_ECC_CTRL_ECC_ON_OFF) == 0) {
|
||||
/*
|
||||
* ECC is not enabled and should already have been by BOOT.bin. Enabling it
|
||||
* now could corrupt existing data in the OCM.
|
||||
*/
|
||||
return RTEMS_NOT_CONFIGURED;
|
||||
}
|
||||
|
||||
/*
|
||||
* OCM_ERR_CTRL.UE_RES forces generation of a synchronous external abort
|
||||
* instead of using interrupts to signal the fault
|
||||
*/
|
||||
*err_ctrl &= ~(OCM_ERR_CTRL_UE_RES);
|
||||
|
||||
/* Ensure ECC_CTRL is in the right state */
|
||||
*ecc_ctrl &= ~(OCM_ECC_CTRL_DET_ONLY);
|
||||
|
||||
/* enable correctable and uncorrectable error interrupts */
|
||||
*int_enable = OCM_IE_CE | OCM_IE_UE | OCM_IE_UE_RMW;
|
||||
|
||||
return RTEMS_SUCCESSFUL;
|
||||
}
|
||||
@@ -1,51 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This source file contains the implementatin of bsp_fdt_get().
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <bsp.h>
|
||||
#include <bsp/fdt.h>
|
||||
|
||||
const void *bsp_fdt_get(void)
|
||||
{
|
||||
return zynqmp_dtb;
|
||||
}
|
||||
|
||||
uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
|
||||
{
|
||||
if (icells != 3) {
|
||||
return 0;
|
||||
}
|
||||
return (intr[0] == 0 ? 32 : 16) + intr[1];
|
||||
}
|
||||
@@ -1,114 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This file provides the CFC-400X device tree
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <0x02>;
|
||||
#interrupt-cells = <0x03>;
|
||||
reg = <0x00 0xf9010000 0x00 0x10000>;
|
||||
interrupt-controller;
|
||||
phandle = <0x01>;
|
||||
};
|
||||
|
||||
ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x39 0x04>;
|
||||
reg = <0x00 0xff0b0000 0x00 0x1000>;
|
||||
phy-mode = "sgmii";
|
||||
ref-clock-num = <0>;
|
||||
};
|
||||
|
||||
ethernet@ff0c0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3b 0x04>;
|
||||
reg = <0x00 0xff0c0000 0x00 0x1000>;
|
||||
phy-mode = "sgmii";
|
||||
ref-clock-num = <1>;
|
||||
};
|
||||
|
||||
ethernet@ff0d0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3d 0x04>;
|
||||
reg = <0x00 0xff0d0000 0x00 0x1000>;
|
||||
phy-mode = "sgmii";
|
||||
ref-clock-num = <2>;
|
||||
};
|
||||
|
||||
ethernet@ff0e0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3f 0x04>;
|
||||
reg = <0x00 0xff0e0000 0x00 0x1000>;
|
||||
phy-mode = "sgmii";
|
||||
ref-clock-num = <3>;
|
||||
};
|
||||
|
||||
serial@800a0000 {
|
||||
clock-frequency = <0x189c000>;
|
||||
compatible = "ns16550a";
|
||||
current-speed = <0x1c200>;
|
||||
device_type = "serial";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x6e 0x04>;
|
||||
reg = <0x00 0x800a0000 0x00 0x10000>;
|
||||
reg-offset = <0x1000>;
|
||||
reg-shift = <0x02>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
mgmtport = "/amba/serial@800a0000";
|
||||
};
|
||||
};
|
||||
@@ -1,130 +0,0 @@
|
||||
unsigned char zynqmp_dtb[] = {
|
||||
0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x05, 0xf1, 0x00, 0x00, 0x00, 0x38,
|
||||
0x00, 0x00, 0x05, 0x10, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
|
||||
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1,
|
||||
0x00, 0x00, 0x04, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x61, 0x6d, 0x62, 0x61, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1b,
|
||||
0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x01,
|
||||
0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,
|
||||
0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x40, 0x66, 0x39, 0x30,
|
||||
0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1b, 0x61, 0x72, 0x6d, 0x2c,
|
||||
0x67, 0x69, 0x63, 0x2d, 0x34, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2d,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x62, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0b, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
|
||||
0x40, 0x66, 0x66, 0x30, 0x63, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b,
|
||||
0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f,
|
||||
0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e,
|
||||
0x00, 0x00, 0x00, 0x00, 0xff, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06,
|
||||
0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
|
||||
0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30,
|
||||
0x64, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73,
|
||||
0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00,
|
||||
0xff, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82,
|
||||
0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x65, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0e, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40, 0x38,
|
||||
0x30, 0x30, 0x61, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x99, 0x01, 0x89, 0xc0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b,
|
||||
0x6e, 0x73, 0x31, 0x36, 0x35, 0x35, 0x30, 0x61, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xa9,
|
||||
0x00, 0x01, 0xc2, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x07,
|
||||
0x00, 0x00, 0x00, 0xb7, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6e,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xc3, 0x00, 0x00, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xce,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x61, 0x6c, 0x69, 0x61, 0x73, 0x65, 0x73, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0xd8,
|
||||
0x2f, 0x61, 0x6d, 0x62, 0x61, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c,
|
||||
0x40, 0x38, 0x30, 0x30, 0x61, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09,
|
||||
0x23, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c,
|
||||
0x6c, 0x73, 0x00, 0x23, 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c,
|
||||
0x6c, 0x73, 0x00, 0x63, 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c,
|
||||
0x65, 0x00, 0x72, 0x61, 0x6e, 0x67, 0x65, 0x73, 0x00, 0x23, 0x69, 0x6e,
|
||||
0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c,
|
||||
0x73, 0x00, 0x72, 0x65, 0x67, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
|
||||
0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c,
|
||||
0x65, 0x72, 0x00, 0x70, 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x73,
|
||||
0x74, 0x61, 0x74, 0x75, 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
|
||||
0x75, 0x70, 0x74, 0x2d, 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x69,
|
||||
0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x73, 0x00, 0x70, 0x68,
|
||||
0x79, 0x2d, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x72, 0x65, 0x66, 0x2d, 0x63,
|
||||
0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x6e, 0x75, 0x6d, 0x00, 0x63, 0x6c, 0x6f,
|
||||
0x63, 0x6b, 0x2d, 0x66, 0x72, 0x65, 0x71, 0x75, 0x65, 0x6e, 0x63, 0x79,
|
||||
0x00, 0x63, 0x75, 0x72, 0x72, 0x65, 0x6e, 0x74, 0x2d, 0x73, 0x70, 0x65,
|
||||
0x65, 0x64, 0x00, 0x64, 0x65, 0x76, 0x69, 0x63, 0x65, 0x5f, 0x74, 0x79,
|
||||
0x70, 0x65, 0x00, 0x72, 0x65, 0x67, 0x2d, 0x6f, 0x66, 0x66, 0x73, 0x65,
|
||||
0x74, 0x00, 0x72, 0x65, 0x67, 0x2d, 0x73, 0x68, 0x69, 0x66, 0x74, 0x00,
|
||||
0x6d, 0x67, 0x6d, 0x74, 0x70, 0x6f, 0x72, 0x74, 0x00
|
||||
};
|
||||
unsigned int zynqmp_dtb_len = 1521;
|
||||
@@ -1,98 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This file provides the base ZynqMP device tree
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
ranges;
|
||||
|
||||
interrupt-controller@f9010000 {
|
||||
compatible = "arm,gic-400";
|
||||
#address-cells = <0x02>;
|
||||
#interrupt-cells = <0x03>;
|
||||
reg = <0x00 0xf9010000 0x00 0x10000>;
|
||||
interrupt-controller;
|
||||
phandle = <0x01>;
|
||||
};
|
||||
|
||||
ethernet@ff0b0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x39 0x04>;
|
||||
reg = <0x00 0xff0b0000 0x00 0x1000>;
|
||||
phy-mode = "rgmii-id";
|
||||
ref-clock-num = <0>;
|
||||
};
|
||||
|
||||
ethernet@ff0c0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3b 0x04>;
|
||||
reg = <0x00 0xff0c0000 0x00 0x1000>;
|
||||
phy-mode = "rgmii-id";
|
||||
ref-clock-num = <1>;
|
||||
};
|
||||
|
||||
ethernet@ff0d0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3d 0x04>;
|
||||
reg = <0x00 0xff0d0000 0x00 0x1000>;
|
||||
phy-mode = "rgmii-id";
|
||||
ref-clock-num = <2>;
|
||||
};
|
||||
|
||||
ethernet@ff0e0000 {
|
||||
compatible = "cdns,gem";
|
||||
status = "okay";
|
||||
interrupt-parent = <0x01>;
|
||||
interrupts = <0x00 0x3f 0x04>;
|
||||
reg = <0x00 0xff0e0000 0x00 0x1000>;
|
||||
phy-mode = "rgmii-id";
|
||||
ref-clock-num = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,105 +0,0 @@
|
||||
unsigned char zynqmp_dtb[] = {
|
||||
0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x04, 0xbd, 0x00, 0x00, 0x00, 0x38,
|
||||
0x00, 0x00, 0x04, 0x24, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
|
||||
0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99,
|
||||
0x00, 0x00, 0x03, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x01, 0x61, 0x6d, 0x62, 0x61, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1b,
|
||||
0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
|
||||
0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x01,
|
||||
0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,
|
||||
0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x40, 0x66, 0x39, 0x30,
|
||||
0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1b, 0x61, 0x72, 0x6d, 0x2c,
|
||||
0x67, 0x69, 0x63, 0x2d, 0x34, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2d,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x62, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0b, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x82, 0x72, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x2d, 0x69, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x63, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3b,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x82, 0x72, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x2d, 0x69, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x64, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3d,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0d, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x82, 0x72, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x2d, 0x69, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
|
||||
0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x65, 0x30, 0x30, 0x30,
|
||||
0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
|
||||
0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
|
||||
0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
|
||||
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
|
||||
0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
|
||||
0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0e, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x82, 0x72, 0x67, 0x6d, 0x69,
|
||||
0x69, 0x2d, 0x69, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73,
|
||||
0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23, 0x73, 0x69, 0x7a, 0x65,
|
||||
0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63, 0x6f, 0x6d, 0x70, 0x61,
|
||||
0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x72, 0x61, 0x6e, 0x67, 0x65, 0x73,
|
||||
0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
|
||||
0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65, 0x67, 0x00, 0x69, 0x6e,
|
||||
0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f, 0x6e, 0x74,
|
||||
0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70, 0x68, 0x61, 0x6e, 0x64,
|
||||
0x6c, 0x65, 0x00, 0x73, 0x74, 0x61, 0x74, 0x75, 0x73, 0x00, 0x69, 0x6e,
|
||||
0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x70, 0x61, 0x72, 0x65,
|
||||
0x6e, 0x74, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74,
|
||||
0x73, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x72,
|
||||
0x65, 0x66, 0x2d, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x6e, 0x75, 0x6d,
|
||||
0x00
|
||||
};
|
||||
unsigned int zynqmp_dtb_len = 1213;
|
||||
@@ -1,134 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This header file provides BSP-specific interfaces.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H
|
||||
#define LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#define BSP_FEATURE_IRQ_EXTENSION
|
||||
|
||||
#define BSP_RESET_SMC
|
||||
|
||||
#define BSP_CPU_ON_USES_SMC
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <bsp/default-initial-extension.h>
|
||||
#include <bsp/start.h>
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#include <dev/serial/zynq-uart-zynqmp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
struct rtems_termios_device_context;
|
||||
|
||||
/**
|
||||
* @defgroup RTEMSBSPsAArch64XilinxZynqMP \
|
||||
* AMD Zynq UltraScale+ MPSoC and RFSoC - Application Processing Unit
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @brief This group contains the BSP for the Application Processing Unit (APU)
|
||||
* contained in AMD Zynq UltraScale+ MPSoC and RFSoC devices.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*
|
||||
* DDRMC mapping
|
||||
*/
|
||||
LINKER_SYMBOL(bsp_r0_ram_base)
|
||||
LINKER_SYMBOL(bsp_r0_ram_end)
|
||||
LINKER_SYMBOL(bsp_r1_ram_base)
|
||||
LINKER_SYMBOL(bsp_r1_ram_end)
|
||||
|
||||
#define BSP_ARM_GIC_CPUIF_BASE 0xf9020000
|
||||
#define BSP_ARM_GIC_DIST_BASE 0xf9010000
|
||||
|
||||
#define BSP_FDT_IS_SUPPORTED
|
||||
extern unsigned int zynqmp_dtb_len;
|
||||
extern unsigned char zynqmp_dtb[];
|
||||
|
||||
#define NANDPSU_BASEADDR 0xFF100000
|
||||
|
||||
/**
|
||||
* @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
|
||||
*
|
||||
* Provide in the application to override the defaults in the BSP.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void zynqmp_setup_mmu_and_cache(void);
|
||||
|
||||
/**
|
||||
* @brief Zynq UltraScale+ MPSoC specific set up of the MMU for non-primary
|
||||
* cores.
|
||||
*
|
||||
* Provide in the application to override the defaults in the BSP.
|
||||
*/
|
||||
BSP_START_TEXT_SECTION void zynqmp_setup_secondary_cpu_mmu_and_cache( void );
|
||||
|
||||
void zynqmp_management_console_termios_init(void);
|
||||
|
||||
void zynqmp_debug_console_flush(void);
|
||||
|
||||
uint32_t zynqmp_clock_i2c0(void);
|
||||
|
||||
uint32_t zynqmp_clock_i2c1(void);
|
||||
|
||||
/**
|
||||
* @brief Zynq UltraScale+ MPSoC specific set up of a management console.
|
||||
*
|
||||
* Some systems may have a management interface which needs special
|
||||
* initialization. Provide in the application to override the defaults in the
|
||||
* BSP. This will only be called if the interface is found in the device tree.
|
||||
*/
|
||||
void zynqmp_configure_management_console(
|
||||
struct rtems_termios_device_context *base
|
||||
);
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_H */
|
||||
@@ -1,211 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This header file provides internal APIs for managing ECC events.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H
|
||||
#define LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
//#include <bspopts.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/**
|
||||
* @brief Enumeration describing the possible types of ECC events
|
||||
*/
|
||||
typedef enum {
|
||||
/* L1 Cache event information is delivered via Cache_Error_Info struct. */
|
||||
L1_CACHE,
|
||||
/* L2 Cache event information is delivered via Cache_Error_Info struct. */
|
||||
L2_CACHE,
|
||||
/*
|
||||
* L1 and L2 cache are on a combined interrupt on ZynqMP. They are enabled as
|
||||
* a single unit. The above individual L1 and L2 cache definitions will be
|
||||
* used for reporting. Attempting to enable L1 or L2 individually will enable
|
||||
* both.
|
||||
*/
|
||||
L1_L2_CACHE,
|
||||
/* OCM RAM event information is delivered via OCM_Error_Info struct. */
|
||||
OCM_RAM,
|
||||
/* DDR RAM event information is delivered via DDR_Error_Info struct. */
|
||||
DDR_RAM,
|
||||
} ECC_Event_Type;
|
||||
|
||||
/**
|
||||
* @brief The specific locations where a cache error can originate
|
||||
*/
|
||||
typedef enum {
|
||||
RAM_ID_L1I_TAG,
|
||||
RAM_ID_L1I_DATA,
|
||||
RAM_ID_L1D_TAG,
|
||||
RAM_ID_L1D_DATA,
|
||||
RAM_ID_L1D_DIRTY,
|
||||
RAM_ID_TLB,
|
||||
RAM_ID_L2_TAG,
|
||||
RAM_ID_L2_DATA,
|
||||
RAM_ID_SCU,
|
||||
RAM_ID_UNKNOWN
|
||||
} Cache_Error_RAM_ID;
|
||||
|
||||
/**
|
||||
* @brief Structure containing information about a Cache error
|
||||
*/
|
||||
typedef struct {
|
||||
/* Indicates the RAM index address */
|
||||
uint64_t address;
|
||||
/* Indicates the type of RAM where the error originated */
|
||||
Cache_Error_RAM_ID ramid;
|
||||
/*
|
||||
* Indicates the segment (way or bank) of the RAM where the error originated.
|
||||
* Does not apply to L1D_DIRTY RAM ID. For SCU errors, this also indicates the
|
||||
* associated CPU.
|
||||
*/
|
||||
uint8_t segment;
|
||||
/* The number of times this specific error has occurred since last reset */
|
||||
uint8_t repeats;
|
||||
/* The number of times other errors have occurred since last reset */
|
||||
uint8_t other_errors;
|
||||
/* Whether any of the errors represented have caused a data abort */
|
||||
bool abort;
|
||||
} Cache_Error_Info;
|
||||
|
||||
/**
|
||||
* @brief Typedef for ECC handlers
|
||||
*
|
||||
* Functions matching this prototype can be registered as the handler for ECC
|
||||
* event callbacks. The data argument is a struct describing the event that
|
||||
* occurred.
|
||||
*/
|
||||
typedef void (*zynqmp_ecc_handler)( ECC_Event_Type event, void *data );
|
||||
|
||||
/**
|
||||
* @brief Enumeration describing the possible types of ECC events
|
||||
*
|
||||
* Note that the provided handler may be called from interrupt context.
|
||||
*
|
||||
* @param handler The handler to be called for all ECC error events
|
||||
*/
|
||||
void zynqmp_ecc_register_handler( zynqmp_ecc_handler handler );
|
||||
|
||||
/**
|
||||
* @brief Enable ECC error reporting
|
||||
*
|
||||
* Enables ECC error reporting for the specified subsystem.
|
||||
*
|
||||
* @param event The ECC error event type to enable
|
||||
*/
|
||||
int zynqmp_ecc_enable( ECC_Event_Type event );
|
||||
|
||||
/**
|
||||
* @brief Injects an ECC fault in the On-Chip Memory (OCM)
|
||||
*/
|
||||
void zynqmp_ocm_inject_fault( void );
|
||||
|
||||
/**
|
||||
* @brief The types of OCM ECC errors
|
||||
*/
|
||||
typedef enum {
|
||||
OCM_UNCORRECTABLE,
|
||||
OCM_UNCORRECTABLE_RMW,
|
||||
OCM_CORRECTABLE
|
||||
} OCM_Error_Type;
|
||||
|
||||
/**
|
||||
* @brief Structure containing information about a OCM ECC error
|
||||
*/
|
||||
typedef struct {
|
||||
/* Describes the type of error being reported */
|
||||
OCM_Error_Type type;
|
||||
/* The offset into OCM where the error occurred */
|
||||
uint32_t offset;
|
||||
/* The data relevant to the error. Does not apply to RMW errors */
|
||||
uint32_t data0;
|
||||
uint32_t data1;
|
||||
uint32_t data2;
|
||||
uint32_t data3;
|
||||
/* The ECC syndrome relevant to the error. Does not apply to RMW errors */
|
||||
uint16_t syndrome;
|
||||
} OCM_Error_Info;
|
||||
|
||||
/**
|
||||
* @brief The types of DDR ECC errors
|
||||
*/
|
||||
typedef enum {
|
||||
DDR_UNCORRECTABLE,
|
||||
DDR_CORRECTABLE
|
||||
} DDR_Error_Type;
|
||||
|
||||
/**
|
||||
* @brief Structure containing information about a DDR ECC error
|
||||
*/
|
||||
typedef struct {
|
||||
/* Describes the type of error being reported */
|
||||
DDR_Error_Type type;
|
||||
/* The DDR Rank where the error occurred */
|
||||
uint32_t rank;
|
||||
/* The DDR Bank Group where the error occurred */
|
||||
uint32_t bank_group;
|
||||
/* The DDR Bank where the error occurred */
|
||||
uint32_t bank;
|
||||
/* The DDR Row where the error occurred */
|
||||
uint32_t row;
|
||||
/* The DDR Column where the error occurred */
|
||||
uint32_t column;
|
||||
/*
|
||||
* When mapping from SDRAM addressing back to AXI addressing, this is will
|
||||
* only be a close approximation of the source address since bits can be
|
||||
* discarded when converting from AXI to SDRAM.
|
||||
*/
|
||||
uint64_t address;
|
||||
} DDR_Error_Info;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_H */
|
||||
@@ -1,104 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This header file provides internal APIs for managing ECC events.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_PRIV_H
|
||||
#define LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_PRIV_H
|
||||
|
||||
/**
|
||||
* @addtogroup RTEMSBSPsAArch64
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include <bspopts.h>
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <bsp/ecc.h>
|
||||
|
||||
/**
|
||||
* @brief Initialize ECC reporting support
|
||||
*
|
||||
* This initializes the base ECC event reporting support for the platform.
|
||||
*/
|
||||
void zynqmp_ecc_init( void );
|
||||
|
||||
/**
|
||||
* @brief Initialize BSP-specific ECC reporting
|
||||
*
|
||||
* Various BSPs may have different ECC capabilities. This allows those BSPs to
|
||||
* initialize those facilities as necessary.
|
||||
*/
|
||||
void zynqmp_ecc_init_bsp( void );
|
||||
|
||||
/**
|
||||
* @brief Configure Cache ECC reporting
|
||||
*/
|
||||
rtems_status_code zynqmp_configure_cache_ecc( void );
|
||||
|
||||
/**
|
||||
* @brief Configure On-Chip Memory (OCM) ECC reporting
|
||||
*/
|
||||
rtems_status_code zynqmp_configure_ocm_ecc( void );
|
||||
|
||||
/**
|
||||
* @brief Configure DDR Memory ECC reporting
|
||||
*/
|
||||
rtems_status_code zynqmp_configure_ddr_ecc( void );
|
||||
|
||||
/**
|
||||
* @brief Invoke the ECC error handler
|
||||
*
|
||||
* @param event The ECC error event type to be raised
|
||||
* @param data The details associated with the raised ECC error
|
||||
*/
|
||||
void zynqmp_invoke_ecc_handler( ECC_Event_Type event, void *data );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_ZYNQMP_BSP_ECC_PRIV_H */
|
||||
@@ -1,64 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2021 On-Line Applications Research (OAR)
|
||||
* Copyright (C) 2014 embedded brains GmbH & Co. KG
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_ARM_XILINX_ZYNQ_I2C_H
|
||||
#define LIBBSP_ARM_XILINX_ZYNQ_I2C_H
|
||||
|
||||
#include <dev/i2c/cadence-i2c.h>
|
||||
#include <bsp/irq.h>
|
||||
#include <bsp.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
static inline int zynqmp_register_i2c_0(void)
|
||||
{
|
||||
return i2c_bus_register_cadence(
|
||||
"/dev/i2c-0",
|
||||
0x00FF020000,
|
||||
zynqmp_clock_i2c0(),
|
||||
ZYNQMP_IRQ_I2C_0
|
||||
);
|
||||
}
|
||||
|
||||
static inline int zynqmp_register_i2c_1(void)
|
||||
{
|
||||
return i2c_bus_register_cadence(
|
||||
"/dev/i2c-1",
|
||||
0x00FF030000,
|
||||
zynqmp_clock_i2c1(),
|
||||
ZYNQMP_IRQ_I2C_1
|
||||
);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_ARM_XILINX_ZYNQ_I2C_H */
|
||||
@@ -1,76 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup RTEMSBSPsAArch64XilinxZynqMP
|
||||
*
|
||||
* @brief This header file provides the BSP's IRQ definitions.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
|
||||
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_AARCH64_XILINX_ZYNQMP_IRQ_H
|
||||
#define LIBBSP_AARCH64_XILINX_ZYNQMP_IRQ_H
|
||||
|
||||
#ifndef ASM
|
||||
|
||||
#include <rtems.h>
|
||||
|
||||
#include <dev/irq/arm-gic-irq.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define BSP_INTERRUPT_VECTOR_COUNT 192
|
||||
|
||||
/* Interrupts vectors */
|
||||
#define BSP_TIMER_VIRT_PPI 27
|
||||
#define BSP_TIMER_PHYS_NS_PPI 30
|
||||
#define ZYNQMP_IRQ_OCM 42
|
||||
#define ZYNQMP_IRQ_QSPI 47
|
||||
#define ZYNQMP_IRQ_I2C_0 49
|
||||
#define ZYNQMP_IRQ_I2C_1 50
|
||||
#define ZYNQMP_IRQ_UART_0 53
|
||||
#define ZYNQMP_IRQ_UART_1 54
|
||||
#define ZYNQMP_IRQ_ETHERNET_0 89
|
||||
#define ZYNQMP_IRQ_ETHERNET_1 91
|
||||
#define ZYNQMP_IRQ_ETHERNET_2 93
|
||||
#define ZYNQMP_IRQ_ETHERNET_3 95
|
||||
#define ZYNQMP_IRQ_DDR 144
|
||||
#define ZYNQMP_IRQ_CACHE 183
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* ASM */
|
||||
|
||||
#endif /* LIBBSP_AARCH64_XILINX_ZYNQMP_IRQ_H */
|
||||
@@ -1,56 +0,0 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause */
|
||||
|
||||
/*
|
||||
* Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef LIBBSP_XILINX_ZYNQMP_JFFS2_XNANDPSU_H
|
||||
#define LIBBSP_XILINX_ZYNQMP_JFFS2_XNANDPSU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#include <dev/nand/xnandpsu.h>
|
||||
#include <rtems/jffs2.h>
|
||||
|
||||
/**
|
||||
* @brief Mount JFFS2 filesystem on NAND device.
|
||||
*
|
||||
* @param[in] mount_dir The directory to mount the filesystem at.
|
||||
* @param[in] NandPsuInstancePtr A pointer to an initialized NAND instance.
|
||||
*
|
||||
* @retval 0 Successful operation. Negative number otherwise.
|
||||
*/
|
||||
int xilinx_zynqmp_nand_jffs2_initialize(
|
||||
const char *mount_dir,
|
||||
XNandPsu *NandPsuInstancePtr
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* LIBBSP_XILINX_ZYNQMP_JFFS2_XNANDPSU_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user