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https://gitlab.rtems.org/rtems/rtos/rtems.git
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b48166b9b6
This adds error reporting for ZynqMP including L1 and L2 cache, on-chip memory (OCM) error correcting code (ECC), and DDR ECC. OCM ECC supports fault injection from within RTEMS. DDR ECC technically supports fault injection as well, but requires that the program injecting faults operate exclusively outside of DDR. The AArch64 port is not currently capable of operating exclusively in OCM due to size constraints and would need to be booted via JTAG or via a non-relocating u-boot to accomplish this.
301 lines
9.5 KiB
C
301 lines
9.5 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsAArch64XilinxZynqMP
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*
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* @brief This source file contains the implementation of OCM ECC support.
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*/
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/*
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* Copyright (C) 2023 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/ecc_priv.h>
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#include <bsp/irq.h>
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#include <bsp/utility.h>
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#include <libcpu/mmu-vmsav8-64.h>
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static uintptr_t ocm_base = 0xFF960000;
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/* ECC Control */
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#define OCM_ECC_CTRL 0x14
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/* 0 -> single error, 1 -> continuous errors */
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#define OCM_ECC_CTRL_FI_MODE BSP_BIT32(2)
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/* When bit is set, detection occurs without correction */
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#define OCM_ECC_CTRL_DET_ONLY BSP_BIT32(1)
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/* Enable ECC, should only be modified at system boot */
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#define OCM_ECC_CTRL_ECC_ON_OFF BSP_BIT32(0)
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/* Interrupt Enable */
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#define OCM_IE 0xc
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#define OCM_IE_UE_RMW BSP_BIT32(10)
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#define OCM_IE_UE BSP_BIT32(7)
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#define OCM_IE_CE BSP_BIT32(6)
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/* Error Response Control */
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#define OCM_ERR_CTRL 0x0
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#define OCM_ERR_CTRL_UE_RES BSP_BIT32(3)
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/*
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* Fault Injection Data, four registers comprising 16 bytes of a data word
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*
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* Bits set to 1 toggle the corresponding bits of the next written word during a
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* fault injection.
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*/
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#define OCM_FI_D0 0x4c
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#define OCM_FI_D1 0x50
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#define OCM_FI_D2 0x54
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#define OCM_FI_D3 0x58
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/* Fault Injection Syndrome */
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#define OCM_FI_SY 0x5c
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#define OCM_FI_SY_DATA(val) BSP_FLD32(val, 0, 15)
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#define OCM_FI_SY_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
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#define OCM_FI_SY_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
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/* Fault Injection Counter */
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#define OCM_FI_CNTR 0x74
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#define OCM_FI_CNTR_COUNT(val) BSP_FLD32(val, 0, 23)
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#define OCM_FI_CNTR_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 23)
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#define OCM_FI_CNTR_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 23)
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/* Interrupt Status */
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#define OCM_IS 0x4
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#define OCM_IS_UE_RMW BSP_BIT32(10)
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#define OCM_IS_UE BSP_BIT32(7)
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#define OCM_IS_CE BSP_BIT32(6)
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/* Interrupt Mask */
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#define OCM_IM 0x8
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#define OCM_IM_UE_RMW BSP_BIT32(10)
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#define OCM_IM_UE BSP_BIT32(7)
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#define OCM_IM_CE BSP_BIT32(6)
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void zynqmp_ocm_inject_fault( void )
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{
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volatile uint32_t *fi_d0 = (uint32_t*)(ocm_base + OCM_FI_D0);
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volatile uint32_t *fi_cnt = (uint32_t*)(ocm_base + OCM_FI_CNTR);
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volatile uint64_t *ocm_top = (uint64_t*)0xFFFFFFF0U;
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volatile uint32_t *ecc_ctrl = (uint32_t*)(ocm_base + OCM_ECC_CTRL);
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uint64_t ocm_tmp = *ocm_top;
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/* Configure OCM to throw constant errors */
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*ecc_ctrl |= OCM_ECC_CTRL_FI_MODE;
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/* Inject a single bit error */
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*fi_d0 = 1;
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/* Configure the clock count after which errors will begin */
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*fi_cnt = 0;
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/* Insert a memory barrier to ensure that fault injection is active */
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_AARCH64_Data_synchronization_barrier();
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/* trigger fault with a write of data that was already at the given address */
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*ocm_top = 0;
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/* Insert a memory barrier to prevent optimization */
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_AARCH64_Data_synchronization_barrier();
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/* Perform read to force reporting of the error */
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*ocm_top;
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/* Disable constant fault mode */
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*ecc_ctrl &= ~(OCM_ECC_CTRL_FI_MODE);
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/* Insert a memory barrier to ensure the mode has changed */
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_AARCH64_Data_synchronization_barrier();
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/* Reset to original value now that constant errors are disabled */
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*ocm_top = ocm_tmp;
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}
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/* Correctable Error First Failing Address */
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#define OCM_CE_FFA 0x1c
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#define OCM_CE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
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#define OCM_CE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
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#define OCM_CE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
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/* Correctable Error First Failing Data, four registers comprising 16 bytes */
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#define OCM_CE_FFD0 0x20
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#define OCM_CE_FFD1 0x24
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#define OCM_CE_FFD2 0x28
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#define OCM_CE_FFD3 0x2c
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/* Correctable Error First Failing ECC */
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#define OCM_CE_FFE 0x1c
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#define OCM_CE_FFE_SYNDROME(val) BSP_FLD32(val, 0, 15)
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#define OCM_CE_FFE_SYNDROME_GET(reg) BSP_FLD32GET(reg, 0, 15)
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#define OCM_CE_FFE_SYNDROME_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
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/* Uncorrectable Error First Failing Address */
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#define OCM_UE_FFA 0x34
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#define OCM_UE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
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#define OCM_UE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
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#define OCM_UE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
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/* Uncorrectable Error First Failing Data, four registers comprising 16 bytes */
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#define OCM_UE_FFD0 0x38
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#define OCM_UE_FFD1 0x3c
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#define OCM_UE_FFD2 0x40
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#define OCM_UE_FFD3 0x44
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/* Uncorrectable Error First Failing ECC */
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#define OCM_UE_FFE 0x48
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#define OCM_UE_FFE_SYNDROME(val) BSP_FLD32(val, 0, 15)
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#define OCM_UE_FFE_SYNDROME_GET(reg) BSP_FLD32GET(reg, 0, 15)
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#define OCM_UE_FFE_SYNDROME_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
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/* Read/Modify/Write Uncorrectable Error First Failing Address */
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#define OCM_RMW_UE_FFA 0x70
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#define OCM_RMW_UE_FFA_ADDR(val) BSP_FLD32(val, 0, 17)
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#define OCM_RMW_UE_FFA_ADDR_GET(reg) BSP_FLD32GET(reg, 0, 17)
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#define OCM_RMW_UE_FFA_ADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 17)
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static void ocm_handle_rmw( void )
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{
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volatile uint32_t *rmw_ffa = (uint32_t*)(ocm_base + OCM_RMW_UE_FFA);
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OCM_Error_Info info;
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info.type = OCM_UNCORRECTABLE_RMW;
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info.offset = OCM_RMW_UE_FFA_ADDR_GET(*rmw_ffa);
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zynqmp_invoke_ecc_handler(OCM_RAM, &info);
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}
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static void ocm_handle_ce( void )
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{
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volatile uint32_t *ce_ffa = (uint32_t*)(ocm_base + OCM_CE_FFA);
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volatile uint32_t *ce_ffe = (uint32_t*)(ocm_base + OCM_CE_FFA);
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volatile uint32_t *ce_ffd0 = (uint32_t*)(ocm_base + OCM_CE_FFD0);
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volatile uint32_t *ce_ffd1 = (uint32_t*)(ocm_base + OCM_CE_FFD1);
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volatile uint32_t *ce_ffd2 = (uint32_t*)(ocm_base + OCM_CE_FFD2);
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volatile uint32_t *ce_ffd3 = (uint32_t*)(ocm_base + OCM_CE_FFD3);
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OCM_Error_Info info;
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info.type = OCM_CORRECTABLE;
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info.offset = OCM_CE_FFA_ADDR_GET(*ce_ffa);
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info.data0 = *ce_ffd0;
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info.data1 = *ce_ffd1;
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info.data2 = *ce_ffd2;
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info.data3 = *ce_ffd3;
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info.syndrome = OCM_CE_FFE_SYNDROME_GET(*ce_ffe);
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zynqmp_invoke_ecc_handler(OCM_RAM, &info);
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}
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static void ocm_handle_ue( void )
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{
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volatile uint32_t *ue_ffa = (uint32_t*)(ocm_base + OCM_UE_FFA);
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volatile uint32_t *ue_ffe = (uint32_t*)(ocm_base + OCM_UE_FFA);
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volatile uint32_t *ue_ffd0 = (uint32_t*)(ocm_base + OCM_UE_FFD0);
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volatile uint32_t *ue_ffd1 = (uint32_t*)(ocm_base + OCM_UE_FFD1);
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volatile uint32_t *ue_ffd2 = (uint32_t*)(ocm_base + OCM_UE_FFD2);
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volatile uint32_t *ue_ffd3 = (uint32_t*)(ocm_base + OCM_UE_FFD3);
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OCM_Error_Info info;
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info.type = OCM_UNCORRECTABLE;
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info.offset = OCM_UE_FFA_ADDR_GET(*ue_ffa);
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info.data0 = *ue_ffd0;
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info.data1 = *ue_ffd1;
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info.data2 = *ue_ffd2;
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info.data3 = *ue_ffd3;
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info.syndrome = OCM_UE_FFE_SYNDROME_GET(*ue_ffe);
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zynqmp_invoke_ecc_handler(OCM_RAM, &info);
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}
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static void ocm_handler(void *arg)
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{
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volatile uint32_t *ocm_is = (uint32_t*)(ocm_base + OCM_IS);
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uint32_t ocm_is_value = *ocm_is;
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(void) arg;
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/* Check and clear each error type after handling */
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if ((ocm_is_value & OCM_IS_UE_RMW) != 0) {
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ocm_handle_rmw();
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*ocm_is = OCM_IS_UE_RMW;
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}
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if ((ocm_is_value & OCM_IS_CE) != 0) {
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ocm_handle_ce();
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*ocm_is = OCM_IS_CE;
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}
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if ((ocm_is_value & OCM_IS_UE) != 0) {
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ocm_handle_ue();
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*ocm_is = OCM_IS_UE;
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}
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}
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static rtems_interrupt_entry zynqmp_ocm_ecc_entry;
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rtems_status_code zynqmp_configure_ocm_ecc( void )
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{
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volatile uint32_t *err_ctrl = (uint32_t*)(ocm_base + OCM_ERR_CTRL);
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volatile uint32_t *ecc_ctrl = (uint32_t*)(ocm_base + OCM_ECC_CTRL);
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volatile uint32_t *int_enable = (uint32_t*)(ocm_base + OCM_IE);
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rtems_status_code sc;
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rtems_interrupt_entry_initialize(
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&zynqmp_ocm_ecc_entry,
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ocm_handler,
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NULL,
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"OCM RAM ECC"
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);
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sc = rtems_interrupt_entry_install(
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ZYNQMP_IRQ_OCM,
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RTEMS_INTERRUPT_SHARED,
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&zynqmp_ocm_ecc_entry
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);
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if (sc != RTEMS_SUCCESSFUL) {
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return sc;
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}
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if ((*ecc_ctrl & OCM_ECC_CTRL_ECC_ON_OFF) == 0) {
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/*
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* ECC is not enabled and should already have been by BOOT.bin. Enabling it
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* now could corrupt existing data in the OCM.
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*/
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return RTEMS_NOT_CONFIGURED;
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}
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/*
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* OCM_ERR_CTRL.UE_RES forces generation of a synchronous external abort
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* instead of using interrupts to signal the fault
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*/
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*err_ctrl &= ~(OCM_ERR_CTRL_UE_RES);
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/* Ensure ECC_CTRL is in the right state */
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*ecc_ctrl &= ~(OCM_ECC_CTRL_DET_ONLY);
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/* enable correctable and uncorrectable error interrupts */
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*int_enable = OCM_IE_CE | OCM_IE_UE | OCM_IE_UE_RMW;
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return RTEMS_SUCCESSFUL;
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}
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