In CLANG_PLUGIN_FILE it is possible for plugin_file to be non-NULL
when LLVMgold.so does not exist.
configure output is messy, with results not printed against their
"checking.." line, eg.
checking for clang... (cached) yes
checking for clang plugin file... checking for x86_64-pc-linux-gnu-ar... (cached) ar --plugin /usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so
/usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so
This patch fixes those problems, and a similar interposition of other
configure output between AC_MSG_CHECKING and AC_MSG_RESULT in
gcc-plugin.m4. It also tidies some of the message text, and makes
similar code in gcc-plugin.m4 and clang-plugin.m4 a little more
consistent.
config/
* clang-plugin.m4 (CLANG_PLUGIN_FILE): Don't place checks for
tools (llvm-config, ar) inside AC_MSG_CHECKING..AC_MSG_RESULT
for clang plugin file. Clear plugin_file before loop exit.
(CLANG_PLUGIN_FILE_FOR_TARGET): Similarly.
* gcc-plugin.m4 (GCC_PLUGIN_OPTION): Similarly.
(GCC_PLUGIN_OPTION_FOR_TARGET): Correct AC_MSG_CHECKING. Tidy
return code.
binutils/
* testsuite/lib/binutils-common.exp <llvm_plug_opt>: Set for
non-native.
* configure: Regenerate.
/
* configure: Regenerate.
bfd/
* configure: Regenerate.
gas/
* configure: Regenerate.
gdb/
* configure: Regenerate.
gprof/
* configure: Regenerate.
gprofng/
* configure: Regenerate.
* libcollector/configure: Regenerate.
ld/
* configure: Regenerate.
libbacktrace/
* configure: Regenerate.
libctf/
* configure: Regenerate.
libiberty/
* configure: Regenerate.
libsframe/
* configure: Regenerate.
opcodes/
* configure: Regenerate.
sim/
* configure: Regenerate.
zlib/
* configure: Regenerate.
Complementing commit 7ea90d9316 ("MIPS: Fix linker for REL TLS
HI16/LO16 relocs") also add pairing for HI16/LO16 REL TLS relocations
in GAS, which is where it needs to be done in the first place and
which is required for later linker operation on the objects produced.
Pairing also corrects in-place addend installation for the high-part
relocations, which used not to happen in the absence of this fix for
ones not already followed by the corresponding low-part relocation.
Add test cases to verify relocation ordering and addend installation.
Fix `micromips_reloc_p' wrongly classifying microMIPS TLS relocations
as non microMIPS relocations.
Owing to where the function is called this issue does not trigger in
reality, but with an upcoming change it would, where suitable tests
will be included.
MIPS/VxWorks targets have an unusual arrangement in that they use RELA
relocations with the o32 ABI, unlike any other MIPS target. Due to an
inconsistency in BFD however "hybrid" relocations are produced by GAS,
where despite the relocations being of the RELA type the field to be
relocated also holds an in-place addend to be applied at link time.
For example:
$ cat vxworks-rela.s
.text
foo:
la $2, bar + 0x12345678
$ mips-vxworks-as -o vxworks-rela.o vxworks-rela.s
$ mips-vxworks-objdump -dr vxworks-rela.o
vxworks-rela.o: file format elf32-bigmips-vxworks
Disassembly of section .text:
00000000 <foo>:
0: 3c021234 lui v0,0x1234
0: R_MIPS_HI16 bar+0x12345678
4: 24425678 addiu v0,v0,22136
4: R_MIPS_LO16 bar+0x12345678
$
This is due to the BFD backend being strapped for RELA relocations:
#undef elf_backend_may_use_rel_p
#define elf_backend_may_use_rel_p 0
#undef elf_backend_may_use_rela_p
#define elf_backend_may_use_rela_p 1
#undef elf_backend_default_use_rela_p
#define elf_backend_default_use_rela_p 1
but the howtos in use requesting an in-place addend, e.g.:
/* High 16 bits of symbol value. */
HOWTO (R_MIPS_HI16, /* type */
16, /* rightshift */
4, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_mips_elf_hi16_reloc, /* special_function */
"R_MIPS_HI16", /* name */
true, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
/* Low 16 bits of symbol value. */
HOWTO (R_MIPS_LO16, /* type */
0, /* rightshift */
4, /* size */
16, /* bitsize */
false, /* pc_relative */
0, /* bitpos */
complain_overflow_dont, /* complain_on_overflow */
_bfd_mips_elf_lo16_reloc, /* special_function */
"R_MIPS_LO16", /* name */
true, /* partial_inplace */
0x0000ffff, /* src_mask */
0x0000ffff, /* dst_mask */
false), /* pcrel_offset */
This arrangement nevertheless happens to produce correct ELF executables
owing to the ELF linker avoiding the use of howtos and doing relocation
calculations using its own knowledge of relocation semantics embedded
directly in `mips_elf_calculate_relocation' code.
Beyond producing questionable link object files it however breaks badly
with the generic linker, such as when output is srec.
Fix the problem by providing a set of o32 RELA howtos and making VxWorks
targets use it. Complement it with a set of test cases for GAS and LD;
we expect link object files to be essentially the same as n32 ones for
other MIPS targets sans the ABI2 ELF file header flag, and machine code
produced to be the same between SREC and ELF executables.
In Binutils, we choose to keep the AMX-TRANSPOSE support for
now in case there are vendors want to utilize the instructions
although the feature itself is de-published. AMX-TRANSPOSE will
not show up on any Intel/AMD hardware. Also in foreseeable future,
no hardware will support AMX-TRANSPOSE, we will disable it by
default.
gas/ChangeLog:
* testsuite/gas/i386/x86-64-amx-movrs-intel.d:
Move AMX-TRANSPOSE part to AMX-TRANSPOSE test.
* testsuite/gas/i386/x86-64-amx-movrs.d: Ditto.
* testsuite/gas/i386/x86-64-amx-movrs.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-bad.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32.d: Ditto.
* testsuite/gas/i386/x86-64-amx-tf32.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto.
* testsuite/gas/i386/x86-64-amx-movrs-inval.l: Move
AMX-TRANSPOSE part to AMX-TRANSPOSE file. Remove
noamx_transpose test.
* testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-bad.d:
Add AMX-MOVRS and AMX-TF32 related test.
* testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose.s: Ditto.
* testsuite/gas/i386/x86-64.exp: Remove AMX-MOVRS invalid test.
* testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d:
New test originally comes from APX_F test.
* testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-apx.d: Ditto.
* testsuite/gas/i386/x86-64-amx-transpose-apx.s: Ditto.
opcodes/ChangeLog:
* i386-gen.c: Disable AMX-TRANSPOSE by default.
* i386-init.h: Regenerated.
This reverts commit bafcf0823c.
The patch (the removal) was done on the wrong assumption that
it was only the APX-promoted forms which would be dropped
because the APX spec was updated ahead of ISE and there was no
info that AMX-TRANSPOSE would be de-published at that time.
Given the current situation, since we will choose to disable
AMX-TRANSPOSE but not to remove the support in Binutils, we will
also not remove the APX support.
For arithmetic ops, Z80 syntax wants "op A,x" for ADD, ADC and SBC and
"op x" for SUB, AND, OR, XOR, and CP. Many historical assemblers
simply treat them orthogonally; allowing but not requiring the "A,"
operand for any of these operations. This is widely used in legacy
source code, and there is no reason not to.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
In DWARF CFI an "undefined" register rule for the return address (RA)
register indicates that there is no return address and the stack trace
is complete.
Represent DW_CFA_undefined as SFrame FRE without any offsets, so that a
stack tracer implementation can use this as indication that an outermost
frame has been reached and the stack trace is complete.
This representation is backward compatible, as existing stack tracers
should already deal with the case, that an SFrame FRE a so far invalid
offset count of zero and stop the trace.
include/
* sframe.h (SFRAME_V2_FRE_RA_UNDEFINED_P): New macro to test
FRE info word for RA undefined (FRE without any offsets).
binutils/
* NEWS: Mention SFrame can represent an undefined RA as FRE
without any offsets.
gas/
* gen-sframe.h (struct sframe_row_entry): Add ra_undefined_p
flag.
* gen-sframe.c (sframe_row_entry_new): Initialize ra_undefined_p
flag to not set.
(sframe_row_entry_initialize): Treat ra_undefined_p flag as
sticky.
(sframe_fre_set_ra_track): Reset ra_undefined_p flag.
(sframe_xlate_do_restore): Reset ra_undefined_p flag to saved
state.
(sframe_xlate_do_same_value): Reset ra_undefined_p flag.
(sframe_xlate_do_cfi_undefined): For RA set ra_undefined_p flag.
(output_sframe_row_entry): Represent RA undefined as SFrame FRE
without any offsets and FRE info word fields zeroed.
* NEWS: Mention assembler represents .cfi_undefined RA in SFrame
as FRE without any offsets.
libsframe/
* doc/sframe-spec.texi (Changes from Version 1 to Version 2):
Mention that a SFrame FRE without any offsets flag indicates an
outermost frame with an undefined RA.
(fre_offset_count): Document that a FRE offset count of zero
indicates an outermost frame with an undefined RA.
* sframe.c (sframe_get_fre_ra_undefined_p): Use macro
SFRAME_V2_FRE_RA_UNDEFINED_P.
(sframe_fre_get_fp_offset, sframe_fre_get_ra_offset): Do not
return fixed FP/RA offset if RA undefined.
* sframe-dump.c (dump_sframe_func_with_fres): Show FRE without
any offsets as "RA undefined".
gas/testsuite/
* gas/cfi-sframe/cfi-sframe.exp: Run tests for .cfi_undefined RA
on AArch64, s390x, and x86-64.
* gas/cfi-sframe/cfi-sframe-aarch64-ra-undefined-1.d: Add test
for .cfi_undefined RA on AArch64.
* gas/cfi-sframe/cfi-sframe-aarch64-ra-undefined-1.s: Likewise.
* as/cfi-sframe/cfi-sframe-s390x-ra-undefined-1.d: Add test
for .cfi_undefined RA on s390x.
* gas/cfi-sframe/cfi-sframe-s390x-ra-undefined-1.s: Likewise.
* gas/cfi-sframe/cfi-sframe-x86_64-ra-undefined-1.d: Add test
for .cfi_undefined RA on x86-64.
* gas/cfi-sframe/cfi-sframe-x86_64-ra-undefined-1.s: Likewise.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Allow SFrame sections without any FREs, that can occur if they solely
contain FDEs without any FREs. For FDEs without and FREs set the
offset to the first FRE to zero.
libsframe/
* sframe.c (sframe_encoder_write_sframe): Allow SFrame sections
without any FREs. For FDEs without any FREs set the offset to
the first FRE to zero.
gas/
* gen-sframe.c (output_sframe_funcdesc): For FDEs without any
FREs set the offset to the first FRE to zero.
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
While in the common case sections like .reloc don't need to be accessed
by a binary (that's the job of the loader), there are rare cases where
the situation is different. Unconditionally forcing the discardable flag
is therefore unhelpful. Avoid doing so when SEC_ALLOC is set, which
would in particular be the case when .reloc isn't (solely) linker-
generated.
While adjusting the comment, drop the wrong (stale?) following sentence:
.rsrc, as per its table entry, doesn't need to be writable. And
commenting on it wanting to be readable would then need to be repeated
for all other sections as well.
This is once again just so the target won't need excluding in a
forthcoming new testcase, which requires no padding at the end of at
least some of the sections.
In line with bfd's styp_to_sec_flags(), set SEC_ALLOC for code/data
sections. Tie the setting to SEC_LOAD, not avoid inadvertently producing
a .bss-like section.
For one, all PadLock insns depend on CR4.FXSR to be enabled, which means
they ought to be taking FXSR as a prereq.
Furthermore none of them permits a REPNE prefix; such forms are documented
to cause #UD. (This is mainly relevant for XSTORE, which doesn't include a
REP prefix in its base encoding. For the others this merely is a change in
what diagnostic is issued.)
Finally it is documented that an operand size prefix also causes #UD.
This code:
if (in->ptr[idx] == '!')
{
idx++;
sb_add_char (acc, in->ptr[idx++]);
}
and similar code in the other loop, blindly accessed the next element
of the string buffer without first checking idx against in->len,
leading to uninitialised accesses or buffer overruns. Fix that, and
tidy the loops so that the function always returns the index one past
the last char consumed. (It could return idx == in->len + 1).
* macro.c (getstring): Don't access past end of input string
buffer. Tidy loops. Don't return an index past in->len.
Work around a compilation error:
.../gas/config/tc-tic6x.c: In function 'tic6x_start_unwind_section':
.../gas/config/tc-tic6x.c:4632:17: error: offset '16' outside bounds of constant string [-Werror=array-bounds]
4632 | text_name += strlen (".gnu.linkonce.t.");
| ~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
observed with GCC 10.
Work around compilation errors:
.../gas/config/tc-ia64.c: In function 'declare_register_set':
.../gas/config/tc-ia64.c:5375:41: error: '%u' directive output may be truncated writing between 1 and 10 bytes into a region of size 8 [-Werror=format-truncation=]
5375 | snprintf (name, sizeof (name), "%s%u", prefix, i);
| ^~
.../gas/config/tc-ia64.c:5375:38: note: directive argument in the range [0, 4294967294]
5375 | snprintf (name, sizeof (name), "%s%u", prefix, i);
| ^~~~~~
.../gas/config/tc-ia64.c:5375:7: note: 'snprintf' output 2 or more bytes (assuming 11) into a destination of size 8
5375 | snprintf (name, sizeof (name), "%s%u", prefix, i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
observed with GCC 10. Pick 16 for a round 64-bit stack frame size.
This patch adds support for hypervisor control registers on AArch64,
available via the Generic Interrupt Controller v5 feature, and enabled
via the +gcie flag.
- ich_apr_el2
- ich_contextr_el2
- ich_hfgitr_el2
- ich_hfgrtr_el2
- ich_hfgwtr_el2
- ich_hppir_el2 (RO)
- ich_ppi_activer[0,1]_el2
- ich_ppi_dvir[0,1]_el2
- ich_ppi_enabler[0,1]_el2
- ich_ppi_pendr[0,1]_el2
- ich_ppi_priorityr[0,15]_el2
- ich_vctlr_el2
- ich_vmcr_el2
This patch adds support for PPI registers on AArch64, available via the
Generic Interrupt Controller v5 feature, and enabled via the +gcie flag.
- icc_ppi_cactiver[0,1]_el1
- icc_ppi_cpendr[0,1]_el1
- icc_ppi_enabler[0,1]_el1
- icc_ppi_hmr[0,1]_el1 (RO)
- icc_ppi_priorityr[0,15]_el1
- icc_ppi_sactiver[0,1]_el1
- icc_ppi_spendr[0,1]_el1
Also, the new system register 'icc_ppi_priorityr8_el1' clashed with the
encoding of 's3_0_c12_c15_0' used in a test for the generic syntax of
system registers using mrs and msr.
This patch replaces 's3_0_c12_c15_0' in the test by an unused encoding:
s3_7_c0_c15_0.
This patch adds support for 13 new AArch64 system registers for the CPU
interface, which are enabled on using Generic Interrupt Controller v5
(+gcie flag) feature:
- 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3
ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3.
- 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1,
ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1.
Note: the already-existing ID_AA64PFR2_EL1 register is required by the
GICv5 feature.
Add new instructions from the Generic Interrupt Controller, GICv5,
extension. These instructions are aliases to system instructions and are
the following:
* gic <operation>, <reg>
* gicr <reg>, <operation>
* gsb <operation>
Generic Interrupt Controller v5, GICv5, adds new system registers
and system instructions. These are enabled with the +gcie flag, where
gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt
Extension.
There is a make_expr_symbol in append_insn, which gets called from
macro_build, which is all over the place. Many of these set up an
expression without initialising all fields. Now the uninitialised
fields should not be accessed in a properly functioning assembler,
but I'm inclined to think anything copied ought to be initialised.
* config/tc-mips.c (fix_loongson2f_jump, load_register),
(add_got_offset, add_got_offset_hilo, macro_build_branch_likely),
(macro, mips16_macro, s_cpload, s_cpsetup, s_cprestore)
(s_cpreturn): Use structure initialiser to ensure all fields of
expression are initialised.
(load_address): Copy entire structure for the same reason.
There are many more places that copy an uninitialised expressionS to a
symbol via symbol_set_value_expression and make_expr_symbol. This
patch focuses on general gas code that does that, and a few backends.
Note that unlike the i386 case that oss-fuzz found, it is likely that
the tc-alpha.c, tc-ppc.c and tc-tic54x.c changes are not fixing bugs,
alpha and tic54x because they don't use X_md, ppc because it carefully
handles X_md. Also, as an example an O_constant expression should
only ever have its X_add_number field accessed, therefore the other
fields can stay uninitialised. However, I think that copying
uninitialised struct fields around is not good practice. If nothing
else it can be confusing when examining symbols under gdb.
I also replaced gen-sframe.c "#ifdef SFRAME_FRE_TYPE_SELECTION_OPT"
with "if (SFRAME_FRE_TYPE_SELECTION_OPT)" so code in the false
branches is compiled and thus less likely to bitrot. (As far as I can
see, SFRAME_FRE_TYPE_SELECTION_OPT is always 1.)
* cgen.c (expr_build_binary): Use structure initialiser to
ensure all fields of expression are initialised.
* config/obj-coff.c (obj_coff_val): Likewise.
* config/tc-alpha.c (add_to_link_pool): Likewise.
* config/tc-i386-intel.c (i386_intel_simplify): Likewise.
* config/tc-mips.c (fix_loongson2f_jump, load_register),
(load_address, add_got_offset, add_got_offset_hilo),
(macro_build_branch_likely, macro, mips16_macro),
(s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Likewise.
* config/tc-ppc.c (ppc_function): Likewise.
* config/tc-tic54x.c (tic54x_field): Likewise.
* dw2gencfi.c (output_cfi_insn): Likewise.
* expr.c (expr_build_uconstant): Likewise.
* read.c (s_mri_common): Likewise.
* gen-sframe.c (create_fre_start_addr_exp),
(create_func_info_exp, output_sframe_row_entry): Likewise.
Don't conditionally compile via SFRAME_FRE_TYPE_SELECTION_OPT.
* cgen.c (gas_cgen_parse_operand): Use md_expr_init_rest.
* config/tc-microblaze.c (microblaze_s_weakext): Likewise.
* ecoff.c (ecoff_directive_weakext, ecoff_stab): Likewise.
* read.c (pseudo_set): Likewise.
This patch removes clean_up_expression which runs just before operand()
returns. clean_up_expression sets as yet uninitialised fields of
expressionS. Well, it sets fields based on the value of X_op,
trusting that others have been written, and has one notable exception:
X_md is not initialised.
Instead initialise expressionS fully inside operand(), which is called
at the start of expr(), and introduce md_expr_init for the odd
backends that want to mess with X_md.
This is in response to an oss-fuzz report that read.c:pseudo_set calls
expr() leaving exp.X_md uninitialised and can copy that to a symbol
via symbol_set_value_expression. tc-i386-intel.c:565 is one place
that later tests the uninitialised X_md.
* config/tc-z80.h (md_expr_init, md_expr_init_rest): Define.
* config/tc-microblaze.h: Likewise.
* expr.c (clean_up_expression): Delete.
(operand): Init expression early.
(expr): Use md_expr_init_rest to init X_md when necessary.
tc-arc.c:tokenize_arguments tweaks expression() parsing, controlling
whether arc_parse_name does anything by setting X_op and X_md in the
expressionS argument passed to expression(). I want to change expr()
to always fully initialise its result, and that means either a special
expression initialiser for arc, or controlling arc_parse_name by some
other means. Since arc_parse_name already tests "assembling_insn" and
no other code does, change "assembling_insn" to directly control
arc_parse_name. Doing it this way also stops a possible uninitialised
access to right.X_op from expr() in arc_parse_name with current gas.
The next patch in this series will also stop such uninitialised
accesses.
* config/tc-arc.c (assembling_insn): Update comment.
(tokenize_arguments): Don't set X_op and X_md to control
expression(), instead just use assembling_insn.
(md_operand): Similarly.
(arc_parse_name): Don't test X_op and X_md.
(md_assemble): Don't set assembling_insn here.
While compilers default to v8plus on 32-bit Solaris/SPARC (gcc at least
since 4.4 in 2009, cc since at least Stdio 9 in 2010), gas still uses a
sparclite default. While this doesn't cause issue for gcc (it passes
-Av8plus as necessary), it repeatedly lead to problems in the testsuite
which has to be sprinkled with setting ASFLAGS accordingly since gas cannot
assemble the gcc output by default.
This patch switches the default to v8plus on Solaris to match gcc.
I had to introduce a new arch value, v8plus-32, matching v9-64, to allow
for this.
I cannot reliably tell if other SPARC targets are similarly affected, so
this patch restricts the change to Solaris.
Tested on sparc-sun-solaris2.11 and sparcv9-sun-solaris2.11.
2025-09-25 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
gas:
* config/tc-sparc.c (sparc_arch_table): Introduce v8plus-32.
* configure.tgt (generic_target) <sparc-*-solaris*>: Set arch to
v8plus-32 for 32-bit sparc.
* testsuite/gas/sparc/v8plus.rd, testsuite/gas/sparc/v8plus.s: New
test.
* testsuite/gas/sparc/sparc.exp: Run it on sparc*-*-solaris2*.
Many feature bits were unnecessarily added for features with no command
line flags, and effectively acted as aliases of the architecture version
bit they were linked to. The system register regating patch removed all
uses of these feature bits, so we can just remove them.
Historically we have been inconsistent and overly restrictive in our
choice of features to gate system register accesses. (Originally this
gating was always applied, but now it is disabled unless the
--menable-sysreg-checking option is specified).
This patch updates these constraints, following the principle that we
should only reject a system register access if it requires some
architecture feature or version whose corresponding command line
extension has not been enabled.
The most common change in this patch concerns system registers that
were:
- part of a feature FEAT_X with no corresponding command line extension;
- introduced in a newer architecture version ArmvX.Z;
- permitted to be implemented from an earlier version ArmvX.Y.
Previously these system registers tended to be gated on ArmvX.Z or left
ungated, but following the above principle they are now gated on ArmvX.Y
instead.
Most support for CSRE was removed from Binutils in 2021 after it was
removed from the architecture. This patch removes the remaining system
registers and test files.
Remove all test cases that expect spmzr_el0 to be readable, and remove
some redundant default macro values from armv9_5-a-sysregs.s while we're
there.
Add a read of spmzr_el0 to sysreg-diagnostics.s. This turns out to be
the first test for the "reading from a write-only register" note.
Also remove the recently added -menable-sysreg-checking option from this
test, both to simplify the addition of spmzr_el0 to the test, and to
verify that read/write diagnostics don't depend on that option.
The flag is unnecessary, because we can just unconditionally check the
features field every time. Having the information duplicated in two
separate fields makes it harder to maintain, particularly in the context
of the upcoming regating patch.
The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now
unused, so remove that as well.
This test runs with the assembler options '-march=armv9.4-a' twice.
Looking at the related tests in this set, this appears to be redundant
rather than a typo, so remove the second run.
