gas: aarch64: Add instructions for GICv5

Add new instructions from the Generic Interrupt Controller, GICv5,
extension. These instructions are aliases to system instructions and are
the following:

* gic <operation>, <reg>
* gicr <reg>, <operation>
* gsb <operation>
This commit is contained in:
Saurabh Jha
2025-07-23 10:41:53 +00:00
committed by saurabhjha
parent c3954fc3a1
commit a149def232
16 changed files with 413 additions and 2 deletions

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@@ -564,6 +564,9 @@ static htab_t aarch64_barrier_opt_hsh;
static htab_t aarch64_nzcv_hsh;
static htab_t aarch64_pldop_hsh;
static htab_t aarch64_hint_opt_hsh;
static htab_t aarch64_sys_ins_gic_hsh;
static htab_t aarch64_sys_ins_gicr_hsh;
static htab_t aarch64_sys_ins_gsb_hsh;
/* Stuff needed to resolve the label ambiguity
As:
@@ -8079,6 +8082,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SYSREG_TLBIP:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, true);
goto sys_reg_ins;
case AARCH64_OPND_GIC:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_ins_gic_hsh, false);
goto sys_reg_ins;
case AARCH64_OPND_GICR:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_ins_gicr_hsh, false);
goto sys_reg_ins;
case AARCH64_OPND_GSB:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_ins_gsb_hsh, false);
sys_reg_ins:
if (inst.base.operands[i].sysins_op == NULL)
{
@@ -10412,6 +10431,9 @@ md_begin (void)
aarch64_nzcv_hsh = str_htab_create ();
aarch64_pldop_hsh = str_htab_create ();
aarch64_hint_opt_hsh = str_htab_create ();
aarch64_sys_ins_gic_hsh = str_htab_create ();
aarch64_sys_ins_gicr_hsh = str_htab_create ();
aarch64_sys_ins_gsb_hsh = str_htab_create ();
fill_instruction_hash_table ();
@@ -10535,6 +10557,18 @@ md_begin (void)
aarch64_hint_options + i);
}
for (i = 0; aarch64_sys_ins_gic[i].name != NULL; i++)
sysreg_hash_insert (aarch64_sys_ins_gic_hsh, aarch64_sys_ins_gic[i].name,
aarch64_sys_ins_gic + i);
for (i = 0; aarch64_sys_ins_gicr[i].name != NULL; i++)
sysreg_hash_insert (aarch64_sys_ins_gicr_hsh, aarch64_sys_ins_gicr[i].name,
aarch64_sys_ins_gicr + i);
for (i = 0; aarch64_sys_ins_gsb[i].name != NULL; i++)
sysreg_hash_insert (aarch64_sys_ins_gsb_hsh, aarch64_sys_ins_gsb[i].name,
aarch64_sys_ins_gsb + i);
/* Set the cpu variant based on the command-line options. */
if (!mcpu_cpu_opt)
mcpu_cpu_opt = march_cpu_opt;

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@@ -0,0 +1,3 @@
#as:
#source: gcie.s
#error_output: gcie-bad.l

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@@ -0,0 +1,57 @@
[^ :]+: Assembler messages:
.*: Error: selected processor does not support `gic cdaff,x0'
.*: Error: selected processor does not support `gic cdaff,xzr'
.*: Error: selected processor does not support `gic cddi,x0'
.*: Error: selected processor does not support `gic cddi,xzr'
.*: Error: selected processor does not support `gic cddis,x0'
.*: Error: selected processor does not support `gic cddis,xzr'
.*: Error: selected processor does not support `gic cden,x0'
.*: Error: selected processor does not support `gic cden,xzr'
.*: Error: selected processor does not support `gic cdeoi,x0'
.*: Error: selected processor does not support `gic cdeoi,xzr'
.*: Error: selected processor does not support `gic cdhm,x0'
.*: Error: selected processor does not support `gic cdhm,xzr'
.*: Error: selected processor does not support `gic cdpend,x0'
.*: Error: selected processor does not support `gic cdpend,xzr'
.*: Error: selected processor does not support `gic cdpri,x0'
.*: Error: selected processor does not support `gic cdpri,xzr'
.*: Error: selected processor does not support `gic cdrcfg,x0'
.*: Error: selected processor does not support `gic cdrcfg,xzr'
.*: Error: selected processor does not support `gicr x0,cdia'
.*: Error: selected processor does not support `gicr xzr,cdia'
.*: Error: selected processor does not support `gicr x0,cdnmia'
.*: Error: selected processor does not support `gicr xzr,cdnmia'
.*: Error: selected processor does not support `gic vdaff,x0'
.*: Error: selected processor does not support `gic vdaff,xzr'
.*: Error: selected processor does not support `gic vddi,x0'
.*: Error: selected processor does not support `gic vddi,xzr'
.*: Error: selected processor does not support `gic vddis,x0'
.*: Error: selected processor does not support `gic vddis,xzr'
.*: Error: selected processor does not support `gic vden,x0'
.*: Error: selected processor does not support `gic vden,xzr'
.*: Error: selected processor does not support `gic vdhm,x0'
.*: Error: selected processor does not support `gic vdhm,xzr'
.*: Error: selected processor does not support `gic vdpend,x0'
.*: Error: selected processor does not support `gic vdpend,xzr'
.*: Error: selected processor does not support `gic vdpri,x0'
.*: Error: selected processor does not support `gic vdpri,xzr'
.*: Error: selected processor does not support `gic vdrcfg,x0'
.*: Error: selected processor does not support `gic vdrcfg,xzr'
.*: Error: selected processor does not support `gic ldaff,x0'
.*: Error: selected processor does not support `gic ldaff,xzr'
.*: Error: selected processor does not support `gic lddi,x0'
.*: Error: selected processor does not support `gic lddi,xzr'
.*: Error: selected processor does not support `gic lddis,x0'
.*: Error: selected processor does not support `gic lddis,xzr'
.*: Error: selected processor does not support `gic lden,x0'
.*: Error: selected processor does not support `gic lden,xzr'
.*: Error: selected processor does not support `gic ldhm,x0'
.*: Error: selected processor does not support `gic ldhm,xzr'
.*: Error: selected processor does not support `gic ldpend,x0'
.*: Error: selected processor does not support `gic ldpend,xzr'
.*: Error: selected processor does not support `gic ldpri,x0'
.*: Error: selected processor does not support `gic ldpri,xzr'
.*: Error: selected processor does not support `gic ldrcfg,x0'
.*: Error: selected processor does not support `gic ldrcfg,xzr'
.*: Error: selected processor does not support `gsb sys'
.*: Error: selected processor does not support `gsb ack'

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@@ -0,0 +1,3 @@
#as: -march=armv8-a+gcie
#source: gcie-illegal.s
#error_output: gcie-illegal.l

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@@ -0,0 +1,16 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gic cdaff'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `gic cdaff,'
[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gicr x0'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb'
[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gic cdaff,x0,x1'
[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gicr x0,cdia,x1'
[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `gsb ack,x0'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0,cdaff'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia,x0'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic cdwat,x0'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,cdwat'
[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb awt'

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@@ -0,0 +1,22 @@
// Less operands
gic cdaff
gic cdaff,
gicr x0
gicr x0,
gsb
// More operands
gic cdaff, x0, x1
gicr x0, cdia, x1
gsb ack, x0
// Incorrect operands
gic x0
gic x0, cdaff
gicr cdia
gicr cdia, x0
// Incorrect operation
gic cdwat, x0
gicr x0, cdwat
gsb awt

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@@ -0,0 +1,66 @@
#objdump: -dr
#as: -march=armv8-a+gcie
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
[^:]+: d508c160 gic cdaff, x0
[^:]+: d508c17f gic cdaff, xzr
[^:]+: d508c200 gic cddi, x0
[^:]+: d508c21f gic cddi, xzr
[^:]+: d508c100 gic cddis, x0
[^:]+: d508c11f gic cddis, xzr
[^:]+: d508c120 gic cden, x0
[^:]+: d508c13f gic cden, xzr
[^:]+: d508c1e0 gic cdeoi, x0
[^:]+: d508c1ff gic cdeoi, xzr
[^:]+: d508c220 gic cdhm, x0
[^:]+: d508c23f gic cdhm, xzr
[^:]+: d508c180 gic cdpend, x0
[^:]+: d508c19f gic cdpend, xzr
[^:]+: d508c140 gic cdpri, x0
[^:]+: d508c15f gic cdpri, xzr
[^:]+: d508c1a0 gic cdrcfg, x0
[^:]+: d508c1bf gic cdrcfg, xzr
[^:]+: d508c300 gicr x0, cdia
[^:]+: d508c31f gicr xzr, cdia
[^:]+: d508c320 gicr x0, cdnmia
[^:]+: d508c33f gicr xzr, cdnmia
[^:]+: d50cc160 gic vdaff, x0
[^:]+: d50cc17f gic vdaff, xzr
[^:]+: d50cc200 gic vddi, x0
[^:]+: d50cc21f gic vddi, xzr
[^:]+: d50cc100 gic vddis, x0
[^:]+: d50cc11f gic vddis, xzr
[^:]+: d50cc120 gic vden, x0
[^:]+: d50cc13f gic vden, xzr
[^:]+: d50cc220 gic vdhm, x0
[^:]+: d50cc23f gic vdhm, xzr
[^:]+: d50cc180 gic vdpend, x0
[^:]+: d50cc19f gic vdpend, xzr
[^:]+: d50cc140 gic vdpri, x0
[^:]+: d50cc15f gic vdpri, xzr
[^:]+: d50cc1a0 gic vdrcfg, x0
[^:]+: d50cc1bf gic vdrcfg, xzr
[^:]+: d50ec160 gic ldaff, x0
[^:]+: d50ec17f gic ldaff, xzr
[^:]+: d50ec200 gic lddi, x0
[^:]+: d50ec21f gic lddi, xzr
[^:]+: d50ec100 gic lddis, x0
[^:]+: d50ec11f gic lddis, xzr
[^:]+: d50ec120 gic lden, x0
[^:]+: d50ec13f gic lden, xzr
[^:]+: d50ec220 gic ldhm, x0
[^:]+: d50ec23f gic ldhm, xzr
[^:]+: d50ec180 gic ldpend, x0
[^:]+: d50ec19f gic ldpend, xzr
[^:]+: d50ec140 gic ldpri, x0
[^:]+: d50ec15f gic ldpri, xzr
[^:]+: d50ec1a0 gic ldrcfg, x0
[^:]+: d50ec1bf gic ldrcfg, xzr
[^:]+: d508c01f gsb sys
[^:]+: d508c03f gsb ack
[^:]+: d508c000 sys #0, C12, C0, #0, x0
[^:]+: d508c020 sys #0, C12, C0, #1, x0

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@@ -0,0 +1,117 @@
// GIC CDAFF
gic cdaff, x0
gic cdaff, xzr
// GIC CDDI
gic cddi, x0
gic cddi, xzr
// GIC CDDIS
gic cddis, x0
gic cddis, xzr
// GIC CDEN
gic cden, x0
gic cden, xzr
// GIC CDEOI
gic cdeoi, x0
gic cdeoi, xzr
// GIC CDHM
gic cdhm, x0
gic cdhm, xzr
// GIC CDPEND
gic cdpend, x0
gic cdpend, xzr
// GIC CDPRI
gic cdpri, x0
gic cdpri, xzr
// GIC CDRCFG
gic cdrcfg, x0
gic cdrcfg, xzr
// GICR CDIA
gicr x0, cdia
gicr xzr, cdia
// GICR CDNMIA
gicr x0, cdnmia
gicr xzr, cdnmia
// GIC VDAFF
gic vdaff, x0
gic vdaff, xzr
// GIC VDDI
gic vddi, x0
gic vddi, xzr
// GIC VDDIS
gic vddis, x0
gic vddis, xzr
// GIC VDEN
gic vden, x0
gic vden, xzr
// GIC VDHM
gic vdhm, x0
gic vdhm, xzr
// GIC VDPEND
gic vdpend, x0
gic vdpend, xzr
// GIC VDPRI
gic vdpri, x0
gic vdpri, xzr
// GIC VDRCFG
gic vdrcfg, x0
gic vdrcfg, xzr
// GIC LDAFF
gic ldaff, x0
gic ldaff, xzr
// GIC LDDI
gic lddi, x0
gic lddi, xzr
// GIC LDDIS
gic lddis, x0
gic lddis, xzr
// GIC LDEN
gic lden, x0
gic lden, xzr
// GIC LDHM
gic ldhm, x0
gic ldhm, xzr
// GIC LDPEND
gic ldpend, x0
gic ldpend, xzr
// GIC LDPRI
gic ldpri, x0
gic ldpri, xzr
// GIC LDRCFG
gic ldrcfg, x0
gic ldrcfg, xzr
// GSB SYS
gsb sys
// GSB ACK
gsb ack
// Don't disassemble gsb with nonzero Rt
sys #0, c12, c0, #0, x0
sys #0, c12, c0, #1, x0