Matthew Brecknell 9ec5df5fa8 riscv: more efficient clz and ctz
For RISC-V platforms that do not provide machine instructions to count
leading and trailing zeros, this commit includes more efficient library
functions. For verification, we expose the bodies of the functions to
the proofs.

Kernel config options `CLZ_BUILTIN` and `CTZ_BUILTIN` allow selection of
whether compiler builtin functions should be used. These are only
supported on platforms where the builtin compiles to inline assembly. By
default, the options are on for all platforms except RISC-V.

Signed-off-by: Matthew Brecknell <Matthew.Brecknell@data61.csiro.au>
2021-03-23 14:43:34 +11:00
2021-03-23 14:43:34 +11:00
2021-03-23 14:43:34 +11:00
2021-03-23 14:43:34 +11:00
2021-03-22 11:41:03 +11:00
2020-06-17 17:27:20 +08:00
2020-11-06 18:29:45 +11:00
2020-04-01 17:23:36 +08:00
2021-03-23 14:43:34 +11:00
2020-04-07 19:35:33 +10:00
2020-08-26 14:21:35 +10:00
2020-11-06 18:29:45 +11:00

The seL4 microkernel

This project contains the source code of seL4 microkernel.

For details about the seL4 microkernel, including details about its formal correctness proof, please see the sel4.systems website and associated FAQ.

DOIs for citing recent releases of this repository:

  • DOI

We welcome contributions to seL4. Please see the website for information on how to contribute.

This repository is usually not used in isolation, but as part of the build system in a larger project.

seL4 Basics

Community

Manual

A hosted version of the manual for the most recent release can be found here.

A web version of the API can be found here

Repository Overview

  • include and src: C and ASM source code of seL4
  • tools: build tools
  • libsel4: C bindings for the seL4 ABI
  • manual: LaTeX sources of the seL4 reference manual

Build Instructions

See the seL4 website for build instructions.

Status

A list of releases and current project status can be found under seL4 releases.

Description
The seL4 microkernel
Readme 22 MiB
Languages
C 72.6%
Python 9.5%
CMake 6.3%
TeX 5.8%
Assembly 2.7%
Other 3.1%